Skip to content

Commit bffc6d9

Browse files
tinebptinebp
committed
enabling Vivado's asynchronous bram suppot via direct netlist transformation
1 parent ce510d7 commit bffc6d9

15 files changed

+1391
-273
lines changed

‎configure

+4-4
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,7 @@ copy_files() {
6565
filename_no_ext="${filename%.in}"
6666
dest_file="$dest_dir/$filename_no_ext"
6767
mkdir -p "$dest_dir"
68-
sed "s|@VORTEX_HOME@|$SCRIPT_DIR|g; s|@XLEN@|$XLEN|g; s|@TOOLDIR@|$TOOLDIR|g; s|@OSVERSION@|$OSVERSION|g; s|@INSTALLDIR@|$PREFIX|g; s|@CURRENTDIR@|$CURRENT_DIR|g" "$file" > "$dest_file"
68+
sed "s|@VORTEX_HOME@|$SOURCE_DIR|g; s|@XLEN@|$XLEN|g; s|@TOOLDIR@|$TOOLDIR|g; s|@OSVERSION@|$OSVERSION|g; s|@INSTALLDIR@|$PREFIX|g; s|@BUILDDIR@|$CURRENT_DIR|g" "$file" > "$dest_file"
6969
# apply permissions to bash scripts
7070
read -r firstline < "$dest_file"
7171
if [[ "$firstline" =~ ^#!.*bash ]]; then
@@ -169,8 +169,8 @@ fi
169169
SUBDIRS=("." "!ci" "!perf" "hw*" "kernel*" "runtime*" "sim*" "tests*")
170170

171171
# Get the directory of the script
172-
SCRIPT_DIR="$( cd -- "$( dirname -- "${BASH_SOURCE[0]}" )" &> /dev/null && pwd )"
172+
SOURCE_DIR="$( cd -- "$( dirname -- "${BASH_SOURCE[0]}" )" &> /dev/null && pwd )"
173173

174-
THIRD_PARTY_DIR=$SCRIPT_DIR/third_party
174+
THIRD_PARTY_DIR=$SOURCE_DIR/third_party
175175

176-
copy_files "$SCRIPT_DIR" "$CURRENT_DIR"
176+
copy_files "$SOURCE_DIR" "$CURRENT_DIR"

‎hw/rtl/VX_platform.vh

+3-3
Original file line numberDiff line numberDiff line change
@@ -160,32 +160,32 @@ endgenerate
160160
`ifdef QUARTUS
161161
`define MAX_FANOUT 8
162162
`define MAX_LUTRAM 1024
163-
`define IF_DATA_SIZE(x) $bits(x.data)
164163
`define USE_BLOCK_BRAM (* ramstyle = "block" *)
165164
`define USE_FAST_BRAM (* ramstyle = "MLAB, no_rw_check" *)
166165
`define NO_RW_RAM_CHECK (* altera_attribute = "-name add_pass_through_logic_to_inferred_rams off" *)
167166
`define DISABLE_BRAM (* ramstyle = "logic" *)
168167
`define PRESERVE_NET (* preserve *)
168+
`define BLACKBOX_CELL (* black_box *)
169169
`define STRING string
170170
`elsif VIVADO
171171
`define MAX_FANOUT 8
172172
`define MAX_LUTRAM 1024
173-
`define IF_DATA_SIZE(x) $bits(x.data)
174173
`define USE_BLOCK_BRAM (* ram_style = "block" *)
175174
`define USE_FAST_BRAM (* ram_style = "distributed" *)
176175
`define NO_RW_RAM_CHECK (* rw_addr_collision = "no" *)
177176
`define DISABLE_BRAM (* ram_style = "registers" *)
178177
`define PRESERVE_NET (* keep = "true" *)
178+
`define BLACKBOX_CELL (* black_box *)
179179
`define STRING
180180
`else
181181
`define MAX_FANOUT 8
182182
`define MAX_LUTRAM 1024
183-
`define IF_DATA_SIZE(x) x.DATA_WIDTH
184183
`define USE_BLOCK_BRAM
185184
`define USE_FAST_BRAM
186185
`define NO_RW_RAM_CHECK
187186
`define DISABLE_BRAM
188187
`define PRESERVE_NET
188+
`define BLACKBOX_CELL
189189
`define STRING string
190190
`endif
191191

‎hw/rtl/cache/VX_cache_top.sv

+6-6
Original file line numberDiff line numberDiff line change
@@ -31,28 +31,28 @@ module VX_cache_top import VX_gpu_pkg::*; #(
3131
parameter WORD_SIZE = 16,
3232

3333
// Core Response Queue Size
34-
parameter CRSQ_SIZE = 4,
34+
parameter CRSQ_SIZE = 8,
3535
// Miss Reserv Queue Knob
3636
parameter MSHR_SIZE = 16,
3737
// Memory Response Queue Size
38-
parameter MRSQ_SIZE = 4,
38+
parameter MRSQ_SIZE = 8,
3939
// Memory Request Queue Size
40-
parameter MREQ_SIZE = 4,
40+
parameter MREQ_SIZE = 8,
4141

4242
// Enable cache writeable
4343
parameter WRITE_ENABLE = 1,
4444

4545
// Enable cache writeback
46-
parameter WRITEBACK = 0,
46+
parameter WRITEBACK = 1,
4747

4848
// Enable dirty bytes on writeback
49-
parameter DIRTY_BYTES = 0,
49+
parameter DIRTY_BYTES = 1,
5050

5151
// Request debug identifier
5252
parameter UUID_WIDTH = 0,
5353

5454
// core request tag size
55-
parameter TAG_WIDTH = 16,
55+
parameter TAG_WIDTH = 32,
5656

5757
// Core response output buffer
5858
parameter CORE_OUT_BUF = 3,

‎hw/rtl/libs/VX_async_ram_patch.sv

+158
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,158 @@
1+
// Copyright © 2019-2023
2+
//
3+
// Licensed under the Apache License, Version 2.0 (the "License");
4+
// you may not use this file except in compliance with the License.
5+
// You may obtain a copy of the License at
6+
// http://www.apache.org/licenses/LICENSE-2.0
7+
//
8+
// Unless required by applicable law or agreed to in writing, software
9+
// distributed under the License is distributed on an "AS IS" BASIS,
10+
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
11+
// See the License for the specific language governing permissions and
12+
// limitations under the License.
13+
14+
`include "VX_platform.vh"
15+
16+
`define RAM_WRITE_WREN for (integer i = 0; i < WRENW; ++i) begin \
17+
if (wren[i]) begin \
18+
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; \
19+
end \
20+
end
21+
22+
`define RAM_INITIALIZATION \
23+
if (INIT_ENABLE != 0) begin : g_init \
24+
if (INIT_FILE != "") begin : g_file \
25+
initial $readmemh(INIT_FILE, ram); \
26+
end else begin : g_value \
27+
initial begin \
28+
for (integer i = 0; i < SIZE; ++i) begin : g_i \
29+
ram[i] = INIT_VALUE; \
30+
end \
31+
end \
32+
end \
33+
end
34+
35+
`define RAM_BYPASS(__d) \
36+
reg [DATAW-1:0] bypass_data_r; \
37+
reg bypass_valid_r; \
38+
always @(posedge clk) begin \
39+
bypass_valid_r <= read_s && write && (raddr_s == waddr); \
40+
bypass_data_r <= wdata; \
41+
end \
42+
assign __d = bypass_valid_r ? bypass_data_r : rdata_r
43+
44+
`TRACING_OFF
45+
module VX_async_ram_patch #(
46+
parameter DATAW = 1,
47+
parameter SIZE = 1,
48+
parameter WRENW = 1,
49+
parameter DUAL_PORT = 0,
50+
parameter INIT_ENABLE = 0,
51+
parameter INIT_FILE = "",
52+
parameter [DATAW-1:0] INIT_VALUE = 0,
53+
parameter ADDRW = `LOG2UP(SIZE)
54+
) (
55+
input wire clk,
56+
input wire reset,
57+
input wire read,
58+
input wire write,
59+
input wire [WRENW-1:0] wren,
60+
input wire [ADDRW-1:0] waddr,
61+
input wire [DATAW-1:0] wdata,
62+
input wire [ADDRW-1:0] raddr,
63+
output wire [DATAW-1:0] rdata
64+
);
65+
localparam WSELW = DATAW / WRENW;
66+
67+
`UNUSED_VAR (reset)
68+
69+
(* keep = "true" *) wire [ADDRW-1:0] raddr_w, raddr_s;
70+
(* keep = "true" *) wire read_s, is_raddr_reg;
71+
72+
assign raddr_w = raddr;
73+
74+
VX_placeholder #(
75+
.I (ADDRW),
76+
.O (ADDRW + 1 + 1)
77+
) placeholder (
78+
.in (raddr_w),
79+
.out ({raddr_s, read_s, is_raddr_reg})
80+
);
81+
82+
// synchroneous ram
83+
84+
wire [DATAW-1:0] rdata_s;
85+
86+
if (WRENW != 1) begin : g_wren_sync_ram
87+
`USE_BLOCK_BRAM reg [DATAW-1:0] ram [0:SIZE-1];
88+
reg [DATAW-1:0] rdata_r;
89+
`RAM_INITIALIZATION
90+
always @(posedge clk) begin
91+
if (read_s || write) begin
92+
if (write) begin
93+
`RAM_WRITE_WREN
94+
end
95+
rdata_r <= ram[raddr_s];
96+
end
97+
end
98+
`RAM_BYPASS(rdata_s);
99+
end else begin : g_no_wren_sync_ram
100+
`USE_BLOCK_BRAM reg [DATAW-1:0] ram [0:SIZE-1];
101+
reg [DATAW-1:0] rdata_r;
102+
`RAM_INITIALIZATION
103+
`UNUSED_VAR (wren)
104+
always @(posedge clk) begin
105+
if (read_s || write) begin
106+
if (write) begin
107+
ram[waddr] <= wdata;
108+
end
109+
rdata_r <= ram[raddr_s];
110+
end
111+
end
112+
`RAM_BYPASS(rdata_s);
113+
end
114+
115+
// asynchronous ram (fallback)
116+
117+
wire [DATAW-1:0] rdata_a;
118+
119+
if (DUAL_PORT != 0) begin : g_dp_async_ram
120+
reg [DATAW-1:0] ram [0:SIZE-1];
121+
`RAM_INITIALIZATION
122+
if (WRENW != 1) begin : g_wren
123+
always @(posedge clk) begin
124+
if (write) begin
125+
`RAM_WRITE_WREN
126+
end
127+
end
128+
end else begin : g_no_wren
129+
always @(posedge clk) begin
130+
if (write) begin
131+
ram[waddr] <= wdata;
132+
end
133+
end
134+
end
135+
assign rdata_a = ram[raddr];
136+
end else begin : g_sp_async_ram
137+
reg [DATAW-1:0] ram [0:SIZE-1];
138+
`RAM_INITIALIZATION
139+
if (WRENW != 1) begin : g_wren
140+
always @(posedge clk) begin
141+
if (write) begin
142+
`RAM_WRITE_WREN
143+
end
144+
end
145+
end else begin : g_no_wren
146+
always @(posedge clk) begin
147+
if (write) begin
148+
ram[waddr] <= wdata;
149+
end
150+
end
151+
end
152+
assign rdata_a = ram[waddr];
153+
end
154+
155+
assign rdata = is_raddr_reg ? rdata_s : rdata_a;
156+
157+
endmodule
158+
`TRACING_ON

0 commit comments

Comments
 (0)