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tinebptinebp
committed
minor updates
1 parent a389606 commit fa1fd39

23 files changed

+37
-39
lines changed

Diff for: ‎hw/rtl/cache/VX_cache.sv

+1-1
Original file line numberDiff line numberDiff line change
@@ -136,7 +136,7 @@ module VX_cache import VX_gpu_pkg::*; #(
136136
wire [NUM_REQS-1:0][TAG_WIDTH-1:0] core_rsp_tag_s;
137137
wire [NUM_REQS-1:0] core_rsp_ready_s;
138138

139-
for (genvar i = 0; i < NUM_REQS; ++i) begin
139+
for (genvar i = 0; i < NUM_REQS; ++i) begin : core_rsp_bufs
140140
VX_elastic_buffer #(
141141
.DATAW (`CS_WORD_WIDTH + TAG_WIDTH),
142142
.SIZE (CORE_RSP_REG_DISABLE ? `TO_OUT_BUF_SIZE(CORE_OUT_BUF) : 0),

Diff for: ‎hw/rtl/cache/VX_cache_cluster.sv

+1-1
Original file line numberDiff line numberDiff line change
@@ -102,7 +102,7 @@ module VX_cache_cluster import VX_gpu_pkg::*; #(
102102
.TAG_WIDTH (ARB_TAG_WIDTH)
103103
) arb_core_bus_if[NUM_CACHES * NUM_REQS]();
104104

105-
for (genvar i = 0; i < NUM_REQS; ++i) begin
105+
for (genvar i = 0; i < NUM_REQS; ++i) begin : core_arbs
106106
VX_mem_bus_if #(
107107
.DATA_SIZE (WORD_SIZE),
108108
.TAG_WIDTH (TAG_WIDTH)

Diff for: ‎hw/rtl/cache/VX_cache_tags.sv

+1-1
Original file line numberDiff line numberDiff line change
@@ -100,7 +100,7 @@ module VX_cache_tags #(
100100
wire fill_s = fill && (!WRITEBACK || ~stall);
101101
wire flush_s = flush && (!WRITEBACK || ~stall);
102102

103-
for (genvar i = 0; i < NUM_WAYS; ++i) begin : ways
103+
for (genvar i = 0; i < NUM_WAYS; ++i) begin : tag_stores
104104

105105
wire do_fill = fill_s && evict_way[i];
106106
wire do_flush = flush_s && (!WRITEBACK || way_sel[i]); // flush the whole line in writethrough mode

Diff for: ‎hw/rtl/core/VX_alu_unit.sv

+1-1
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,7 @@ module VX_alu_unit #(
5555
.NUM_LANES (NUM_LANES)
5656
) per_block_commit_if[BLOCK_SIZE]();
5757

58-
for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : alu_blocks
58+
for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : alus
5959

6060
`RESET_RELAY_EN (block_reset, reset, (BLOCK_SIZE > 1));
6161

Diff for: ‎hw/rtl/core/VX_commit.sv

+1-1
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@ module VX_commit import VX_gpu_pkg::*; #(
4141
wire [`ISSUE_WIDTH-1:0][`NUM_THREADS-1:0] per_issue_commit_tmask;
4242
wire [`ISSUE_WIDTH-1:0] per_issue_commit_eop;
4343

44-
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
44+
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin : commit_arbs
4545

4646
wire [`NUM_EX_UNITS-1:0] valid_in;
4747
wire [`NUM_EX_UNITS-1:0][DATAW-1:0] data_in;

Diff for: ‎hw/rtl/core/VX_dispatch.sv

+1-1
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@ module VX_dispatch import VX_gpu_pkg::*; #(
5353
wire [`NUM_EX_UNITS-1:0] operands_ready_in;
5454
assign operands_if.ready = operands_ready_in[operands_if.data.ex_type];
5555

56-
for (genvar i = 0; i < `NUM_EX_UNITS; ++i) begin
56+
for (genvar i = 0; i < `NUM_EX_UNITS; ++i) begin : buffers
5757
VX_elastic_buffer #(
5858
.DATAW (DATAW),
5959
.SIZE (2),

Diff for: ‎hw/rtl/core/VX_fetch.sv

+1-1
Original file line numberDiff line numberDiff line change
@@ -71,7 +71,7 @@ module VX_fetch import VX_gpu_pkg::*; #(
7171
// This resolves potential deadlock if ibuffer fills and the LSU stalls the execute stage due to pending dcache requests.
7272
// This issue is particularly prevalent when the icache and dcache are disabled and both requests share the same bus.
7373
wire [`NUM_WARPS-1:0] pending_ibuf_full;
74-
for (genvar i = 0; i < `NUM_WARPS; ++i) begin
74+
for (genvar i = 0; i < `NUM_WARPS; ++i) begin : pending_reads
7575
VX_pending_size #(
7676
.SIZE (`IBUF_SIZE)
7777
) pending_reads (

Diff for: ‎hw/rtl/core/VX_fpu_unit.sv

+1-1
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@ module VX_fpu_unit import VX_fpu_pkg::*; #(
5353
.NUM_LANES (NUM_LANES)
5454
) per_block_commit_if[BLOCK_SIZE]();
5555

56-
for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : fpu_blocks
56+
for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : fpus
5757
`UNUSED_VAR (per_block_execute_if[block_idx].data.tid)
5858
`UNUSED_VAR (per_block_execute_if[block_idx].data.wb)
5959

Diff for: ‎hw/rtl/core/VX_gather_unit.sv

+1-1
Original file line numberDiff line numberDiff line change
@@ -74,7 +74,7 @@ module VX_gather_unit import VX_gpu_pkg::*; #(
7474
assign commit_in_ready[i] = commit_out_ready[commit_in_isw[i]];
7575
end
7676

77-
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
77+
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin: out_bufs
7878
VX_commit_if #(
7979
.NUM_LANES (NUM_LANES)
8080
) commit_tmp_if();

Diff for: ‎hw/rtl/core/VX_ibuffer.sv

+1-1
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ module VX_ibuffer import VX_gpu_pkg::*; #(
3535
wire [PER_ISSUE_WARPS-1:0] ibuf_ready_in;
3636
assign decode_if.ready = ibuf_ready_in[decode_if.data.wid];
3737

38-
for (genvar w = 0; w < PER_ISSUE_WARPS; ++w) begin : ibuf_slices
38+
for (genvar w = 0; w < PER_ISSUE_WARPS; ++w) begin : instr_bufs
3939
VX_elastic_buffer #(
4040
.DATAW (DATAW),
4141
.SIZE (`IBUF_SIZE),

Diff for: ‎hw/rtl/core/VX_lsu_unit.sv

+1-1
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ module VX_lsu_unit import VX_gpu_pkg::*; #(
5454
.NUM_LANES (NUM_LANES)
5555
) per_block_commit_if[BLOCK_SIZE]();
5656

57-
for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : lsu_blocks
57+
for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : lsus
5858

5959
`RESET_RELAY_EN (slice_reset, reset, (BLOCK_SIZE > 1));
6060

Diff for: ‎hw/rtl/core/VX_mem_unit.sv

+4-4
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,7 @@ module VX_mem_unit import VX_gpu_pkg::*; #(
4545
.TAG_WIDTH (LSU_TAG_WIDTH)
4646
) lsu_lmem_if[`NUM_LSU_BLOCKS]();
4747

48-
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : demux_slices
48+
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : lmem_switches
4949
VX_lmem_switch #(
5050
.REQ0_OUT_BUF (3),
5151
.REQ1_OUT_BUF (0),
@@ -65,7 +65,7 @@ module VX_mem_unit import VX_gpu_pkg::*; #(
6565
.TAG_WIDTH (LSU_TAG_WIDTH)
6666
) lmem_bus_if[LSU_NUM_REQS]();
6767

68-
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : lmem_adapter_slices
68+
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : lmem_adapters
6969
VX_mem_bus_if #(
7070
.DATA_SIZE (LSU_WORD_SIZE),
7171
.TAG_WIDTH (LSU_TAG_WIDTH)
@@ -131,7 +131,7 @@ module VX_mem_unit import VX_gpu_pkg::*; #(
131131

132132
if (LSU_WORD_SIZE != DCACHE_WORD_SIZE) begin : coalescer_if
133133

134-
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : coalescer_blocks
134+
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : coalescers
135135

136136
`RESET_RELAY (mem_coalescer_reset, reset);
137137

@@ -195,7 +195,7 @@ module VX_mem_unit import VX_gpu_pkg::*; #(
195195

196196
end
197197

198-
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : dcache_adapter_slices
198+
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : dcache_adapters
199199

200200
VX_mem_bus_if #(
201201
.DATA_SIZE (DCACHE_WORD_SIZE),

Diff for: ‎hw/rtl/core/VX_operands.sv

+1-1
Original file line numberDiff line numberDiff line change
@@ -246,7 +246,7 @@ module VX_operands import VX_gpu_pkg::*; #(
246246
assign gpr_wr_bank_idx = '0;
247247
end
248248

249-
for (genvar b = 0; b < NUM_BANKS; ++b) begin
249+
for (genvar b = 0; b < NUM_BANKS; ++b) begin : gpr_rams
250250
wire gpr_wr_enabled;
251251
if (BANK_SEL_BITS != 0) begin
252252
assign gpr_wr_enabled = writeback_if.valid

Diff for: ‎hw/rtl/core/VX_schedule.sv

+1-1
Original file line numberDiff line numberDiff line change
@@ -379,7 +379,7 @@ module VX_schedule import VX_gpu_pkg::*; #(
379379

380380
`RESET_RELAY (pending_instr_reset, reset);
381381

382-
for (genvar i = 0; i < `NUM_WARPS; ++i) begin
382+
for (genvar i = 0; i < `NUM_WARPS; ++i) begin : pending_sizes
383383
VX_pending_size #(
384384
.SIZE (4096),
385385
.ALM_EMPTY (1)

Diff for: ‎hw/rtl/core/VX_scoreboard.sv

+1-1
Original file line numberDiff line numberDiff line change
@@ -101,7 +101,7 @@ module VX_scoreboard import VX_gpu_pkg::*; #(
101101
end
102102
`endif
103103

104-
for (genvar w = 0; w < PER_ISSUE_WARPS; ++w) begin
104+
for (genvar w = 0; w < PER_ISSUE_WARPS; ++w) begin : stanging_bufs
105105
VX_pipe_buffer #(
106106
.DATAW (DATAW)
107107
) stanging_buf (

Diff for: ‎hw/rtl/core/VX_split_join.sv

+1-1
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,7 @@ module VX_split_join import VX_gpu_pkg::*; #(
4545
wire ipdom_push = valid && split.valid && split.is_dvg;
4646
wire ipdom_pop = valid && sjoin.valid && sjoin_is_dvg;
4747

48-
for (genvar i = 0; i < `NUM_WARPS; ++i) begin : ipdom_slices
48+
for (genvar i = 0; i < `NUM_WARPS; ++i) begin : ipdom_stacks
4949
VX_ipdom_stack #(
5050
.WIDTH (`NUM_THREADS+`PC_BITS),
5151
.DEPTH (`DV_STACK_SIZE)

Diff for: ‎hw/rtl/fpu/VX_fpu_cvt.sv

+1-1
Original file line numberDiff line numberDiff line change
@@ -86,7 +86,7 @@ module VX_fpu_cvt import VX_fpu_pkg::*; #(
8686
assign fflags_out[i] = data_out[i][32 +: `FP_FLAGS_BITS];
8787
end
8888

89-
for (genvar i = 0; i < NUM_PES; ++i) begin
89+
for (genvar i = 0; i < NUM_PES; ++i) begin : fcvt_units
9090
VX_fcvt_unit #(
9191
.LATENCY (`LATENCY_FCVT),
9292
.OUT_REG (1)

Diff for: ‎hw/rtl/fpu/VX_fpu_div.sv

+3-3
Original file line numberDiff line numberDiff line change
@@ -94,7 +94,7 @@ module VX_fpu_div import VX_fpu_pkg::*; #(
9494

9595
`ifdef QUARTUS
9696

97-
for (genvar i = 0; i < NUM_PES; ++i) begin
97+
for (genvar i = 0; i < NUM_PES; ++i) begin : fdivs
9898
acl_fdiv fdiv (
9999
.clk (clk),
100100
.areset (1'b0),
@@ -112,7 +112,7 @@ module VX_fpu_div import VX_fpu_pkg::*; #(
112112

113113
`elsif VIVADO
114114

115-
for (genvar i = 0; i < NUM_PES; ++i) begin
115+
for (genvar i = 0; i < NUM_PES; ++i) begin : fdivs
116116
wire [3:0] tuser;
117117
xil_fdiv fdiv (
118118
.aclk (clk),
@@ -134,7 +134,7 @@ module VX_fpu_div import VX_fpu_pkg::*; #(
134134

135135
`else
136136

137-
for (genvar i = 0; i < NUM_PES; ++i) begin
137+
for (genvar i = 0; i < NUM_PES; ++i) begin fdivs
138138
reg [63:0] r;
139139
`UNUSED_VAR (r)
140140
fflags_t f;

Diff for: ‎hw/rtl/fpu/VX_fpu_fma.sv

+3-3
Original file line numberDiff line numberDiff line change
@@ -125,7 +125,7 @@ module VX_fpu_fma import VX_fpu_pkg::*; #(
125125

126126
`ifdef QUARTUS
127127

128-
for (genvar i = 0; i < NUM_PES; ++i) begin
128+
for (genvar i = 0; i < NUM_PES; ++i) begin : fmadds
129129
acl_fmadd fmadd (
130130
.clk (clk),
131131
.areset (1'b0),
@@ -143,7 +143,7 @@ module VX_fpu_fma import VX_fpu_pkg::*; #(
143143

144144
`elsif VIVADO
145145

146-
for (genvar i = 0; i < NUM_PES; ++i) begin
146+
for (genvar i = 0; i < NUM_PES; ++i) begin : fmas
147147
wire [2:0] tuser;
148148

149149
xil_fma fma (
@@ -168,7 +168,7 @@ module VX_fpu_fma import VX_fpu_pkg::*; #(
168168

169169
`else
170170

171-
for (genvar i = 0; i < NUM_PES; ++i) begin
171+
for (genvar i = 0; i < NUM_PES; ++i) begin : fmas
172172
reg [63:0] r;
173173
`UNUSED_VAR (r)
174174
fflags_t f;

Diff for: ‎hw/rtl/fpu/VX_fpu_fpnew.sv

+1-1
Original file line numberDiff line numberDiff line change
@@ -162,7 +162,7 @@ module VX_fpu_fpnew
162162
end
163163

164164
`UNUSED_VAR (mask_in)
165-
for (genvar i = 0; i < NUM_LANES; ++i) begin
165+
for (genvar i = 0; i < NUM_LANES; ++i) begin : fpnew_cores
166166
wire [(TAG_WIDTH+1)-1:0] fpu_tag;
167167
wire fpu_valid_out_uq;
168168
wire fpu_ready_in_uq;

Diff for: ‎hw/rtl/fpu/VX_fpu_ncp.sv

+1-1
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,7 @@ module VX_fpu_ncp import VX_fpu_pkg::*; #(
9191
assign fflags_out[i] = data_out[i][32 +: `FP_FLAGS_BITS];
9292
end
9393

94-
for (genvar i = 0; i < NUM_PES; ++i) begin
94+
for (genvar i = 0; i < NUM_PES; ++i) begin : fncp_units
9595
VX_fncp_unit #(
9696
.LATENCY (`LATENCY_FNCP),
9797
.OUT_REG (1)

Diff for: ‎hw/rtl/fpu/VX_fpu_sqrt.sv

+3-3
Original file line numberDiff line numberDiff line change
@@ -88,7 +88,7 @@ module VX_fpu_sqrt import VX_fpu_pkg::*; #(
8888

8989
`ifdef QUARTUS
9090

91-
for (genvar i = 0; i < NUM_PES; ++i) begin
91+
for (genvar i = 0; i < NUM_PES; ++i) begin : fsqrts
9292
acl_fsqrt fsqrt (
9393
.clk (clk),
9494
.areset (1'b0),
@@ -105,7 +105,7 @@ module VX_fpu_sqrt import VX_fpu_pkg::*; #(
105105

106106
`elsif VIVADO
107107

108-
for (genvar i = 0; i < NUM_PES; ++i) begin
108+
for (genvar i = 0; i < NUM_PES; ++i) begin : fsqrts
109109
wire tuser;
110110

111111
xil_fsqrt fsqrt (
@@ -126,7 +126,7 @@ module VX_fpu_sqrt import VX_fpu_pkg::*; #(
126126

127127
`else
128128

129-
for (genvar i = 0; i < NUM_PES; ++i) begin
129+
for (genvar i = 0; i < NUM_PES; ++i) begin : fsqrts
130130
reg [63:0] r;
131131
`UNUSED_VAR (r)
132132
fflags_t f;

Diff for: ‎hw/rtl/libs/VX_avs_adapter.sv

+6-8
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,6 @@ module VX_avs_adapter #(
6464
wire [NUM_BANKS-1:0] req_queue_push, req_queue_pop;
6565
wire [NUM_BANKS-1:0][TAG_WIDTH-1:0] req_queue_tag_out;
6666
wire [NUM_BANKS-1:0] req_queue_going_full;
67-
wire [NUM_BANKS-1:0][RD_QUEUE_ADDR_WIDTH-1:0] req_queue_size;
6867
wire [BANK_ADDRW-1:0] req_bank_sel;
6968
wire [BANK_OFFSETW-1:0] req_bank_off;
7069
wire [NUM_BANKS-1:0] bank_req_ready;
@@ -81,8 +80,7 @@ module VX_avs_adapter #(
8180
assign req_queue_push[i] = mem_req_valid && ~mem_req_rw && bank_req_ready[i] && (req_bank_sel == i);
8281
end
8382

84-
for (genvar i = 0; i < NUM_BANKS; ++i) begin
85-
83+
for (genvar i = 0; i < NUM_BANKS; ++i) begin : pending_sizes
8684
VX_pending_size #(
8785
.SIZE (RD_QUEUE_SIZE)
8886
) pending_size (
@@ -94,10 +92,11 @@ module VX_avs_adapter #(
9492
`UNUSED_PIN (alm_empty),
9593
.full (req_queue_going_full[i]),
9694
`UNUSED_PIN (alm_full),
97-
.size (req_queue_size[i])
95+
`UNUSED_PIN (size)
9896
);
99-
`UNUSED_VAR (req_queue_size)
97+
end
10098

99+
for (genvar i = 0; i < NUM_BANKS; ++i) begin : rd_req_queues
101100
VX_fifo_queue #(
102101
.DATAW (TAG_WIDTH),
103102
.DEPTH (RD_QUEUE_SIZE)
@@ -116,7 +115,7 @@ module VX_avs_adapter #(
116115
);
117116
end
118117

119-
for (genvar i = 0; i < NUM_BANKS; ++i) begin
118+
for (genvar i = 0; i < NUM_BANKS; ++i) begin : req_out_bufs
120119
wire valid_out;
121120
wire rw_out;
122121
wire [DATA_SIZE-1:0] byteen_out;
@@ -168,8 +167,7 @@ module VX_avs_adapter #(
168167
wire [NUM_BANKS-1:0][DATA_WIDTH-1:0] rsp_queue_data_out;
169168
wire [NUM_BANKS-1:0] rsp_queue_empty;
170169

171-
for (genvar i = 0; i < NUM_BANKS; ++i) begin
172-
170+
for (genvar i = 0; i < NUM_BANKS; ++i) begin : rd_rsp_queues
173171
VX_fifo_queue #(
174172
.DATAW (DATA_WIDTH),
175173
.DEPTH (RD_QUEUE_SIZE)

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