kernel/nortos/dpl/a53: fix gic for xen

- Change GIC address as the vGIC in Xen is at 0x30010000
- Remove SGI_PPI stuff as Xen does not support it

Signed-off-by: Amneesh Singh <[email protected]>

Author: natto1784

source/drivers/.meta/system/system_config.c.xdt

@@ -79,12 +79,15 @@ void System_init(void)
 `system.getTemplate(sciclientInitTemplate)()`
 % }
 
+#ifndef XEN_ENABLED
    `system.getTemplate("/kernel/dpl/pmu_init.c.xdt")()`
 
     PowerClock_init();
     /* Now we can do pinmux */
     Pinmux_init();
     /* finally we initialize all peripheral drivers */
+#endif
+
 % let driverOrder = system.getScript('/common').getDriverOpenOrder();
 % let orderedTemplates = [];
 % let otherTemplates = [];

source/kernel/nortos/dpl/a53/HwiP_armv8_gic.c

@@ -337,11 +337,15 @@ void HwiP_init()
     /* Initialize the GIC V3 */
     CSL_gic500_gicdRegs *gicdRegs = (CSL_gic500_gicdRegs *)(HWIP_GIC_BASE_ADDR);
     CSL_gic500_gicrRegs_core_control *gicrRegs;
+#ifndef XEN_ENABLED
     CSL_gic500_gicrRegs_core_sgi_ppi *gicsRegs;
+#endif
 
     /* update the redistributor and sgi_ppi address */
     gicrRegs = (CSL_gic500_gicrRegs_core_control *) (HWIP_GIC_BASE_ADDR + CSL_GIC500_GICR_CORE_CONTROL_CTLR(coreId));
+#ifndef XEN_ENABLED
     gicsRegs = (CSL_gic500_gicrRegs_core_sgi_ppi *) ((uintptr_t)gicrRegs + (uintptr_t) 0x10000U);
+#endif
 
     /* Initialize the Interrupt controller */
     {
@@ -363,7 +367,9 @@ void HwiP_init()
         /*
          * Disable all interrupts at startup
          */
+#ifndef XEN_ENABLED
         gicsRegs->ICENABLER0 = 0xFFFFFFFF;
+#endif
 
         if(0 == coreId)
         {
@@ -384,7 +390,9 @@ void HwiP_init()
         }
 
         /* Search for any previously active interrupts and acknowledge them */
+#ifndef XEN_ENABLED
         intrActiveReg = gicsRegs->ICACTIVER0;
+#endif
         if (intrActiveReg)
         {
             for (j = 0; j < HWIP_GICD_SGI_PPI_INTR_ID_MAX; j++)
@@ -420,7 +428,9 @@ void HwiP_init()
         /*
          * Clear any currently pending enabled interrupts
          */
+#ifndef XEN_ENABLED
         gicsRegs->ICPENDR0  = 0xFFFFFFFF;
+#endif
         if(0 == coreId)
         {
             for (i = 0; i < HWIP_GICD_SPI_INTR_COUNT_MAX/32; i++)
@@ -432,7 +442,9 @@ void HwiP_init()
         /*
          * Clear all interrupt active status registers
          */
+#ifndef XEN_ENABLED
         gicsRegs->ICACTIVER0 = 0xFFFFFFFF;
+#endif
         if(0 == coreId)
         {
             for (i = 0; i < HWIP_GICD_SPI_INTR_COUNT_MAX/32; i++)
@@ -467,7 +479,9 @@ void HwiP_init()
          */
         for (i = 0; i < HWIP_GICD_SGI_PPI_INTR_ID_MAX/4; i++)
         {
+#ifndef XEN_ENABLED
            gicsRegs->IPRIORITYR[i]=0x20202020;
+#endif
         }
         if(0 == coreId)
         {
@@ -499,7 +513,9 @@ void HwiP_init()
          *          b00    Interrupt is active-High level-sensitive
          *          b10    Interrupt is rising edge-sensitive
          */
+#ifndef XEN_ENABLED
         gicsRegs->ICFGR1 = 0;
+#endif
         if(0 == coreId)
         {
             for (i = 0; i < HWIP_GICD_SPI_INTR_COUNT_MAX/16; i++)

source/kernel/nortos/dpl/a53/HwiP_armv8_gic.h

@@ -53,7 +53,11 @@ extern "C"
 #define HWIP_GICD_SPI_INTR_COUNT_MAX    (960U)
 #define HwiP_MAX_INTERRUPTS             (1024u)
 
+#ifndef XEN_ENABLED
 #define HWIP_GIC_BASE_ADDR              (0x1800000UL)
+#else
+#define HWIP_GIC_BASE_ADDR              (0x3001000UL)
+#endif
 
 #define HWIP_GIC_DEFAULT_PRIORITY       ((uint32_t) 0x9U)
 

source/kernel/nortos/dpl/a53/boot_armv8_asm.S

@@ -43,7 +43,11 @@
         .global CacheP_disableEL3
         .global HwiP_armv8GetGicxAddr
 
+#ifndef XEN_ENABLED
 #define HWIP_GIC_BASE_ADDR      (0x1800000U)
+#else
+#define HWIP_GIC_BASE_ADDR      (0x3001000U)
+#endif
 
 #ifdef SOC_AM62AX
 #include <kernel/nortos/dpl/a53/soc/gic_base_address_am62a.h>