SPI slave send macro is unstable at higher frequencies #104
Description
SCLK frequencies at which m_send_packet_spi_slave_msb_gpo_sclk and m_send_packet_spi_slave_lsb_gpo_sclk macros were stable ("Practical Max. Frequency) was considerably lower than the theoretical max.
Practical Max. SCLK : 13.88MHz
Theoretical Max SCLK : 47.619MHz
The instability causes a 1 bit shift of the data that's being send.
Discussions in the below e2e thread suggests that the latency from when SDO bit is push in PRU code until it is seen on the wire is higher than the time the next SCLK sampling edge is received at frequencies higher than the Practical Max. SCLK documented.
https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1603957/am2431-question-about-pru-io-control-delay
A crude solution suggested is to match the first SDO bit with the CS edge and subsequent SDO bits with SCLK to avoid the bit shift issue.
Though this should work with higher frequencies, it is not a general solution.
This behavior needs to be evaluated and fixed with a generic solution for all frequencies.