@@ -28,6 +28,8 @@ module lw_tb;
2828 // set up instrctions and data memory
2929 uut.memory.M [ 0 ] = 32'h00012083 ; // lw x1, 0(x2)
3030 uut.memory.M [ 4 ] = 32'h00412083 ; // lw x1, 4(x2)
31+ uut.memory.M [ 8 ] = 32'hff812083 ; // lw x1, -8(x2)
32+ uut.memory.M [34 ] = 32'hbadab00f ; // have some data at address 34
3133 uut.memory.M [42 ] = 32'hdeadbeef ; // have some data at address 42
3234 uut.memory.M [46 ] = 32'hcafebabe ; // have some data at address 46
3335
@@ -96,7 +98,37 @@ module lw_tb;
9698
9799 `assert_equal (uut.instruction_decode.instanceRegFile.RFMem[1 ], 32'hcafebabe )
98100 `assert_equal (uut.instruction_decode.instanceRegFile.RFMem[2 ], 42 )
99- `assert_equal (uut.fetch.pc_cur, 8 )
101+ `assert_equal (uut.fetch.pc_cur, 8 ) // starting third instruction already
102+
103+ wait_till_next_cfsm_state (uut.control_fsm.DECODE );
104+
105+ `assert_equal (uut.opcode, 7'b0000011 )
106+ `assert_equal (uut.instruction_decode.rs1, 2 )
107+ `assert_equal (uut.instruction_decode.rs2, 0 )
108+ `assert_equal (uut.instruction_decode.imm_ext, - 8 )
109+
110+ wait_till_next_cfsm_state (uut.control_fsm.MEMADR );
111+
112+ `assert_equal (uut.instruction_decode.instanceRegFile.RFMem[2 ], 42 )
113+ `assert_equal (uut.alu.a, 42 )
114+ `assert_equal (uut.alu.b, - 8 )
115+ `assert_equal (uut.alu.out, 34 )
116+
117+ wait_till_next_cfsm_state (uut.control_fsm.MEMREAD );
118+
119+ `assert_equal (uut.result, 34 )
120+ `assert_equal (uut.memory_address, 34 )
121+
122+ wait_till_next_cfsm_state (uut.control_fsm.MEMWB );
123+
124+ `assert_equal (uut.data, 32'hbadab00f )
125+ `assert_equal (uut.result, 32'hbadab00f )
126+
127+ wait_till_next_cfsm_state (uut.control_fsm.FETCH );
128+
129+ `assert_equal (uut.instruction_decode.instanceRegFile.RFMem[1 ], 32'hbadab00f )
130+ `assert_equal (uut.instruction_decode.instanceRegFile.RFMem[2 ], 42 )
131+ `assert_equal (uut.fetch.pc_cur, 12 )
100132
101133 end
102134
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