bit more cleanup

Author: TheDeepestSpace

envs/de1-soc/memory_map.sv

@@ -3,10 +3,11 @@
 
 
 module memory_map #( parameter SIZE = 1024 )
-  ( input  wire    clk
+  ( input  wire       clk
+  , output reg  [9:0] LEDR
+
   , mem_bus.memory d_bus
   , mem_bus.memory i_bus
-  , output reg    [9:0] LEDR
   );
 
   reg [7:0] M0 [0:SIZE - 1] /* synthesis ram_init_file = "../../poc/poc0.mif" */;  // byte lane 0

envs/de1-soc/top.sv

@@ -1,5 +1,3 @@
-//do i need include?
-
 `include "src/interfaces/mem_bus.svh"
 
 module top
@@ -14,18 +12,18 @@ module top
   memory_map #( .SIZE ( 512 ) )
     memory_map
       ( .clk ( CLOCK_50 )
-
-      , .d_bus(d_bus)
-      , .i_bus(i_bus)
-
       , .LEDR ( LEDR )
+
+      , .d_bus ( d_bus )
+      , .i_bus ( i_bus )
       );
 
   utoss_riscv core
     ( .clk   ( CLOCK_50 )
-    , .reset ( ~KEY[0]   )
-    , .d_bus(d_bus)
-    , .i_bus(i_bus)
+    , .reset ( ~KEY[0]  )
+
+    , .d_bus ( d_bus )
+    , .i_bus ( i_bus )
     );
 
 endmodule

envs/simulation/memory.sv

@@ -4,7 +4,8 @@
 // a dual-read single-write memory block that we use with our core in simulation environment
 module memory
   #( parameter SIZE = 1024 )
-  ( input  wire         clk
+  ( input wire clk
+
   , mem_bus.memory i_bus
   , mem_bus.memory d_bus
   );

envs/simulation/top.sv

@@ -13,16 +13,18 @@ module top
   wire unused = &{i_bus.write_data, i_bus.write_enable};
   memory #( .SIZE ( MEM_SIZE ) )
     u_memory
-      ( .clk   ( clk   )
-      , .d_bus ( d_bus )
-      , .i_bus ( i_bus )
+      ( .clk   ( clk )
+
+      , .d_bus ( d_bus.memory )
+      , .i_bus ( i_bus.memory )
       );
 
   utoss_riscv core
     ( .clk   ( clk   )
     , .reset ( reset )
-    , .d_bus ( d_bus )
-    , .i_bus ( i_bus )
+
+    , .d_bus ( d_bus.consumer )
+    , .i_bus ( i_bus.consumer )
     );
 
 endmodule

src/utoss_riscv.sv

@@ -46,8 +46,8 @@ module utoss_riscv
     , .stall_f ( stall_f )
     , .flush_f ( flush_f )
 
-    , .imem__address (i_bus.address)
-    , .imem__data    (i_bus.read_data)
+    , .imem__address ( i_bus.address   )
+    , .imem__data    ( i_bus.read_data )
     );
 
   assign i_bus.write_data = data_t'(0);