From 36edb5ef13ace8780b90311f6f1100e7f261cc74 Mon Sep 17 00:00:00 2001 From: DanielTaoHuang123 Date: Sun, 3 Aug 2025 19:23:27 -0400 Subject: [PATCH 01/11] add sw_testbench add sw testbench; add FF between RF and ALU --- src/top.v | 32 ++++++++--------- test/sw_tb.sv | 97 +++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 111 insertions(+), 18 deletions(-) create mode 100644 test/sw_tb.sv diff --git a/src/top.v b/src/top.v index 94488ccb..0297df14 100644 --- a/src/top.v +++ b/src/top.v @@ -12,7 +12,6 @@ module top ( input wire clk addr_t pc_cur; addr_t memory_address; - data_t memory_data; data_t data; instr_t instruction; opcode_t opcode; @@ -41,6 +40,8 @@ module top ( input wire clk wire [3:0] __tmp_ALUControl; wire [1:0] __tmp_ResultSrc; wire [3:0] __tmp_FSMState; + wire [31:0] dataA + ,dataB; ControlFSM control_fsm ( .opcode ( opcode ) @@ -83,26 +84,16 @@ module top ( input wire clk MA memory // instructions and data ( .A ( memory_address ) - , .WD ( 32'hxxxxxxxx ) - , .WE ( `FALSE ) + , .WD ( dataB ) + , .WE ( __tmp_MemWrite ) , .CLK ( clk ) // outputs - , .RD ( memory_data ) + , .RD ( data ) ); - always @(posedge clk) begin - if (cfsm__ir_write) begin - instruction <= memory_data; - end - end - - always @(posedge clk) begin - data <= memory_data; - end - Instruction_Decode instruction_decode - ( .instr ( instruction ) + ( .instr ( data ) , .clk ( clk ) , .reset ( reset ) , .ResultData ( result ) @@ -130,14 +121,14 @@ module top ( input wire clk case (__tmp_ALUSrcA) ALU_SRC_A__PC: alu_input_a = pc_cur; ALU_SRC_A__OLD_PC: alu_input_a = pc_old; - ALU_SRC_A__RD1: alu_input_a = rd1; + ALU_SRC_A__RD1: alu_input_a = dataA; default: alu_input_a = 32'hxxxxxxxx; endcase end always @(*) begin case (__tmp_ALUSrcB) - ALU_SRC_B__RD2: alu_input_b = rd2; + ALU_SRC_B__RD2: alu_input_b = dataB; ALU_SRC_B__IMM_EXT: alu_input_b = imm_ext; ALU_SRC_B__4: alu_input_b = 32'd4; default: alu_input_b = 32'hxxxxxxxx; @@ -152,5 +143,10 @@ module top ( input wire clk default: result = 32'hxxxxxxxx; endcase end + + always @(posedge clk) begin + dataA <= rd1; + dataB <= rd2; + end -endmodule +endmodule diff --git a/test/sw_tb.sv b/test/sw_tb.sv new file mode 100644 index 00000000..650f67c2 --- /dev/null +++ b/test/sw_tb.sv @@ -0,0 +1,97 @@ +`timescale 1ns/1ps + +`include "test/utils.svh" + +module sw_tb; + + reg clk; + reg reset; + + top uut + ( .clk ( clk ) + , .reset ( reset ) + ); + + initial begin + clk = 0; + forever #5 clk = ~clk; + end + + task wait_till_next_cfsm_state(input [5:0] expected_state); + @(posedge clk); #1; + `assert_equal(uut.control_fsm.current_state, expected_state) + endtask + + initial begin + reset <= `TRUE; + + // set up instructions and data memory + uut.memory.M[ 0] = 32'h00532023; // sw x5, 0(x6) + uut.memory.M[ 4] = 32'h00532223; // sw x5, 4(x6) + uut.memory.M[ 8] = 32'h00532423; // sw x5, 8(x6) + uut.memory.M[34] = 32'hbadab00f; // initial value + uut.memory.M[42] = 32'hdeadbeef; // initial value + uut.memory.M[46] = 32'hcafebabe; // initial value + uut.memory.M[50] = 32'h00000000; // will be written by sw x5, 8(x6) + + // set up register file + uut.instruction_decode.instanceRegFile.RFMem[6] = 42; // x6 = 42 + uut.instruction_decode.instanceRegFile.RFMem[5] = 256; // x5 = 256 + + wait_till_next_cfsm_state(uut.control_fsm.FETCH); + + reset <= `FALSE; + + // --- Instruction 1: sw x5, 0(x6) --- + wait_till_next_cfsm_state(uut.control_fsm.DECODE); + `assert_equal(uut.opcode, 7'b0100011) + `assert_equal(uut.instruction_decode.rs1, 6) + `assert_equal(uut.instruction_decode.rs2, 5) + `assert_equal(uut.instruction_decode.imm_ext, 0) + + wait_till_next_cfsm_state(uut.control_fsm.MEMADR); + `assert_equal(uut.alu.out, 42) + + wait_till_next_cfsm_state(uut.control_fsm.MEMWRITE); + `assert_equal(uut.memory_address, 42) + `assert_equal(uut.memory.M[42], 256) + + wait_till_next_cfsm_state(uut.control_fsm.FETCH); + `assert_equal(uut.fetch.pc_cur, 4) + + // --- Instruction 2: sw x5, 4(x6) --- + wait_till_next_cfsm_state(uut.control_fsm.DECODE); + `assert_equal(uut.instruction_decode.imm_ext, 4) + + wait_till_next_cfsm_state(uut.control_fsm.MEMADR); + `assert_equal(uut.alu.out, 46) + + wait_till_next_cfsm_state(uut.control_fsm.MEMWRITE); + `assert_equal(uut.memory.M[46], 256) + + wait_till_next_cfsm_state(uut.control_fsm.FETCH); + `assert_equal(uut.fetch.pc_cur, 8) + + // --- Instruction 3: sw x5, 8(x6) --- + wait_till_next_cfsm_state(uut.control_fsm.DECODE); + `assert_equal(uut.instruction_decode.imm_ext, 8) + + wait_till_next_cfsm_state(uut.control_fsm.MEMADR); + `assert_equal(uut.alu.out, 50) + + wait_till_next_cfsm_state(uut.control_fsm.MEMWRITE); + `assert_equal(uut.memory.M[50], 256) + + wait_till_next_cfsm_state(uut.control_fsm.FETCH); + + // Final assertions + `assert_equal(uut.memory.M[42], 256) + `assert_equal(uut.memory.M[46], 256) + `assert_equal(uut.memory.M[50], 256) + `assert_equal(uut.instruction_decode.instanceRegFile.RFMem[5], 256) + `assert_equal(uut.instruction_decode.instanceRegFile.RFMem[6], 42) + end + + `SETUP_VCD_DUMP(sw_tb) + +endmodule From 0c9d383c43a83384230be4cd7e5c997f2b3cda89 Mon Sep 17 00:00:00 2001 From: DanielTaoHuang123 Date: Sun, 3 Aug 2025 19:31:59 -0400 Subject: [PATCH 02/11] Update top.v --- src/top.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/top.v b/src/top.v index 0297df14..eb2a0f01 100644 --- a/src/top.v +++ b/src/top.v @@ -40,7 +40,7 @@ module top ( input wire clk wire [3:0] __tmp_ALUControl; wire [1:0] __tmp_ResultSrc; wire [3:0] __tmp_FSMState; - wire [31:0] dataA + logic [31:0] dataA ,dataB; ControlFSM control_fsm From a6d5ec9fb690084b2f2ada1b65fb543bf2d8f302 Mon Sep 17 00:00:00 2001 From: DanielTaoHuang123 Date: Sun, 3 Aug 2025 19:42:42 -0400 Subject: [PATCH 03/11] Update top.v --- src/top.v | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/top.v b/src/top.v index eb2a0f01..7fd13958 100644 --- a/src/top.v +++ b/src/top.v @@ -92,6 +92,16 @@ module top ( input wire clk , .RD ( data ) ); + always @(posedge clk) begin + if (cfsm__ir_write) begin + instruction <= memory_data; + end + end + + always @(posedge clk) begin + data <= memory_data; + end + Instruction_Decode instruction_decode ( .instr ( data ) , .clk ( clk ) From 356be06f793812d3d1f41f41f0587da1985fca89 Mon Sep 17 00:00:00 2001 From: DanielTaoHuang123 Date: Sun, 3 Aug 2025 19:48:06 -0400 Subject: [PATCH 04/11] Update top.v --- src/top.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/top.v b/src/top.v index 7fd13958..8452471b 100644 --- a/src/top.v +++ b/src/top.v @@ -89,7 +89,7 @@ module top ( input wire clk , .CLK ( clk ) // outputs - , .RD ( data ) + , .RD ( memory_data ) ); always @(posedge clk) begin From bf3307b50fdbb4f61251cc0b515dc9e90c12b52b Mon Sep 17 00:00:00 2001 From: DanielTaoHuang123 Date: Sun, 3 Aug 2025 19:53:58 -0400 Subject: [PATCH 05/11] Update top.v --- src/top.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/top.v b/src/top.v index 8452471b..00f2b061 100644 --- a/src/top.v +++ b/src/top.v @@ -12,6 +12,7 @@ module top ( input wire clk addr_t pc_cur; addr_t memory_address; + data_t memory_data; data_t data; instr_t instruction; opcode_t opcode; @@ -103,7 +104,7 @@ module top ( input wire clk end Instruction_Decode instruction_decode - ( .instr ( data ) + ( .instr ( instruction ) , .clk ( clk ) , .reset ( reset ) , .ResultData ( result ) From 2c3457b0d72e5f3094b2c5abb8f5128a2f9b2638 Mon Sep 17 00:00:00 2001 From: Boris Date: Tue, 5 Aug 2025 02:53:55 +0000 Subject: [PATCH 06/11] stop clocking rf reads --- src/Instruction_Decode/RegisterFile.v | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/Instruction_Decode/RegisterFile.v b/src/Instruction_Decode/RegisterFile.v index 4b674b24..c43b6c47 100644 --- a/src/Instruction_Decode/RegisterFile.v +++ b/src/Instruction_Decode/RegisterFile.v @@ -17,8 +17,8 @@ input clk, input regWrite, input [31:0] dataIn, input reset, -output reg [31:0] baseAddr, //data read line #1 - from first source register -output reg [31:0] writeData //data read line #2 - from second source register +output wire [31:0] baseAddr, //data read line #1 - from first source register +output wire [31:0] writeData //data read line #2 - from second source register ); @@ -26,14 +26,14 @@ output reg [31:0] writeData //data read line #2 - from second source register //32 bits deep (32 addresses) and 32 bits wide (32 bits at each register) //note that RFMem[0:31] means there are 32 elements (with addr for each element), each of which are 32-bit regs reg [31:0] RFMem [0:31] /* synthesis ramstyle = M10K*/; - + + assign baseAddr = RFMem[Addr1]; //read out 32-bit contents of rs1 register + assign writeData = RFMem[Addr2]; //read out 32-bit contents of rs2 register + always@(posedge clk) begin if (reset) RFMem[0] <= 0; //register r0 should always remain at 0 - - baseAddr <= RFMem[Addr1]; //read out 32-bit contents of rs1 register - writeData <= RFMem[Addr2]; //read out 32-bit contents of rs2 register - + if(regWrite && Addr3 != 0) begin RFMem[Addr3] <= dataIn; //write into destination register if RegWrite = 1 From a839e4977d73a4b5f7dc3c4f1316cf7bd53227d0 Mon Sep 17 00:00:00 2001 From: Boris Date: Tue, 5 Aug 2025 03:49:57 +0000 Subject: [PATCH 07/11] reset MemWrite for new cycles --- src/ControlFSM.sv | 1 + 1 file changed, 1 insertion(+) diff --git a/src/ControlFSM.sv b/src/ControlFSM.sv index de2e4670..73e09133 100644 --- a/src/ControlFSM.sv +++ b/src/ControlFSM.sv @@ -102,6 +102,7 @@ module ControlFSM( pc_src <= 1'b0; PCUpdate <= 1'b0; IRWrite <= 1'b0; + MemWrite <= 1'b0; FSMState <= current_state; From ebd8ff07d2a78e8d79289dd18c909dfb74245b92 Mon Sep 17 00:00:00 2001 From: Boris Date: Tue, 5 Aug 2025 03:50:10 +0000 Subject: [PATCH 08/11] update addressing and sync in sw tb --- test/sw_tb.sv | 48 ++++++++++++++++++++++++++++++------------------ 1 file changed, 30 insertions(+), 18 deletions(-) diff --git a/test/sw_tb.sv b/test/sw_tb.sv index 650f67c2..d58fce4e 100644 --- a/test/sw_tb.sv +++ b/test/sw_tb.sv @@ -27,15 +27,15 @@ module sw_tb; // set up instructions and data memory uut.memory.M[ 0] = 32'h00532023; // sw x5, 0(x6) - uut.memory.M[ 4] = 32'h00532223; // sw x5, 4(x6) - uut.memory.M[ 8] = 32'h00532423; // sw x5, 8(x6) - uut.memory.M[34] = 32'hbadab00f; // initial value - uut.memory.M[42] = 32'hdeadbeef; // initial value - uut.memory.M[46] = 32'hcafebabe; // initial value - uut.memory.M[50] = 32'h00000000; // will be written by sw x5, 8(x6) + uut.memory.M[ 1] = 32'h00532223; // sw x5, 4(x6) + uut.memory.M[ 2] = 32'h00532423; // sw x5, 8(x6) + uut.memory.M[10] = 32'hbadab00f; // initial value + uut.memory.M[11] = 32'hdeadbeef; // initial value + uut.memory.M[12] = 32'hcafebabe; // initial value + uut.memory.M[13] = 32'h00000000; // will be written by sw x5, 8(x6) // set up register file - uut.instruction_decode.instanceRegFile.RFMem[6] = 42; // x6 = 42 + uut.instruction_decode.instanceRegFile.RFMem[6] = 44; // x6 = 44 uut.instruction_decode.instanceRegFile.RFMem[5] = 256; // x5 = 256 wait_till_next_cfsm_state(uut.control_fsm.FETCH); @@ -50,46 +50,58 @@ module sw_tb; `assert_equal(uut.instruction_decode.imm_ext, 0) wait_till_next_cfsm_state(uut.control_fsm.MEMADR); - `assert_equal(uut.alu.out, 42) + `assert_equal(uut.alu.out, 44) wait_till_next_cfsm_state(uut.control_fsm.MEMWRITE); - `assert_equal(uut.memory_address, 42) - `assert_equal(uut.memory.M[42], 256) + `assert_equal(uut.memory_address, 44) wait_till_next_cfsm_state(uut.control_fsm.FETCH); + + `assert_equal(uut.memory.M[11], 256) `assert_equal(uut.fetch.pc_cur, 4) // --- Instruction 2: sw x5, 4(x6) --- wait_till_next_cfsm_state(uut.control_fsm.DECODE); + `assert_equal(uut.instruction_decode.imm_ext, 4) wait_till_next_cfsm_state(uut.control_fsm.MEMADR); - `assert_equal(uut.alu.out, 46) + + `assert_equal(uut.alu.out, 48) wait_till_next_cfsm_state(uut.control_fsm.MEMWRITE); - `assert_equal(uut.memory.M[46], 256) wait_till_next_cfsm_state(uut.control_fsm.FETCH); + + `assert_equal(uut.memory.M[12], 256) `assert_equal(uut.fetch.pc_cur, 8) // --- Instruction 3: sw x5, 8(x6) --- wait_till_next_cfsm_state(uut.control_fsm.DECODE); + + `assert_equal(uut.opcode, 7'b0100011) + `assert_equal(uut.instruction_decode.rs1, 6) + `assert_equal(uut.instruction_decode.rs2, 5) `assert_equal(uut.instruction_decode.imm_ext, 8) wait_till_next_cfsm_state(uut.control_fsm.MEMADR); - `assert_equal(uut.alu.out, 50) + + `assert_equal(uut.alu.out, 52) wait_till_next_cfsm_state(uut.control_fsm.MEMWRITE); - `assert_equal(uut.memory.M[50], 256) wait_till_next_cfsm_state(uut.control_fsm.FETCH); + `assert_equal(uut.memory.M[13], 256) + // Final assertions - `assert_equal(uut.memory.M[42], 256) - `assert_equal(uut.memory.M[46], 256) - `assert_equal(uut.memory.M[50], 256) + `assert_equal(uut.memory.M[11], 256) + `assert_equal(uut.memory.M[12], 256) + `assert_equal(uut.memory.M[13], 256) `assert_equal(uut.instruction_decode.instanceRegFile.RFMem[5], 256) - `assert_equal(uut.instruction_decode.instanceRegFile.RFMem[6], 42) + `assert_equal(uut.instruction_decode.instanceRegFile.RFMem[6], 44) + + $finish; end `SETUP_VCD_DUMP(sw_tb) From aac18d32a14020caf87bed98f5a28d17cc7da987 Mon Sep 17 00:00:00 2001 From: DanielTaoHuang123 Date: Sun, 10 Aug 2025 10:39:33 -0400 Subject: [PATCH 09/11] Create addi_tb.sv --- test/addi_tb.sv | 91 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 test/addi_tb.sv diff --git a/test/addi_tb.sv b/test/addi_tb.sv new file mode 100644 index 00000000..f743c273 --- /dev/null +++ b/test/addi_tb.sv @@ -0,0 +1,91 @@ +`timescale 1ns/1ps + +`include "test/utils.svh" + +module addi_tb; + + reg clk; + reg reset; + + top uut + ( .clk ( clk ) + , .reset ( reset ) + ); + + initial begin + clk = 0; + forever #5 clk = ~clk; + end + + task wait_till_next_cfsm_state(input [5:0] expected_state); + @(posedge clk); #1; + `assert_equal(uut.control_fsm.current_state, expected_state) + endtask + + initial begin + reset <= `TRUE; + + // Set up instruction memory + uut.memory.M[ 0] = 32'h00010113; // addi x1, x2, 0 + uut.memory.M[ 4] = 32'h00410113; // addi x1, x2, 4 + uut.memory.M[ 8] = 32'hff810113; // addi x1, x2, -8 + + // Set up register file + // x1 = 0 by default + uut.instruction_decode.instanceRegFile.RFMem[2] = 42; // x2 = 42 + + wait_till_next_cfsm_state(uut.control_fsm.FETCH); + + reset <= `FALSE; + + // --- Instruction 1: addi x1, x2, 0 --- + wait_till_next_cfsm_state(uut.control_fsm.DECODE); + `assert_equal(uut.opcode, 7'b0010011) + `assert_equal(uut.instruction_decode.rs1, 2) + `assert_equal(uut.instruction_decode.rd, 1) + `assert_equal(uut.instruction_decode.imm_ext, 0) + + wait_till_next_cfsm_state(uut.control_fsm.EXECUTE); + `assert_equal(uut.alu.a, 42) + `assert_equal(uut.alu.b, 0) + `assert_equal(uut.alu.out, 42) + + wait_till_next_cfsm_state(uut.control_fsm.ALUWB); + `assert_equal(uut.instruction_decode.instanceRegFile.RFMem[1], 42) + + wait_till_next_cfsm_state(uut.control_fsm.FETCH); + `assert_equal(uut.fetch.pc_cur, 4) + + // --- Instruction 2: addi x1, x2, 4 --- + wait_till_next_cfsm_state(uut.control_fsm.DECODE); + `assert_equal(uut.instruction_decode.imm_ext, 4) + + wait_till_next_cfsm_state(uut.control_fsm.EXECUTE); + `assert_equal(uut.alu.out, 46) + + wait_till_next_cfsm_state(uut.control_fsm.ALUWB); + `assert_equal(uut.instruction_decode.instanceRegFile.RFMem[1], 46) + + wait_till_next_cfsm_state(uut.control_fsm.FETCH); + `assert_equal(uut.fetch.pc_cur, 8) + + // --- Instruction 3: addi x1, x2, -8 --- + wait_till_next_cfsm_state(uut.control_fsm.DECODE); + `assert_equal(uut.instruction_decode.imm_ext, -8) + + wait_till_next_cfsm_state(uut.control_fsm.EXECUTE); + `assert_equal(uut.alu.out, 34) + + wait_till_next_cfsm_state(uut.control_fsm.ALUWB); + `assert_equal(uut.instruction_decode.instanceRegFile.RFMem[1], 34) + + wait_till_next_cfsm_state(uut.control_fsm.FETCH); + + // Final assertions + `assert_equal(uut.instruction_decode.instanceRegFile.RFMem[2], 42) + `assert_equal(uut.instruction_decode.instanceRegFile.RFMem[1], 34) + end + + `SETUP_VCD_DUMP(addi_tb) + +endmodule From 540d456ad139b713e070caeccc13fd4285cb3519 Mon Sep 17 00:00:00 2001 From: Boris Date: Sun, 10 Aug 2025 19:07:45 +0000 Subject: [PATCH 10/11] fix fsm state name --- test/addi_tb.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/test/addi_tb.sv b/test/addi_tb.sv index f743c273..1a99de60 100644 --- a/test/addi_tb.sv +++ b/test/addi_tb.sv @@ -45,7 +45,7 @@ module addi_tb; `assert_equal(uut.instruction_decode.rd, 1) `assert_equal(uut.instruction_decode.imm_ext, 0) - wait_till_next_cfsm_state(uut.control_fsm.EXECUTE); + wait_till_next_cfsm_state(uut.control_fsm.EXECUTER); `assert_equal(uut.alu.a, 42) `assert_equal(uut.alu.b, 0) `assert_equal(uut.alu.out, 42) @@ -60,7 +60,7 @@ module addi_tb; wait_till_next_cfsm_state(uut.control_fsm.DECODE); `assert_equal(uut.instruction_decode.imm_ext, 4) - wait_till_next_cfsm_state(uut.control_fsm.EXECUTE); + wait_till_next_cfsm_state(uut.control_fsm.EXECUTER); `assert_equal(uut.alu.out, 46) wait_till_next_cfsm_state(uut.control_fsm.ALUWB); @@ -73,7 +73,7 @@ module addi_tb; wait_till_next_cfsm_state(uut.control_fsm.DECODE); `assert_equal(uut.instruction_decode.imm_ext, -8) - wait_till_next_cfsm_state(uut.control_fsm.EXECUTE); + wait_till_next_cfsm_state(uut.control_fsm.EXECUTER); `assert_equal(uut.alu.out, 34) wait_till_next_cfsm_state(uut.control_fsm.ALUWB); From 25ea49ed1436465fb894b6860394368a3310e65d Mon Sep 17 00:00:00 2001 From: Boris Date: Sun, 10 Aug 2025 19:44:20 +0000 Subject: [PATCH 11/11] fix tb --- test/addi_tb.sv | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/test/addi_tb.sv b/test/addi_tb.sv index 1a99de60..d9f83505 100644 --- a/test/addi_tb.sv +++ b/test/addi_tb.sv @@ -26,12 +26,12 @@ module addi_tb; reset <= `TRUE; // Set up instruction memory - uut.memory.M[ 0] = 32'h00010113; // addi x1, x2, 0 - uut.memory.M[ 4] = 32'h00410113; // addi x1, x2, 4 - uut.memory.M[ 8] = 32'hff810113; // addi x1, x2, -8 + uut.memory.M[ 0] = 32'h00010093; // addi x1, x2, 0 + uut.memory.M[ 1] = 32'h00410093; // addi x1, x2, 4 + uut.memory.M[ 2] = 32'hff810093; // addi x1, x2, -8 // Set up register file - // x1 = 0 by default + uut.instruction_decode.instanceRegFile.RFMem[1] = 0; // x1 = 0 uut.instruction_decode.instanceRegFile.RFMem[2] = 42; // x2 = 42 wait_till_next_cfsm_state(uut.control_fsm.FETCH); @@ -45,45 +45,47 @@ module addi_tb; `assert_equal(uut.instruction_decode.rd, 1) `assert_equal(uut.instruction_decode.imm_ext, 0) - wait_till_next_cfsm_state(uut.control_fsm.EXECUTER); + wait_till_next_cfsm_state(uut.control_fsm.EXECUTEI); `assert_equal(uut.alu.a, 42) `assert_equal(uut.alu.b, 0) `assert_equal(uut.alu.out, 42) wait_till_next_cfsm_state(uut.control_fsm.ALUWB); - `assert_equal(uut.instruction_decode.instanceRegFile.RFMem[1], 42) wait_till_next_cfsm_state(uut.control_fsm.FETCH); + `assert_equal(uut.instruction_decode.instanceRegFile.RFMem[1], 42) `assert_equal(uut.fetch.pc_cur, 4) // --- Instruction 2: addi x1, x2, 4 --- wait_till_next_cfsm_state(uut.control_fsm.DECODE); `assert_equal(uut.instruction_decode.imm_ext, 4) - wait_till_next_cfsm_state(uut.control_fsm.EXECUTER); + wait_till_next_cfsm_state(uut.control_fsm.EXECUTEI); `assert_equal(uut.alu.out, 46) wait_till_next_cfsm_state(uut.control_fsm.ALUWB); - `assert_equal(uut.instruction_decode.instanceRegFile.RFMem[1], 46) wait_till_next_cfsm_state(uut.control_fsm.FETCH); + `assert_equal(uut.instruction_decode.instanceRegFile.RFMem[1], 46) `assert_equal(uut.fetch.pc_cur, 8) // --- Instruction 3: addi x1, x2, -8 --- wait_till_next_cfsm_state(uut.control_fsm.DECODE); `assert_equal(uut.instruction_decode.imm_ext, -8) - wait_till_next_cfsm_state(uut.control_fsm.EXECUTER); + wait_till_next_cfsm_state(uut.control_fsm.EXECUTEI); `assert_equal(uut.alu.out, 34) wait_till_next_cfsm_state(uut.control_fsm.ALUWB); - `assert_equal(uut.instruction_decode.instanceRegFile.RFMem[1], 34) wait_till_next_cfsm_state(uut.control_fsm.FETCH); + `assert_equal(uut.instruction_decode.instanceRegFile.RFMem[1], 34) // Final assertions `assert_equal(uut.instruction_decode.instanceRegFile.RFMem[2], 42) `assert_equal(uut.instruction_decode.instanceRegFile.RFMem[1], 34) + + $finish; end `SETUP_VCD_DUMP(addi_tb)