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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Arnd Bergmann: "The main addition this time around is the new ARM "SCMI" framework, which is the latest in a series of standards coming from ARM to do power management in a platform independent way. This has been through many review cycles, and it relies on a rather interesting way of using the mailbox subsystem, but in the end I agreed that Sudeep's version was the best we could do after all. Other changes include: - the ARM CCN driver is moved out of drivers/bus into drivers/perf, which makes more sense. Similarly, the performance monitoring portion of the CCI driver are moved the same way and cleaned up a little more. - a series of updates to the SCPI framework - support for the Mediatek mt7623a SoC in drivers/soc - support for additional NVIDIA Tegra hardware in drivers/soc - a new reset driver for Socionext Uniphier - lesser bug fixes in drivers/soc, drivers/tee, drivers/memory, and drivers/firmware and drivers/reset across platforms" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (87 commits) reset: uniphier: add ethernet reset control support for PXs3 reset: stm32mp1: Enable stm32mp1 reset driver dt-bindings: reset: add STM32MP1 resets reset: uniphier: add Pro4/Pro5/PXs2 audio systems reset control reset: imx7: add 'depends on HAS_IOMEM' to fix unmet dependency reset: modify the way reset lookup works for board files reset: add support for non-DT systems clk: scmi: use devm_of_clk_add_hw_provider() API and drop scmi_clocks_remove firmware: arm_scmi: prevent accessing rate_discrete uninitialized hwmon: (scmi) return -EINVAL when sensor information is unavailable amlogic: meson-gx-socinfo: Update soc ids soc/tegra: pmc: Use the new reset APIs to manage reset controllers soc: mediatek: update power domain data of MT2712 dt-bindings: soc: update MT2712 power dt-bindings cpufreq: scmi: add thermal dependency soc: mediatek: fix the mistaken pointer accessed when subdomains are added soc: mediatek: add SCPSYS power domain driver for MediaTek MT7623A SoC soc: mediatek: avoid hardcoded value with bus_prot_mask dt-bindings: soc: add header files required for MT7623A SCPSYS dt-binding dt-bindings: soc: add SCPSYS binding for MT7623 and MT7623A SoC ...
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‎Documentation/devicetree/bindings/arm/arm,scmi.txt

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System Control and Management Interface (SCMI) Message Protocol
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----------------------------------------------------------
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The SCMI is intended to allow agents such as OSPM to manage various functions
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that are provided by the hardware platform it is running on, including power
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and performance functions.
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This binding is intended to define the interface the firmware implementing
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the SCMI as described in ARM document number ARM DUI 0922B ("ARM System Control
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and Management Interface Platform Design Document")[0] provide for OSPM in
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the device tree.
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Required properties:
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The scmi node with the following properties shall be under the /firmware/ node.
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- compatible : shall be "arm,scmi"
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- mboxes: List of phandle and mailbox channel specifiers. It should contain
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exactly one or two mailboxes, one for transmitting messages("tx")
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and another optional for receiving the notifications("rx") if
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supported.
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- shmem : List of phandle pointing to the shared memory(SHM) area as per
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generic mailbox client binding.
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- #address-cells : should be '1' if the device has sub-nodes, maps to
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protocol identifier for a given sub-node.
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- #size-cells : should be '0' as 'reg' property doesn't have any size
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associated with it.
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Optional properties:
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- mbox-names: shall be "tx" or "rx" depending on mboxes entries.
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See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details
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about the generic mailbox controller and client driver bindings.
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The mailbox is the only permitted method of calling the SCMI firmware.
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Mailbox doorbell is used as a mechanism to alert the presence of a
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messages and/or notification.
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Each protocol supported shall have a sub-node with corresponding compatible
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as described in the following sections. If the platform supports dedicated
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communication channel for a particular protocol, the 3 properties namely:
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mboxes, mbox-names and shmem shall be present in the sub-node corresponding
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to that protocol.
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Clock/Performance bindings for the clocks/OPPs based on SCMI Message Protocol
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------------------------------------------------------------
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This binding uses the common clock binding[1].
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Required properties:
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- #clock-cells : Should be 1. Contains the Clock ID value used by SCMI commands.
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Power domain bindings for the power domains based on SCMI Message Protocol
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------------------------------------------------------------
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This binding for the SCMI power domain providers uses the generic power
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domain binding[2].
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Required properties:
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- #power-domain-cells : Should be 1. Contains the device or the power
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domain ID value used by SCMI commands.
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Sensor bindings for the sensors based on SCMI Message Protocol
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--------------------------------------------------------------
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SCMI provides an API to access the various sensors on the SoC.
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Required properties:
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- #thermal-sensor-cells: should be set to 1. This property follows the
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thermal device tree bindings[3].
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Valid cell values are raw identifiers (Sensor ID)
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as used by the firmware. Refer to platform details
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for your implementation for the IDs to use.
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SRAM and Shared Memory for SCMI
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-------------------------------
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A small area of SRAM is reserved for SCMI communication between application
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processors and SCP.
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The properties should follow the generic mmio-sram description found in [4]
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Each sub-node represents the reserved area for SCMI.
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Required sub-node properties:
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- reg : The base offset and size of the reserved area with the SRAM
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- compatible : should be "arm,scmi-shmem" for Non-secure SRAM based
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shared memory
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[0] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/index.html
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/power/power_domain.txt
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[3] Documentation/devicetree/bindings/thermal/thermal.txt
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[4] Documentation/devicetree/bindings/sram/sram.txt
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Example:
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sram@50000000 {
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compatible = "mmio-sram";
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reg = <0x0 0x50000000 0x0 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0x50000000 0x10000>;
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cpu_scp_lpri: scp-shmem@0 {
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compatible = "arm,scmi-shmem";
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reg = <0x0 0x200>;
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};
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cpu_scp_hpri: scp-shmem@200 {
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compatible = "arm,scmi-shmem";
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reg = <0x200 0x200>;
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};
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};
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mailbox@40000000 {
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....
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#mbox-cells = <1>;
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reg = <0x0 0x40000000 0x0 0x10000>;
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};
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firmware {
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...
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scmi {
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compatible = "arm,scmi";
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mboxes = <&mailbox 0 &mailbox 1>;
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mbox-names = "tx", "rx";
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shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
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#address-cells = <1>;
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#size-cells = <0>;
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scmi_devpd: protocol@11 {
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reg = <0x11>;
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#power-domain-cells = <1>;
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};
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scmi_dvfs: protocol@13 {
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reg = <0x13>;
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#clock-cells = <1>;
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};
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scmi_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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scmi_sensors0: protocol@15 {
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reg = <0x15>;
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#thermal-sensor-cells = <1>;
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};
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};
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};
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cpu@0 {
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...
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reg = <0 0>;
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clocks = <&scmi_dvfs 0>;
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};
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hdlcd@7ff60000 {
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...
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reg = <0 0x7ff60000 0 0x1000>;
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clocks = <&scmi_clk 4>;
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power-domains = <&scmi_devpd 1>;
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};
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thermal-zones {
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soc_thermal {
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polling-delay-passive = <100>;
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polling-delay = <1000>;
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/* sensor ID */
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thermal-sensors = <&scmi_sensors0 3>;
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...
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};
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};

‎Documentation/devicetree/bindings/arm/samsung/pmu.txt

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- interrupt-parent: a phandle indicating which interrupt controller
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this PMU signals interrupts to.
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Optional nodes:
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- nodes defining the restart and poweroff syscon children
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Example :
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pmu_system_controller: system-controller@10040000 {
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compatible = "samsung,exynos5250-pmu", "syscon";

‎Documentation/devicetree/bindings/mailbox/mailbox.txt

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Optional property:
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- mbox-names: List of identifier strings for each mailbox channel.
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- shmem : List of phandle pointing to the shared memory(SHM) area between the
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users of these mailboxes for IPC, one for each mailbox. This shared
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memory can be part of any memory reserved for the purpose of this
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communication between the mailbox client and the remote.
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Example:
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pwr_cntrl: power {
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...
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mbox-names = "pwr-ctrl", "rpc";
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mboxes = <&mailbox 0 &mailbox 1>;
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};
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Example with shared memory(shmem):
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sram: sram@50000000 {
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compatible = "mmio-sram";
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reg = <0x50000000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x50000000 0x10000>;
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cl_shmem: shmem@0 {
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compatible = "client-shmem";
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reg = <0x0 0x200>;
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};
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};
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client@2e000000 {
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...
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mboxes = <&mailbox 0>;
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shmem = <&cl_shmem>;
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..
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};

‎Documentation/devicetree/bindings/mfd/aspeed-lpc.txt

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compatible = "aspeed,ast2500-lhc";
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reg = <0x20 0x24 0x48 0x8>;
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};
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LPC reset control
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-----------------
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The UARTs present in the ASPEED SoC can have their resets tied to the reset
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state of the LPC bus. Some systems may chose to modify this configuration.
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Required properties:
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- compatible: "aspeed,ast2500-lpc-reset" or
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"aspeed,ast2400-lpc-reset"
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- reg: offset and length of the IP in the LHC memory region
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- #reset-controller indicates the number of reset cells expected
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Example:
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lpc_reset: reset-controller@18 {
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compatible = "aspeed,ast2500-lpc-reset";
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reg = <0x18 0x4>;
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#reset-cells = <1>;
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};

‎Documentation/devicetree/bindings/arm/ccn.txt renamed to ‎Documentation/devicetree/bindings/perf/arm-ccn.txt

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‎Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt

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STMicroelectronics STM32MP1 Peripheral Reset Controller
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=======================================================
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The RCC IP is both a reset and a clock controller.
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Please see Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt

‎Documentation/devicetree/bindings/soc/mediatek/scpsys.txt

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- "mediatek,mt2712-scpsys"
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- "mediatek,mt6797-scpsys"
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- "mediatek,mt7622-scpsys"
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- "mediatek,mt7623-scpsys", "mediatek,mt2701-scpsys": For MT7623 SoC
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- "mediatek,mt7623a-scpsys": For MT7623A SoC
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- "mediatek,mt8173-scpsys"
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- #power-domain-cells: Must be 1
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- reg: Address range of the SCPSYS unit
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- infracfg: must contain a phandle to the infracfg controller
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- clock, clock-names: clocks according to the common clock binding.
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These are clocks which hardware needs to be
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enabled before enabling certain power domains.
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Required clocks for MT2701: "mm", "mfg", "ethif"
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Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif"
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Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec"
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Required clocks for MT6797: "mm", "mfg", "vdec"
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Required clocks for MT7622: "hif_sel"
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Required clocks for MT7622A: "ethif"
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Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
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Optional properties:

‎Documentation/arm/CCN.txt renamed to ‎Documentation/perf/arm-ccn.txt

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‎MAINTAINERS

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S: Supported
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F: drivers/mfd/syscon.c
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SYSTEM CONTROL & POWER INTERFACE (SCPI) Message Protocol drivers
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SYSTEM CONTROL & POWER/MANAGEMENT INTERFACE (SCPI/SCMI) Message Protocol drivers
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M: Sudeep Holla <[email protected]>
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L: [email protected]
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S: Maintained
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F: Documentation/devicetree/bindings/arm/arm,scpi.txt
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F: drivers/clk/clk-scpi.c
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F: drivers/cpufreq/scpi-cpufreq.c
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F: Documentation/devicetree/bindings/arm/arm,sc[mp]i.txt
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F: drivers/clk/clk-sc[mp]i.c
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F: drivers/cpufreq/sc[mp]i-cpufreq.c
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F: drivers/firmware/arm_scpi.c
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F: include/linux/scpi_protocol.h
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F: drivers/firmware/arm_scmi/
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F: include/linux/sc[mp]i_protocol.h
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SYSTEM RESET/SHUTDOWN DRIVERS
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M: Sebastian Reichel <[email protected]>

‎drivers/bus/Kconfig

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config ARM_CCI
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bool
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config ARM_CCI_PMU
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bool
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select ARM_CCI
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1511
config ARM_CCI400_COMMON
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bool
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select ARM_CCI
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config ARM_CCI400_PMU
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bool "ARM CCI400 PMU support"
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depends on (ARM && CPU_V7) || ARM64
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depends on PERF_EVENTS
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select ARM_CCI400_COMMON
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select ARM_CCI_PMU
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help
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Support for PMU events monitoring on the ARM CCI-400 (cache coherent
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interconnect). CCI-400 supports counting events related to the
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connected slave/master interfaces.
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config ARM_CCI400_PORT_CTRL
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bool
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depends on ARM && OF && CPU_V7
@@ -35,27 +20,6 @@ config ARM_CCI400_PORT_CTRL
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Low level power management driver for CCI400 cache coherent
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interconnect for ARM platforms.
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38-
config ARM_CCI5xx_PMU
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bool "ARM CCI-500/CCI-550 PMU support"
40-
depends on (ARM && CPU_V7) || ARM64
41-
depends on PERF_EVENTS
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select ARM_CCI_PMU
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help
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Support for PMU events monitoring on the ARM CCI-500/CCI-550 cache
45-
coherent interconnects. Both of them provide 8 independent event counters,
46-
which can count events pertaining to the slave/master interfaces as well
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as the internal events to the CCI.
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If unsure, say Y
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config ARM_CCN
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tristate "ARM CCN driver support"
53-
depends on ARM || ARM64
54-
depends on PERF_EVENTS
55-
help
56-
PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
57-
interconnect.
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config BRCMSTB_GISB_ARB
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bool "Broadcom STB GISB bus arbiter"
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depends on ARM || ARM64 || MIPS

‎drivers/bus/Makefile

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# Interconnect bus drivers for ARM platforms
77
obj-$(CONFIG_ARM_CCI) += arm-cci.o
8-
obj-$(CONFIG_ARM_CCN) += arm-ccn.o
9-
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obj-$(CONFIG_BRCMSTB_GISB_ARB) += brcmstb_gisb.o
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# DPAA2 fsl-mc bus

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