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README.md
README.md
 
 
sync.pkg.vhdl
sync.pkg.vhdl
 
 
sync_Bits.files
sync_Bits.files
 
 
sync_Bits.vhdl
sync_Bits.vhdl
 
 
sync_Bits_Altera.vhdl
sync_Bits_Altera.vhdl
 
 
sync_Bits_Xilinx.vhdl
sync_Bits_Xilinx.vhdl
 
 
sync_Command.files
sync_Command.files
 
 
sync_Command.vhdl
sync_Command.vhdl
 
 
sync_Pulse.files
sync_Pulse.files
 
 
sync_Pulse.vhdl
sync_Pulse.vhdl
 
 
sync_Pulse_Altera.vhdl
sync_Pulse_Altera.vhdl
 
 
sync_Pulse_Xilinx.vhdl
sync_Pulse_Xilinx.vhdl
 
 
sync_Reset.files
sync_Reset.files
 
 
sync_Reset.vhdl
sync_Reset.vhdl
 
 
sync_Reset_Altera.vhdl
sync_Reset_Altera.vhdl
 
 
sync_Reset_Xilinx.vhdl
sync_Reset_Xilinx.vhdl
 
 
sync_Strobe.files
sync_Strobe.files
 
 
sync_Strobe.vhdl
sync_Strobe.vhdl
 
 
sync_Vector.files
sync_Vector.files
 
 
sync_Vector.vhdl
sync_Vector.vhdl
 
 

README.md

Namespace PoC.misc.sync

The namespace PoC.misc.sync offers different clock-domain-crossing (CDC) synchronizer circuits. All synchronizers are based on the basic 2 flip-flop synchonizer called sync_Bits. PoC has a generic and two platform specific implementations for Altera and Xilinx, which are choosen, if the appropriate MY_DEVICE is configured in my_config.vhdl.

Package(s)

The package PoC.sync holds all component declarations for this namespace.

Entities

Basic 2 Flip-Flop Synchronizer

  • sync_Bits Is a basic 2 flip-flop synchronizer. It's possible to configure the bit count of indivital bits. If a vector shall be synchronized, use one of the special synchronizers like sync_Vector (see below). The vendor specific implementations are named sync_Bits_Altera and sync_Bits_Xilinx respectivily.

    This synchronizer needs to be constrained, so static timing analysis will report the correct results. See the constraint folder for applieable constraint files for your synthesis tool.

  • sync_Reset Is a variant of the 2 flip-flop synchronizer for Reset-signals, implementing asynchronous assertion and synchronous deassertion. The vendor specific implementations are named sync_Reset_Altera and sync_Reset_Xilinx respectivily.

    This synchronizer needs to be constrained, so static timing analysis will report the correct results. See the constraint folder for applieable constraint files for your synthesis tool.

Special Synchronizers

Based on the 2 flip-flop synchronizer, several "high-level" synchronizers are provided:

  • sync_Strobe synchronizes Strobe-signals across clock-domain-boundaries. A busy signal indicates the synchronization status and can be used as a internal gate-signal to disallow new incoming strobes. A Strobe-signal is only for one clock period active.
  • sync_Command like sync_Strobe, it synchronizes a one clock period active signal across the clock-domain-boundary, but the input has multiple bits. After the multi bit strobe (Command) was transfered, the output goes to its idle value.
  • sync_Vector synchronizes a complete vector across the clock-domain-boundary. A changed detection on the input vector causes a register to latch the current state. The changed event is transfered to the new clock-domain and triggers a register to store the latched content, but in the new clock domain.

These synchronizers also need to be constrained, so static timing analysis will report the correct results. See the constraint folder for applieable constraint files for your synthesis tool.

See PoC.fifo.ic_got for a cross-clock capable FIFO.