diff --git a/compiler/base/wire_spice_model.py b/compiler/base/wire_spice_model.py
index 2e3444207..6ed51e097 100644
--- a/compiler/base/wire_spice_model.py
+++ b/compiler/base/wire_spice_model.py
@@ -18,8 +18,7 @@ def __init__(self, lump_num, wire_length, wire_width):
     def cal_wire_c(self, wire_length, wire_width):
         from openram.tech import spice
         # Convert the F/um^2 to fF/um^2 then multiple by width and length
-        # FIXME: shouldn't it be 1e15?
-        total_c = (spice["wire_unit_c"]*1e12) * wire_length * wire_width
+        total_c = (spice["wire_unit_c"]*1e15) * wire_length * wire_width
         wire_c = total_c / self.lump_num
         return wire_c
 
diff --git a/technology/gf180mcu/tech/tech.py b/technology/gf180mcu/tech/tech.py
index ed54979c9..01f4060eb 100644
--- a/technology/gf180mcu/tech/tech.py
+++ b/technology/gf180mcu/tech/tech.py
@@ -427,15 +427,15 @@
 spice["nom_temperature"] = 25        # Nominal temperature (celcius)
 
 # analytical delay parameters
-spice["nom_threshold"] = 0.49     # Typical Threshold voltage in Volts
-spice["wire_unit_r"] = 0.125     # Unit wire resistance in ohms/square
-spice["wire_unit_c"] = 0.134     # Unit wire capacitance ff/um^2
-spice["min_tx_drain_c"] = 0.7    # Minimum transistor drain capacitance in ff
-spice["min_tx_gate_c"] = 0.2     # Minimum transistor gate capacitance in ff
-spice["dff_setup"] = 102.5391    # DFF setup time in ps
-spice["dff_hold"] = -56          # DFF hold time in ps
-spice["dff_in_cap"] = 6.89       # Input capacitance (D) [Femto-farad]
-spice["dff_out_cap"] = 6.89      # Output capacitance (Q) [Femto-farad]
+spice["nom_threshold"] = 0.49       # Typical Threshold voltage in Volts
+spice["wire_unit_r"] = 0.125        # Unit wire resistance in ohms/square
+spice["wire_unit_c"] = 0.134e-15    # Unit wire capacitance F/um^2
+spice["min_tx_drain_c"] = 0.7       # Minimum transistor drain capacitance in ff
+spice["min_tx_gate_c"] = 0.2        # Minimum transistor gate capacitance in ff
+spice["dff_setup"] = 102.5391       # DFF setup time in ps
+spice["dff_hold"] = -56             # DFF hold time in ps
+spice["dff_in_cap"] = 6.89          # Input capacitance (D) [Femto-farad]
+spice["dff_out_cap"] = 6.89         # Output capacitance (Q) [Femto-farad]
 
 # analytical power parameters, many values are temporary
 spice["bitcell_leakage"] = 1     # Leakage power of a single bitcell in nW
diff --git a/technology/scn3me_subm/tech/tech.py b/technology/scn3me_subm/tech/tech.py
index 6e8b599f5..08ff1349d 100755
--- a/technology/scn3me_subm/tech/tech.py
+++ b/technology/scn3me_subm/tech/tech.py
@@ -257,16 +257,16 @@
 spice["nom_temperature"] = 25        # Nominal temperature (celcius)
 
 # analytical delay parameters
-spice["nom_threshold"] = 1.3   # Typical Threshold voltage in Volts
+spice["nom_threshold"] = 1.3        # Typical Threshold voltage in Volts
 # FIXME: These need to be updated for SCMOS, they are copied from FreePDK45.
-spice["wire_unit_r"] = 0.075    # Unit wire resistance in ohms/square
-spice["wire_unit_c"] = 0.64     # Unit wire capacitance ff/um^2
-spice["min_tx_drain_c"] = 0.7   # Minimum transistor drain capacitance in ff
-spice["min_tx_gate_c"] = 0.1    # Minimum transistor gate capacitance in ff
-spice["dff_setup"] = 9        # DFF setup time in ps
-spice["dff_hold"] = 1         # DFF hold time in ps
-spice["dff_in_cap"] = 9.8242  # Input capacitance (D) [Femto-farad]
-spice["dff_out_cap"] = 2       # Output capacitance (Q) [Femto-farad]
+spice["wire_unit_r"] = 0.075        # Unit wire resistance in ohms/square
+spice["wire_unit_c"] = 0.64e-15     # Unit wire capacitance F/um^2
+spice["min_tx_drain_c"] = 0.7       # Minimum transistor drain capacitance in ff
+spice["min_tx_gate_c"] = 0.1        # Minimum transistor gate capacitance in ff
+spice["dff_setup"] = 9              # DFF setup time in ps
+spice["dff_hold"] = 1               # DFF hold time in ps
+spice["dff_in_cap"] = 9.8242        # Input capacitance (D) [Femto-farad]
+spice["dff_out_cap"] = 2            # Output capacitance (Q) [Femto-farad]
 
 # analytical power parameters, many values are temporary
 spice["bitcell_leakage"] = 1     # Leakage power of a single bitcell in nW
diff --git a/technology/sky130/tech/tech.py b/technology/sky130/tech/tech.py
index c8c642a88..72a306a37 100755
--- a/technology/sky130/tech/tech.py
+++ b/technology/sky130/tech/tech.py
@@ -731,15 +731,15 @@
 spice["nom_temperature"] = 25        # Nominal temperature (celcius)
 
 # analytical delay parameters
-spice["nom_threshold"] = 0.49     # Typical Threshold voltage in Volts
-spice["wire_unit_r"] = 0.125     # Unit wire resistance in ohms/square
-spice["wire_unit_c"] = 0.134     # Unit wire capacitance ff/um^2
-spice["min_tx_drain_c"] = 0.7    # Minimum transistor drain capacitance in ff
-spice["min_tx_gate_c"] = 0.2     # Minimum transistor gate capacitance in ff
-spice["dff_setup"] = 102.5391    # DFF setup time in ps
-spice["dff_hold"] = -56          # DFF hold time in ps
-spice["dff_in_cap"] = 6.89       # Input capacitance (D) [Femto-farad]
-spice["dff_out_cap"] = 6.89      # Output capacitance (Q) [Femto-farad]
+spice["nom_threshold"] = 0.49       # Typical Threshold voltage in Volts
+spice["wire_unit_r"] = 0.125        # Unit wire resistance in ohms/square
+spice["wire_unit_c"] = 0.134e-15    # Unit wire capacitance F/um^2
+spice["min_tx_drain_c"] = 0.7       # Minimum transistor drain capacitance in ff
+spice["min_tx_gate_c"] = 0.2        # Minimum transistor gate capacitance in ff
+spice["dff_setup"] = 102.5391       # DFF setup time in ps
+spice["dff_hold"] = -56             # DFF hold time in ps
+spice["dff_in_cap"] = 6.89          # Input capacitance (D) [Femto-farad]
+spice["dff_out_cap"] = 6.89         # Output capacitance (Q) [Femto-farad]
 
 # analytical power parameters, many values are temporary
 spice["bitcell_leakage"] = 1     # Leakage power of a single bitcell in nW