Update README.md

Author: SoldierChen

README.md

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 The Figure above shows the overview of the ReGraph workflow. 
 
 * **Step 1**: To obtain a custumized accelerator design for a graph application, developers only need to **write user-defined functions (UDFs)** of three stages of a GAS model with the provided programminginterface. 
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 * **Step 2**: ReGraph then takes the UDFs, accelerator templates and platform specific optimizations to **generate a set of synthesizable codes for accelerators** with all possible pipeline combinations. 
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 * **Step 3**: The synthesizable codes are compiled to bitstreams using the Xilinx Vitis toolchain. After that, users **assign the graph for acceleration**. 
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 * **Step 4**: ReGraph reorders vertices based on their in-degrees and partitions the graph.  Then, the task scheduler with the built-in graph-aware task scheduling method **selects the accelerator** with the most suitable numbers of Big and Little pipelines and **generates the scheduling plan**.
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 * **Step 5**: ReGraph deploys the selected accelerator and **runs on the target FPGA**.
 
 
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 ## Programming Interface
 With ReGraph, users can implement different graph accelerators by only writing three high-level functions: `accScatter()`, `accGather()` and `accApply()`. By default, we provide you three build-in graph algorithms, PageRank (PR), Breadth-First Search (BFS) and Closeness Centrality (CC) as examples. The desired application can be compiled by passing argument ```APP=[the algorithm]``` to ``` make ``` command.