Unexpected gate in partition that causes FAIL checking result

[Manchdog]

I have checked the equivalence between two Verilog descriptions in1.v and in2.v.

The checking result is "FAIL", but the generated counterexample contains inner gate and_32 (in gate design) that is not connected with primary output out_11, while there is and_33 gate that is an input for out_11 (see partitioning result in *.json file). I wonder why there is such partition here? Are there any opportunities to construct the specific partitions in EQY?

I've attached an archive with Verilog descriptions, JSON result of partitioning and EQY config too.

Thanks in advance!

eqy_fail.tar.gz