diff --git a/ice40/regressions/issue1158/roclk.json.gz b/ice40/regressions/issue1158/roclk.json.gz
new file mode 100644
index 0000000..7bab3a5
Binary files /dev/null and b/ice40/regressions/issue1158/roclk.json.gz differ
diff --git a/ice40/regressions/issue1158/roclk.npnr b/ice40/regressions/issue1158/roclk.npnr
new file mode 100644
index 0000000..934bac4
--- /dev/null
+++ b/ice40/regressions/issue1158/roclk.npnr
@@ -0,0 +1 @@
+--hx8k --ignore-loops
diff --git a/ice40/regressions/issue1158/roclk.pcf b/ice40/regressions/issue1158/roclk.pcf
new file mode 100644
index 0000000..1873d38
--- /dev/null
+++ b/ice40/regressions/issue1158/roclk.pcf
@@ -0,0 +1,2 @@
+
+set_io --warn-no-port dclk_o   L9
\ No newline at end of file
diff --git a/ice40/regressions/issue1158/roclk.v b/ice40/regressions/issue1158/roclk.v
new file mode 100644
index 0000000..8ef5047
--- /dev/null
+++ b/ice40/regressions/issue1158/roclk.v
@@ -0,0 +1,48 @@
+
+module roclk (
+  output wire dclk_o
+);
+
+wire ro1;
+wire ro2;
+wire ro3;
+
+(* keep *) SB_LUT4 #(
+  .LUT_INIT(16'd1)
+) i_inv1 (
+  .O  ( ro2  ),
+  .I0 ( ro1  ),
+  .I1 ( 1'b0 ),
+  .I2 ( 1'b0 ),
+  .I3 ( 1'b0 )
+);
+
+(* keep *) SB_LUT4 #(
+  .LUT_INIT(16'd1)
+) i_inv2 (
+  .O  ( ro3 ),
+  .I0 ( ro2  ),
+  .I1 ( 1'b0 ),
+  .I2 ( 1'b0 ),
+  .I3 ( 1'b0 )
+);
+
+(* keep *) SB_LUT4 #(
+  .LUT_INIT(16'd1)
+) i_inv3 (
+  .O  ( ro1  ),
+  .I0 ( ro3  ),
+  .I1 ( 1'b0 ),
+  .I2 ( 1'b0 ),
+  .I3 ( 1'b0 )
+);
+
+reg flop;
+
+assign dclk_o = flop;
+
+always @(posedge ro3) begin
+  flop <= ~flop;
+end
+
+endmodule
\ No newline at end of file
diff --git a/ice40/regressions/issue1158/roclk.ys b/ice40/regressions/issue1158/roclk.ys
new file mode 100644
index 0000000..f9629dc
--- /dev/null
+++ b/ice40/regressions/issue1158/roclk.ys
@@ -0,0 +1,4 @@
+read_verilog roclk.v
+hierarchy -top roclk
+synth_ice40
+write_json roclk.json
\ No newline at end of file