CATCH_MISALIGN: misaligned load still writes destination register

[canxin121]

Overview

With CATCH_MISALIGN enabled, PicoRV32 raises the misaligned-load trap but still retires the bogus data into the destination register on the next cycle. Architectural state is corrupted even though a trap is taken.

Expected vs. Observed

• Expected: once a misaligned lw/lh/lb is detected, the core should raise the trap and suppress the register writeback.
• Observed: after the trap message (MISALIGNED WORD or MISALIGNED HALFWORD), the following cycle still performs the register write because the writeback latch remains asserted.

Reproduction

1. Run a short program that loads from an address with bits [1:0] != 0, e.g.:

   li x11, 0x1ffde
   lw x25, 0(x11)

2. Observe in simulation that the trap fires, yet the next cycle records a writeback to x25 with the garbage bus data.

Root Cause

The load pipeline asserts the writeback latch (latched_store, latched_rd, and the load-flavor flags) before performing the misalignment check. The misaligned path raises the trap but leaves those latches untouched, so the fetch stage still commits the register write.

Suggested Fix

Clear the writeback latches as soon as a misaligned load is detected:

if (CATCH_MISALIGN && resetn && mem_do_rdata && mem_wordsize == 0 && reg_op1[1:0] != 0) begin
    latched_store <= 0;
    latched_rd    <= 0;
    latched_is_lu <= 0;
    latched_is_lh <= 0;
    latched_is_lb <= 0;
    // existing trap/IRQ logic...
end

After gating the latches this way, the trap occurs without any register writeback.