CATCH_MISALIGN: misaligned store still drives mem_wstrb on AXI-Lite

[canxin121]

Overview

For misaligned halfword/word stores, PicoRV32 asserts the misaligned-store trap yet still emits a bus transaction with non-zero mem_wstrb. The aligned address receives a partial write, corrupting memory even though the store should be discarded.

Expected vs. Observed

• Expected: a misaligned sh/sw should trigger the trap and keep all write strobes deasserted.
• Observed: running sh x19, 0(x4) to an address with addr[0] = 1 reports MISALIGNED HALFWORD, but the bus trace still shows a write with mem_wstrb = 4'b1100, overwriting the neighboring aligned word.

Reproduction

1. Execute a store to an address with addr[0] = 1 (for halfword) or addr[1:0] != 0 (for word), e.g.:

   li x4, 0x1ffe7
   sh x19, 0(x4)

2. Inspect the memory or bus trace: despite the misalignment trap, the aligned word changes value.

Root Cause

The store path aligns the address before issuing the bus command but forwards the original mem_la_wstrb. When misalignment is detected, nothing cancels those strobes; the AXI-Lite master therefore performs the masked write even though a trap is being raised.

Suggested Fix

Gate the write strobes with a store_misaligned flag so no bus write occurs when misalignment is detected:

wire store_misaligned = CATCH_MISALIGN && resetn &&
                        ((instr_sw && (reg_op1 + decoded_imm)[1:0] != 2'b00) ||
                         (instr_sh && (reg_op1 + decoded_imm)[0]    != 1'b0));

always @(posedge clk) begin
    if (mem_la_write)
        mem_wstrb <= store_misaligned ? 4'b0000 : mem_la_wstrb;
    // existing logic...
end

Masking mem_wstrb like this prevents the unintended AXI write; the trap fires and memory remains untouched.

[robfinch]

Is the AXI write channel disabled as well as the data strobe?