spimemio never enters dual-lane DDR despite README listing it as valid

[5S-MOHAMED-SHABAIK]

Hello,

During flash controller testing in PicoSoC, I observed that spimemio never enters dual-lane DDR mode even though it’s listed as a valid configuration in the README.

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Environment

• PicoSoC build from picosoc/ repo
• MEMIO enabled
• Configuration:

  CRM = 0
  QSPI = 0
  DDR  = 1
  

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Reproduce

We perform this memory write (in C) after reset:

/* Program the control word: CRM=0, QSPI=0, DDR=1, dummy=8, OE=0x3 */
*cfg = 0x80480300
- 0x80000000 // MEMIO enable (controller stays in its automatic fetch path)
- 0x00400000 // DDR bit
- 0x00080000 // dummy cycles = 8
- 0x00000300 // OE = 0x3 (IO0/IO1 driven), it shouldn't matter as we're not in bit-bang mode

Observed Behavior

According to picosoc/README.md, the flash controller supports:

BBh Dual I/O DDR — CRM=0, QSPI=0, DDR=1

However, when simulated:

• Controller sends opcode 0xBB on IO0/IO1
• Toggles both lanes (dual-I/O)
• Still advances data once per SCK edge. behaves as a single-data-rate
• dout_valid asserts only once every full cycle (not per edge)
• True DDR behavior only occurs when both QSPI=1 and DDR=1

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Diagnosis

Relevant logic from picosoc/spimemio.v (around lines 302–335):

wire xfer_dspi = din_ddr && !din_qspi;
wire xfer_ddr  = din_ddr &&  din_qspi;   // DDR only when QSPI is also set

casez ({xfer_ddr, xfer_qspi, xfer_dspi})
  3'b000: ...        // single-bit
  3'b01?: ...        // quad SDR
  3'b11?: ...        // quad DDR (requires both DDR=1 and QSPI=1)
  3'b??1: ...        // DSPI branch (still single data rate)
endcase

When QSPI=0 and DDR=1, the logic falls into the 3'b??1 branch.
That branch decrements count once per clock, sampling once per SCK edge.
xfer_ddr never asserts → no DDR operation performed.

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Clash with Documentation

Source	Mode	Behavior
README	(CRM=0, QSPI=0, DDR=1)	Dual I/O DDR
RTL (spimemio.v)	(CRM=0, QSPI=0, DDR=1)	Dual I/O SDR

The README claims Dual-lane DDR exists, but RTL implements only Dual-lane SDR.

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Possible Fixes

1. RTL fix: Implement true dual-lane DDR support when QSPI=0 && DDR=1.
2. Doc fix: Remove or correct the “BBh Dual I/O DDR” row from README.md
   if only quad DDR (QSPI=1, DDR=1) is supported.

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Questions

1. If I misconfigured the controller, could you point us toward the correct sequence?
2. If not, should the logic treat (QSPI=0, DDR=1) as a valid DDR mode as documented?