@@ -2,9 +2,9 @@ add_library(yosys_passes_pmgen INTERFACE)
22
33function (pmgen_command  _name _path)
44    add_custom_command (
5-         OUTPUT  ${CMAKE_BINARY_DIR } /${_path} /${_name} _pm.h
6-         COMMAND  ${Python3_EXECUTABLE}  ${CMAKE_CURRENT_SOURCE_DIR} /pmgen.py -o ${CMAKE_BINARY_DIR } /${_path} /${_name} _pm.h -p ${_name}  ${CMAKE_SOURCE_DIR } /${_path} /${_name} .pmg
7-         DEPENDS  ${CMAKE_CURRENT_SOURCE_DIR} /pmgen.py ${CMAKE_SOURCE_DIR } /${_path} /${_name} .pmg
5+         OUTPUT  ${yosys_BINARY_DIR } /${_path} /${_name} _pm.h
6+         COMMAND  ${Python3_EXECUTABLE}  ${CMAKE_CURRENT_SOURCE_DIR} /pmgen.py -o ${yosys_BINARY_DIR } /${_path} /${_name} _pm.h -p ${_name}  ${yosys_SOURCE_DIR } /${_path} /${_name} .pmg
7+         DEPENDS  ${CMAKE_CURRENT_SOURCE_DIR} /pmgen.py ${yosys_SOURCE_DIR } /${_path} /${_name} .pmg
88        COMMENT  "Generating ${_path} /${_name} _pm.h..." 
99    )
1010endfunction ()
@@ -22,50 +22,50 @@ pmgen_command(microchip_dsp_cascade techlibs/microchip)
2222pmgen_command(xilinx_srl techlibs/xilinx)
2323
2424add_custom_command (
25-     OUTPUT  ${CMAKE_BINARY_DIR } /passes/opt/peepopt_pm.h
26-     COMMAND  ${Python3_EXECUTABLE}  ${CMAKE_CURRENT_SOURCE_DIR} /pmgen.py -o ${CMAKE_BINARY_DIR } /passes/opt/peepopt_pm.h -p peepopt
27-         ${CMAKE_SOURCE_DIR } /passes/opt/peepopt_shiftmul_right.pmg
28-         ${CMAKE_SOURCE_DIR } /passes/opt/peepopt_shiftmul_left.pmg
29-         ${CMAKE_SOURCE_DIR } /passes/opt/peepopt_shiftadd.pmg
30-         ${CMAKE_SOURCE_DIR } /passes/opt/peepopt_muldiv.pmg
31-         ${CMAKE_SOURCE_DIR } /passes/opt/peepopt_muldiv_c.pmg
32-         ${CMAKE_SOURCE_DIR } /passes/opt/peepopt_formal_clockgateff.pmg
25+     OUTPUT  ${yosys_BINARY_DIR } /passes/opt/peepopt_pm.h
26+     COMMAND  ${Python3_EXECUTABLE}  ${CMAKE_CURRENT_SOURCE_DIR} /pmgen.py -o ${yosys_BINARY_DIR } /passes/opt/peepopt_pm.h -p peepopt
27+         ${yosys_SOURCE_DIR } /passes/opt/peepopt_shiftmul_right.pmg
28+         ${yosys_SOURCE_DIR } /passes/opt/peepopt_shiftmul_left.pmg
29+         ${yosys_SOURCE_DIR } /passes/opt/peepopt_shiftadd.pmg
30+         ${yosys_SOURCE_DIR } /passes/opt/peepopt_muldiv.pmg
31+         ${yosys_SOURCE_DIR } /passes/opt/peepopt_muldiv_c.pmg
32+         ${yosys_SOURCE_DIR } /passes/opt/peepopt_formal_clockgateff.pmg
3333    DEPENDS  ${CMAKE_CURRENT_SOURCE_DIR} /pmgen.py
34-         ${CMAKE_SOURCE_DIR } /passes/opt/peepopt_shiftmul_right.pmg
35-         ${CMAKE_SOURCE_DIR } /passes/opt/peepopt_shiftmul_left.pmg
36-         ${CMAKE_SOURCE_DIR } /passes/opt/peepopt_shiftadd.pmg
37-         ${CMAKE_SOURCE_DIR } /passes/opt/peepopt_muldiv.pmg
38-         ${CMAKE_SOURCE_DIR } /passes/opt/peepopt_muldiv_c.pmg
39-         ${CMAKE_SOURCE_DIR } /passes/opt/peepopt_formal_clockgateff.pmg
34+         ${yosys_SOURCE_DIR } /passes/opt/peepopt_shiftmul_right.pmg
35+         ${yosys_SOURCE_DIR } /passes/opt/peepopt_shiftmul_left.pmg
36+         ${yosys_SOURCE_DIR } /passes/opt/peepopt_shiftadd.pmg
37+         ${yosys_SOURCE_DIR } /passes/opt/peepopt_muldiv.pmg
38+         ${yosys_SOURCE_DIR } /passes/opt/peepopt_muldiv_c.pmg
39+         ${yosys_SOURCE_DIR } /passes/opt/peepopt_formal_clockgateff.pmg
4040    COMMENT  "Generating passes/pmgen/peepopt_pm.h..." 
4141)
4242
4343target_sources (yosys_passes_pmgen INTERFACE 
4444    test_pmgen.cc
45-     ${CMAKE_SOURCE_DIR } /techlibs/ice40/ice40_dsp.cc
46-     ${CMAKE_SOURCE_DIR } /techlibs/ice40/ice40_wrapcarry.cc
47-     ${CMAKE_SOURCE_DIR } /techlibs/xilinx/xilinx_dsp.cc
48-     ${CMAKE_SOURCE_DIR } /techlibs/microchip/microchip_dsp.cc
49-     ${CMAKE_SOURCE_DIR } /passes/opt/peepopt.cc
50-     ${CMAKE_SOURCE_DIR } /techlibs/xilinx/xilinx_srl.cc
45+     ${yosys_SOURCE_DIR } /techlibs/ice40/ice40_dsp.cc
46+     ${yosys_SOURCE_DIR } /techlibs/ice40/ice40_wrapcarry.cc
47+     ${yosys_SOURCE_DIR } /techlibs/xilinx/xilinx_dsp.cc
48+     ${yosys_SOURCE_DIR } /techlibs/microchip/microchip_dsp.cc
49+     ${yosys_SOURCE_DIR } /passes/opt/peepopt.cc
50+     ${yosys_SOURCE_DIR } /techlibs/xilinx/xilinx_srl.cc
5151)
5252
53- target_sources (yosys_passes_pmgen PRIVATE  ${CMAKE_BINARY_DIR } /passes/pmgen/test_pmgen_pm.h)
53+ target_sources (yosys_passes_pmgen PRIVATE  ${yosys_BINARY_DIR } /passes/pmgen/test_pmgen_pm.h)
5454
55- target_sources (yosys_passes_pmgen PRIVATE  ${CMAKE_BINARY_DIR } /techlibs/ice40/ice40_dsp_pm.h)
56- target_sources (yosys_passes_pmgen PRIVATE  ${CMAKE_BINARY_DIR } /techlibs/ice40/ice40_wrapcarry_pm.h)
55+ target_sources (yosys_passes_pmgen PRIVATE  ${yosys_BINARY_DIR } /techlibs/ice40/ice40_dsp_pm.h)
56+ target_sources (yosys_passes_pmgen PRIVATE  ${yosys_BINARY_DIR } /techlibs/ice40/ice40_wrapcarry_pm.h)
5757
58- target_sources (yosys_passes_pmgen PRIVATE  ${CMAKE_BINARY_DIR } /techlibs/xilinx/xilinx_dsp_pm.h)
59- target_sources (yosys_passes_pmgen PRIVATE  ${CMAKE_BINARY_DIR } /techlibs/xilinx/xilinx_dsp48a_pm.h)
60- target_sources (yosys_passes_pmgen PRIVATE  ${CMAKE_BINARY_DIR } /techlibs/xilinx/xilinx_dsp_CREG_pm.h)
61- target_sources (yosys_passes_pmgen PRIVATE  ${CMAKE_BINARY_DIR } /techlibs/xilinx/xilinx_dsp_cascade_pm.h)
58+ target_sources (yosys_passes_pmgen PRIVATE  ${yosys_BINARY_DIR } /techlibs/xilinx/xilinx_dsp_pm.h)
59+ target_sources (yosys_passes_pmgen PRIVATE  ${yosys_BINARY_DIR } /techlibs/xilinx/xilinx_dsp48a_pm.h)
60+ target_sources (yosys_passes_pmgen PRIVATE  ${yosys_BINARY_DIR } /techlibs/xilinx/xilinx_dsp_CREG_pm.h)
61+ target_sources (yosys_passes_pmgen PRIVATE  ${yosys_BINARY_DIR } /techlibs/xilinx/xilinx_dsp_cascade_pm.h)
6262
63- target_sources (yosys_passes_pmgen PRIVATE  ${CMAKE_BINARY_DIR } /techlibs/microchip/microchip_dsp_pm.h)
64- target_sources (yosys_passes_pmgen PRIVATE  ${CMAKE_BINARY_DIR } /techlibs/microchip/microchip_dsp_CREG_pm.h)
65- target_sources (yosys_passes_pmgen PRIVATE  ${CMAKE_BINARY_DIR } /techlibs/microchip/microchip_dsp_cascade_pm.h)
63+ target_sources (yosys_passes_pmgen PRIVATE  ${yosys_BINARY_DIR } /techlibs/microchip/microchip_dsp_pm.h)
64+ target_sources (yosys_passes_pmgen PRIVATE  ${yosys_BINARY_DIR } /techlibs/microchip/microchip_dsp_CREG_pm.h)
65+ target_sources (yosys_passes_pmgen PRIVATE  ${yosys_BINARY_DIR } /techlibs/microchip/microchip_dsp_cascade_pm.h)
6666
67- target_sources (yosys_passes_pmgen PRIVATE  ${CMAKE_BINARY_DIR } /passes/opt/peepopt_pm.h)
67+ target_sources (yosys_passes_pmgen PRIVATE  ${yosys_BINARY_DIR } /passes/opt/peepopt_pm.h)
6868
69- target_sources (yosys_passes_pmgen PRIVATE  ${CMAKE_BINARY_DIR } /techlibs/xilinx/xilinx_srl_pm.h)
69+ target_sources (yosys_passes_pmgen PRIVATE  ${yosys_BINARY_DIR } /techlibs/xilinx/xilinx_srl_pm.h)
7070
7171target_link_libraries (yosys PRIVATE  yosys_passes_pmgen)
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