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Description
Version
Yosys 0.59+0 (git sha1 26b5114, g++ 13.3.0-6ubuntu2~24.04 -fPIC -O3)
On which OS did this happen?
Linux
Reproduction Steps
read_liberty cell_with_q2_issue.lib
library (cell_with_q2_issue) {
delay_model : table_lookup;
voltage_unit : 1V;
current_unit : 1mA;
leakage_power_unit : 1nW;
time_unit : 1ns;
capacitive_load_unit (1, pf);
pulling_resistance_unit : 1kohm;
input_threshold_pct_rise : 50;
input_threshold_pct_fall : 50;
output_threshold_pct_rise : 50;
output_threshold_pct_fall : 50;
slew_lower_threshold_pct_rise : 30;
slew_upper_threshold_pct_rise : 70;
slew_upper_threshold_pct_fall : 70;
slew_lower_threshold_pct_fall : 30;
cell ("cell_with_q2_issue") {
ff (Q1,QN1) {
clocked_on : "CK";
next_state : "(D * !SE + SI * SE)";
clear : "(((!B2B) * !Q2) + !RD)";
preset : "((!B2B) * Q2)";
clear_preset_var1 : "L";
clear_preset_var2 : "H";
}
latch (Q2,QN2) {
enable : "B1";
data_in : "Q1";
}
pin (B1) {
direction : input;
}
pin (B2B) {
direction : input;
}
pin (CK) {
clock : true;
direction : input;
}
pin (D) {
direction : input;
}
pin (Q) {
direction : output;
function : "Q1";
}
pin (RD) {
direction : input;
}
pin (SE) {
direction : input;
}
pin (SI) {
direction : input;
}
}
}
Expected Behavior
No parse error
Actual Behavior
$ yosys
/----------------------------------------------------------------------------\
| yosys -- Yosys Open SYnthesis Suite |
| Copyright (C) 2012 - 2025 Claire Xenia Wolf <[email protected]> |
| Distributed under an ISC-like license, type "license" to see terms |
\----------------------------------------------------------------------------/
Yosys 0.59+0 (git sha1 26b51148a, g++ 13.3.0-6ubuntu2~24.04 -fPIC -O3)
yosys> read_liberty cell_with_q2_issue.lib
1. Executing Liberty frontend: cell_with_q2_issue.lib
ERROR: Can't resolve wire name Q2 in module \cell_with_q2_issue.
Note that I modified the error message to include the offending cell. Would be great if you could update the error message, as well. Otherwise, it's not clear which cell has the issue.