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Setundef doesn't respect selection #5624

@max-kudinov

Description

@max-kudinov

Version

Yosys 0.61+21 (git sha1 967b47d, clang++ 18.1.8 -fPIC -O3)

On which OS did this happen?

Linux

Reproduction Steps

module test;
    wire a = 1'bx;
    wire b = 1'bx;
endmodule

setundef -zero w:a

Expected Behavior

setundef should only target selection, so the value of a driver has to be changed to 0, but b should remain x.

Actual Behavior

setundef changes all wire values to 0, ignoring selection.

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