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Description
Version
Yosys 0.61 (git sha1 5ae48ee, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3)
On which OS did this happen?
Linux
Reproduction Steps
Build yosys 0.61 on Alpine 3.23 with external abc and run tests. The test in tests/techmap/xaiger2-5169.ys is designed to check expected behaviour in the case of malformed input when encountering the line connect \D3 { }as described in issue #5169 and recently added in #5525 fails to fail as expected with following output:
Test: t_wide_write_a7r4w0b0 -> ok
Passed techmap-shiftx2mux.ys
Passed techmap-techmap_chtype.ys
Passed techmap-techmap_replace.ys
Passed techmap-wireinit.ys
Warning: Feature 'abc_new' is experimental.
Warning: Feature 'write_xaiger2' is experimental.
Warning: connection on port D3[0] of instance mux (type CC_MX4) missing, using 1'bx
Passed microchip-ram_SDP.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Feature 'read_xaiger2' is experimental.
ERROR: File `/tmp/yosys-abc-ALKDok/output.aig' not found or is a directory
ERROR: Expected error pattern 'Malformed design' not found !
ERROR: Expected error pattern 'Malformed design' not found !
make[1]: *** [run-test.mk:271: techmap-xaiger2-5169.ys] Error 1
make[1]: Leaving directory '/builds/strophy/aports/testing/yosys/src/tests/techmap'
make: *** [Makefile:990: makefile-tests/tests/techmap] Error 2
make: *** Waiting for unfinished jobs....
Expected Behavior
The test xaiger2-5169.ys should pass by producing the expected string "Malformed design"
Actual Behavior
The test fails to produce the expected error and instead produces the following warning:
Warning: connection on port D3[0] of instance mux (type CC_MX4) missing, using 1'bx
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pending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproduction