From 430adb3b59d58513c64fe47129c6fe2b33fb0b9a Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 28 Aug 2025 18:10:00 +0200 Subject: [PATCH 01/18] write_rtlil: don't sort --- backends/rtlil/rtlil_backend.cc | 2 -- 1 file changed, 2 deletions(-) diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc index cb17432b19d..d7de67bfca0 100644 --- a/backends/rtlil/rtlil_backend.cc +++ b/backends/rtlil/rtlil_backend.cc @@ -456,8 +456,6 @@ struct RTLILBackend : public Backend { } extra_args(f, filename, args, argidx); - design->sort(); - log("Output filename: %s\n", filename); *f << stringf("# Generated by %s\n", yosys_maybe_version()); From d6d1f16c4340279f14a8d752d2af1ce3ec5b1707 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 18:21:30 +0200 Subject: [PATCH 02/18] hashlib: add insertion order const iterator --- kernel/hashlib.h | 18 ++++++++++++++---- kernel/utils.h | 11 +++++++++++ 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/kernel/hashlib.h b/kernel/hashlib.h index c95ce1e7b99..ed329bba68d 100644 --- a/kernel/hashlib.h +++ b/kernel/hashlib.h @@ -569,13 +569,16 @@ class dict { int index; const_iterator(const dict *ptr, int index) : ptr(ptr), index(index) { } public: - typedef std::forward_iterator_tag iterator_category; + typedef std::bidirectional_iterator_tag iterator_category; typedef std::pair value_type; typedef ptrdiff_t difference_type; - typedef std::pair* pointer; - typedef std::pair& reference; + typedef const std::pair* pointer; + typedef const std::pair& reference; const_iterator() { } const_iterator operator++() { index--; return *this; } + const_iterator operator++(int) { const_iterator tmp = *this; index--; return tmp; } + const_iterator operator--() { index++; return *this; } + const_iterator operator--(int) { const_iterator tmp = *this; index++; return tmp; } const_iterator operator+=(int amt) { index -= amt; return *this; } bool operator<(const const_iterator &other) const { return index > other.index; } bool operator==(const const_iterator &other) const { return index == other.index; } @@ -609,6 +612,13 @@ class dict { const std::pair *operator->() const { return &ptr->entries[index].udata; } operator const_iterator() const { return const_iterator(ptr, index); } }; + using reverse_iterator = std::reverse_iterator; + reverse_iterator rbegin() const { + return std::make_reverse_iterator(end()); + } + reverse_iterator rend() const { + return std::make_reverse_iterator(begin()); + } constexpr dict() { @@ -858,7 +868,7 @@ class dict { const_iterator begin() const { return const_iterator(this, int(entries.size())-1); } const_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); } - const_iterator end() const { return const_iterator(nullptr, -1); } + const_iterator end() const { return const_iterator(this, -1); } }; template diff --git a/kernel/utils.h b/kernel/utils.h index 6c9fe36a5f8..5c739aceb08 100644 --- a/kernel/utils.h +++ b/kernel/utils.h @@ -21,6 +21,7 @@ // do not depend on any other components of yosys (except stuff like log_*). #include "kernel/yosys.h" +#include #ifndef UTILS_H #define UTILS_H @@ -276,6 +277,16 @@ inline int ceil_log2(int x) #endif } +template +auto reversed(const T& container) { + struct reverse_view { + const T& cont; + auto begin() const { return cont.rbegin(); } + auto end() const { return cont.rend(); } + }; + return reverse_view{container}; +} + YOSYS_NAMESPACE_END #endif From e11ea42af0e1e3dc1efbfb4f053b268e48b91175 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 18:21:42 +0200 Subject: [PATCH 03/18] raise_error: whitespace --- passes/tests/raise_error.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/tests/raise_error.cc b/passes/tests/raise_error.cc index 7233e78fa7a..b21ec7d1d1f 100644 --- a/passes/tests/raise_error.cc +++ b/passes/tests/raise_error.cc @@ -47,7 +47,7 @@ struct RaiseErrorPass : public Pass { extra_args(args, argidx, design, true); RTLIL::NamedObject *err_obj = nullptr; - + for (auto mod : design->all_selected_modules()) { if (mod->has_attribute(ID::raise_error)) { err_obj = mod->clone(); From 68ad52c6ae9b75ccab3681e2bc90ef97269b9cdc Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 18:22:03 +0200 Subject: [PATCH 04/18] bugpoint: don't sort --- passes/cmds/bugpoint.cc | 2 -- 1 file changed, 2 deletions(-) diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc index 8432c27fda5..897dd845903 100644 --- a/passes/cmds/bugpoint.cc +++ b/passes/cmds/bugpoint.cc @@ -122,8 +122,6 @@ struct BugpointPass : public Pass { int run_yosys(RTLIL::Design *design, string runner, string yosys_cmd, string yosys_arg, string suffix, bool catch_err) { - design->sort(); - string bugpoint_file = "bugpoint-case"; if (suffix.size()) bugpoint_file += stringf(".%.8s", suffix); From 1328a33e829923b544a57d70215b8717c6dbab8a Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 18:22:35 +0200 Subject: [PATCH 05/18] write_rtlil: dump in insertion order --- backends/rtlil/rtlil_backend.cc | 148 ++++++++++++++------------------ backends/rtlil/rtlil_backend.h | 1 + 2 files changed, 64 insertions(+), 85 deletions(-) diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc index d7de67bfca0..8402d3e3d6a 100644 --- a/backends/rtlil/rtlil_backend.cc +++ b/backends/rtlil/rtlil_backend.cc @@ -24,12 +24,23 @@ #include "rtlil_backend.h" #include "kernel/yosys.h" +#include "kernel/utils.h" #include +#include USING_YOSYS_NAMESPACE using namespace RTLIL_BACKEND; YOSYS_NAMESPACE_BEGIN +void RTLIL_BACKEND::dump_attributes(std::ostream &f, std::string indent, const RTLIL::AttrObject *obj) +{ + for (const auto& [name, value] : reversed(obj->attributes)) { + f << stringf("%s" "attribute %s ", indent, name); + dump_const(f, value); + f << stringf("\n"); + } +} + void RTLIL_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int width, int offset, bool autoint) { if (width < 0) @@ -110,8 +121,8 @@ void RTLIL_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, boo dump_sigchunk(f, sig.as_chunk(), autoint); } else { f << stringf("{ "); - for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); ++it) { - dump_sigchunk(f, *it, false); + for (const auto& chunk : reversed(sig.chunks())) { + dump_sigchunk(f, chunk, false); f << stringf(" "); } f << stringf("}"); @@ -120,14 +131,10 @@ void RTLIL_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, boo void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire) { - for (auto &it : wire->attributes) { - f << stringf("%s" "attribute %s ", indent, it.first); - dump_const(f, it.second); - f << stringf("\n"); - } + dump_attributes(f, indent, wire); if (wire->driverCell_) { f << stringf("%s" "# driver %s %s\n", indent, - wire->driverCell()->name.c_str(), wire->driverPort().c_str()); + wire->driverCell()->name, wire->driverPort()); } f << stringf("%s" "wire ", indent); if (wire->width != 1) @@ -149,11 +156,7 @@ void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL:: void RTLIL_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL::Memory *memory) { - for (auto &it : memory->attributes) { - f << stringf("%s" "attribute %s ", indent, it.first); - dump_const(f, it.second); - f << stringf("\n"); - } + dump_attributes(f, indent, memory); f << stringf("%s" "memory ", indent); if (memory->width != 1) f << stringf("width %d ", memory->width); @@ -166,23 +169,19 @@ void RTLIL_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::Cell *cell) { - for (auto &it : cell->attributes) { - f << stringf("%s" "attribute %s ", indent, it.first); - dump_const(f, it.second); - f << stringf("\n"); - } + dump_attributes(f, indent, cell); f << stringf("%s" "cell %s %s\n", indent, cell->type, cell->name); - for (auto &it : cell->parameters) { + for (const auto& [name, param] : reversed(cell->parameters)) { f << stringf("%s parameter%s%s %s ", indent, - (it.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0 ? " signed" : "", - (it.second.flags & RTLIL::CONST_FLAG_REAL) != 0 ? " real" : "", - it.first.c_str()); - dump_const(f, it.second); + (param.flags & RTLIL::CONST_FLAG_SIGNED) != 0 ? " signed" : "", + (param.flags & RTLIL::CONST_FLAG_REAL) != 0 ? " real" : "", + name); + dump_const(f, param); f << stringf("\n"); } - for (auto &it : cell->connections()) { - f << stringf("%s connect %s ", indent, it.first); - dump_sigspec(f, it.second); + for (const auto& [port, sig] : reversed(cell->connections_)) { + f << stringf("%s connect %s ", indent, port); + dump_sigspec(f, sig); f << stringf("\n"); } f << stringf("%s" "end\n", indent); @@ -190,47 +189,38 @@ void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL:: void RTLIL_BACKEND::dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs) { - for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it) - { + for (const auto& [lhs, rhs] : cs->actions) { f << stringf("%s" "assign ", indent); - dump_sigspec(f, it->first); + dump_sigspec(f, lhs); f << stringf(" "); - dump_sigspec(f, it->second); + dump_sigspec(f, rhs); f << stringf("\n"); } - for (auto it = cs->switches.begin(); it != cs->switches.end(); ++it) - dump_proc_switch(f, indent, *it); + for (const auto& sw : cs->switches) + dump_proc_switch(f, indent, sw); } void RTLIL_BACKEND::dump_proc_switch(std::ostream &f, std::string indent, const RTLIL::SwitchRule *sw) { - for (auto it = sw->attributes.begin(); it != sw->attributes.end(); ++it) { - f << stringf("%s" "attribute %s ", indent, it->first); - dump_const(f, it->second); - f << stringf("\n"); - } + dump_attributes(f, indent, sw); f << stringf("%s" "switch ", indent); dump_sigspec(f, sw->signal); f << stringf("\n"); - for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) + for (const auto case_ : sw->cases) { - for (auto ait = (*it)->attributes.begin(); ait != (*it)->attributes.end(); ++ait) { - f << stringf("%s attribute %s ", indent, ait->first); - dump_const(f, ait->second); - f << stringf("\n"); - } + dump_attributes(f, indent, case_); f << stringf("%s case ", indent); - for (size_t i = 0; i < (*it)->compare.size(); i++) { + for (size_t i = 0; i < case_->compare.size(); i++) { if (i > 0) f << stringf(" , "); - dump_sigspec(f, (*it)->compare[i]); + dump_sigspec(f, case_->compare[i]); } f << stringf("\n"); - dump_proc_case_body(f, indent + " ", *it); + dump_proc_case_body(f, indent + " ", case_); } f << stringf("%s" "end\n", indent); @@ -253,20 +243,16 @@ void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RT case RTLIL::STi: f << stringf("init\n"); break; } - for (auto &it: sy->actions) { + for (const auto& [lhs, rhs] : sy->actions) { f << stringf("%s update ", indent); - dump_sigspec(f, it.first); + dump_sigspec(f, lhs); f << stringf(" "); - dump_sigspec(f, it.second); + dump_sigspec(f, rhs); f << stringf("\n"); } for (auto &it: sy->mem_write_actions) { - for (auto it2 = it.attributes.begin(); it2 != it.attributes.end(); ++it2) { - f << stringf("%s attribute %s ", indent, it2->first); - dump_const(f, it2->second); - f << stringf("\n"); - } + dump_attributes(f, indent, &it); f << stringf("%s memwr %s ", indent, it.memid); dump_sigspec(f, it.address); f << stringf(" "); @@ -281,15 +267,11 @@ void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RT void RTLIL_BACKEND::dump_proc(std::ostream &f, std::string indent, const RTLIL::Process *proc) { - for (auto it = proc->attributes.begin(); it != proc->attributes.end(); ++it) { - f << stringf("%s" "attribute %s ", indent, it->first); - dump_const(f, it->second); - f << stringf("\n"); - } + dump_attributes(f, indent, proc); f << stringf("%s" "process %s\n", indent, proc->name); dump_proc_case_body(f, indent + " ", &proc->root_case); - for (auto it = proc->syncs.begin(); it != proc->syncs.end(); ++it) - dump_proc_sync(f, indent + " ", *it); + for (auto* sync : proc->syncs) + dump_proc_sync(f, indent + " ", sync); f << stringf("%s" "end\n", indent); } @@ -309,11 +291,7 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu if (print_header) { - for (auto it = module->attributes.begin(); it != module->attributes.end(); ++it) { - f << stringf("%s" "attribute %s ", indent, it->first); - dump_const(f, it->second); - f << stringf("\n"); - } + dump_attributes(f, indent, module); f << stringf("%s" "module %s\n", indent, module->name); @@ -335,40 +313,40 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu if (print_body) { - for (auto it : module->wires()) - if (!only_selected || design->selected(module, it)) { + for (const auto& [_, wire] : reversed(module->wires_)) + if (!only_selected || design->selected(module, wire)) { if (only_selected) f << stringf("\n"); - dump_wire(f, indent + " ", it); + dump_wire(f, indent + " ", wire); } - for (auto it : module->memories) - if (!only_selected || design->selected(module, it.second)) { + for (const auto& [_, mem] : reversed(module->memories)) + if (!only_selected || design->selected(module, mem)) { if (only_selected) f << stringf("\n"); - dump_memory(f, indent + " ", it.second); + dump_memory(f, indent + " ", mem); } - for (auto it : module->cells()) - if (!only_selected || design->selected(module, it)) { + for (const auto& [_, cell] : reversed(module->cells_)) + if (!only_selected || design->selected(module, cell)) { if (only_selected) f << stringf("\n"); - dump_cell(f, indent + " ", it); + dump_cell(f, indent + " ", cell); } - for (auto it : module->processes) - if (!only_selected || design->selected(module, it.second)) { + for (const auto& [_, process] : reversed(module->processes)) + if (!only_selected || design->selected(module, process)) { if (only_selected) f << stringf("\n"); - dump_proc(f, indent + " ", it.second); + dump_proc(f, indent + " ", process); } bool first_conn_line = true; - for (auto it = module->connections().begin(); it != module->connections().end(); ++it) { + for (const auto& [lhs, rhs] : module->connections()) { bool show_conn = !only_selected || design->selected_whole_module(module->name); if (!show_conn) { - RTLIL::SigSpec sigs = it->first; - sigs.append(it->second); + RTLIL::SigSpec sigs = lhs; + sigs.append(rhs); for (auto &c : sigs.chunks()) { if (c.wire == NULL || !design->selected(module, c.wire)) continue; @@ -378,7 +356,7 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu if (show_conn) { if (only_selected && first_conn_line) f << stringf("\n"); - dump_conn(f, indent + " ", it->first, it->second); + dump_conn(f, indent + " ", lhs, rhs); first_conn_line = false; } } @@ -394,7 +372,7 @@ void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl if (!flag_m) { int count_selected_mods = 0; - for (auto module : design->modules()) { + for (auto* module : design->modules()) { if (design->selected_whole_module(module->name)) flag_m = true; if (design->selected(module)) @@ -410,7 +388,7 @@ void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl f << stringf("autoidx %d\n", autoidx); } - for (auto module : design->modules()) { + for (const auto& [_, module] : reversed(design->modules_)) { if (!only_selected || design->selected(module)) { if (only_selected) f << stringf("\n"); @@ -526,7 +504,7 @@ struct DumpPass : public Pass { if (!empty) { rewrite_filename(filename); std::ofstream *ff = new std::ofstream; - ff->open(filename.c_str(), append ? std::ofstream::app : std::ofstream::trunc); + ff->open(filename, append ? std::ofstream::app : std::ofstream::trunc); if (ff->fail()) { delete ff; log_error("Can't open file `%s' for writing: %s\n", filename, strerror(errno)); diff --git a/backends/rtlil/rtlil_backend.h b/backends/rtlil/rtlil_backend.h index 35829729c56..dd7347def66 100644 --- a/backends/rtlil/rtlil_backend.h +++ b/backends/rtlil/rtlil_backend.h @@ -31,6 +31,7 @@ YOSYS_NAMESPACE_BEGIN namespace RTLIL_BACKEND { + void dump_attributes(std::ostream &f, std::string indent, const RTLIL::AttrObject *obj); void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int offset = 0, bool autoint = true); void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool autoint = true); void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, bool autoint = true); From 118c1890b10f8849f720ad27c817e735f9175f3c Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 18:22:59 +0200 Subject: [PATCH 06/18] raise_error: don't rely on module ordering in test --- tests/bugpoint/raise_error.ys | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/tests/bugpoint/raise_error.ys b/tests/bugpoint/raise_error.ys index 8fb10eb9600..79127deff20 100644 --- a/tests/bugpoint/raise_error.ys +++ b/tests/bugpoint/raise_error.ys @@ -22,34 +22,37 @@ logger -check-expected # raise_error with int exits with status design -load read +setattr -mod -unset raise_error def other +dump bugpoint -suffix error -yosys ../../yosys -command raise_error -expect-return 7 select -assert-mod-count 1 =* select -assert-mod-count 1 top # raise_error -always still uses 'raise_error' attribute if possible design -load read +setattr -mod -unset raise_error def other bugpoint -suffix error -yosys ../../yosys -command "raise_error -always" -expect-return 7 select -assert-mod-count 1 =* select -assert-mod-count 1 top # raise_error with string prints message and exits with 1 design -load read -rename top abc +setattr -mod -unset raise_error top def bugpoint -suffix error -yosys ../../yosys -command raise_error -grep "help me" -expect-return 1 select -assert-mod-count 1 =* select -assert-mod-count 1 other # raise_error with no value exits with 1 design -load read -rename def zzy +setattr -mod -unset raise_error top delete other bugpoint -suffix error -yosys ../../yosys -command raise_error -expect-return 1 select -assert-mod-count 1 =* -select -assert-mod-count 1 zzy +select -assert-mod-count 1 def # raise_error -stderr prints to stderr and exits with 1 design -load read -rename top abc +setattr -mod -unset raise_error top def bugpoint -suffix error -yosys ../../yosys -command "raise_error -stderr" -err-grep "help me" -expect-return 1 select -assert-mod-count 1 =* select -assert-mod-count 1 other From bcc69d5f6ed5c0292c6c7c279cfbf3785358b246 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 19:19:57 +0200 Subject: [PATCH 07/18] write_rtlil: add -sort to match old behavior --- backends/rtlil/rtlil_backend.cc | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc index 8402d3e3d6a..d607be8371f 100644 --- a/backends/rtlil/rtlil_backend.cc +++ b/backends/rtlil/rtlil_backend.cc @@ -416,10 +416,14 @@ struct RTLILBackend : public Backend { log(" -selected\n"); log(" only write selected parts of the design.\n"); log("\n"); + log(" -sort\n"); + log(" sort design in-place (used to be default).\n"); + log("\n"); } void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { bool selected = false; + bool do_sort = false; log_header(design, "Executing RTLIL backend.\n"); @@ -430,12 +434,19 @@ struct RTLILBackend : public Backend { selected = true; continue; } + if (arg == "-sort") { + do_sort = true; + continue; + } break; } extra_args(f, filename, args, argidx); log("Output filename: %s\n", filename); + if (do_sort) + design->sort(); + *f << stringf("# Generated by %s\n", yosys_maybe_version()); RTLIL_BACKEND::dump_design(*f, design, selected, true, false); } From 4215f3c13418e2e3f649e1d6175861a97bdd4701 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 19:50:15 +0200 Subject: [PATCH 08/18] rtlil: add textual roundtrip test --- Makefile | 1 + tests/rtlil/.gitignore | 2 + tests/rtlil/everything.v | 40 + tests/rtlil/roundtrip-text.ref.il | 283 ++++++ tests/rtlil/roundtrip-text.sh | 30 + tests/rtlil/roundtrip-text.synth.ref.il | 1194 +++++++++++++++++++++++ tests/rtlil/run-test.sh | 4 + 7 files changed, 1554 insertions(+) create mode 100644 tests/rtlil/.gitignore create mode 100644 tests/rtlil/everything.v create mode 100644 tests/rtlil/roundtrip-text.ref.il create mode 100644 tests/rtlil/roundtrip-text.sh create mode 100644 tests/rtlil/roundtrip-text.synth.ref.il create mode 100755 tests/rtlil/run-test.sh diff --git a/Makefile b/Makefile index 281f5a868c2..51c0015fd54 100644 --- a/Makefile +++ b/Makefile @@ -889,6 +889,7 @@ MK_TEST_DIRS += tests/sim MK_TEST_DIRS += tests/svtypes MK_TEST_DIRS += tests/techmap MK_TEST_DIRS += tests/various +MK_TEST_DIRS += tests/rtlil ifeq ($(ENABLE_VERIFIC),1) ifneq ($(YOSYS_NOVERIFIC),1) MK_TEST_DIRS += tests/verific diff --git a/tests/rtlil/.gitignore b/tests/rtlil/.gitignore new file mode 100644 index 00000000000..e1661c060a3 --- /dev/null +++ b/tests/rtlil/.gitignore @@ -0,0 +1,2 @@ +*.tmp.il +*.tmp.il.bak \ No newline at end of file diff --git a/tests/rtlil/everything.v b/tests/rtlil/everything.v new file mode 100644 index 00000000000..666d630c21d --- /dev/null +++ b/tests/rtlil/everything.v @@ -0,0 +1,40 @@ +module alu( + input clk, + input [7:0] A, + input [7:0] B, + input [3:0] operation, + output reg [7:0] result, + output reg CF, + output reg ZF, + output reg SF +); + + localparam ALU_OP_ADD = 4'b0000; + localparam ALU_OP_SUB = 4'b0001; + + reg [8:0] tmp; + + always @(posedge clk) + begin + case (operation) + ALU_OP_ADD : + tmp = A + B; + ALU_OP_SUB : + tmp = A - B; + endcase + + CF <= tmp[8]; + ZF <= tmp[7:0] == 0; + SF <= tmp[7]; + + result <= tmp[7:0]; + end +endmodule + +module foo( + input [7:0] a, input [7:0] b, output [7:0] y +); + wire [7:0] bb; + assign b = bb; + assign y = a + bb; +endmodule diff --git a/tests/rtlil/roundtrip-text.ref.il b/tests/rtlil/roundtrip-text.ref.il new file mode 100644 index 00000000000..d67cb362640 --- /dev/null +++ b/tests/rtlil/roundtrip-text.ref.il @@ -0,0 +1,283 @@ +autoidx 15 +attribute \src "everything.v:1.1-32.10" +attribute \cells_not_processed 1 +module \alu + attribute \src "everything.v:2.8-2.11" + wire input 1 \clk + attribute \src "everything.v:3.14-3.15" + wire width 8 input 2 \A + attribute \src "everything.v:4.14-4.15" + wire width 8 input 3 \B + attribute \src "everything.v:5.14-5.23" + wire width 4 input 4 \operation + attribute \src "everything.v:6.19-6.25" + wire width 8 output 5 \result + attribute \src "everything.v:7.13-7.15" + wire output 6 \CF + attribute \src "everything.v:8.13-8.15" + wire output 7 \ZF + attribute \src "everything.v:9.13-9.15" + wire output 8 \SF + attribute \src "everything.v:15.12-15.15" + wire width 9 \tmp + attribute \src "everything.v:17.2-31.5" + wire width 8 $0\result[7:0] + attribute \src "everything.v:17.2-31.5" + wire $0\CF[0:0] + attribute \src "everything.v:17.2-31.5" + wire $0\ZF[0:0] + attribute \src "everything.v:17.2-31.5" + wire $0\SF[0:0] + attribute \src "everything.v:17.2-31.5" + wire width 9 $0\tmp[8:0] + attribute \src "everything.v:17.2-31.5" + wire width 9 $1\tmp[8:0] + attribute \src "everything.v:21.11-21.16" + wire width 9 $add$everything.v:21$2_Y + attribute \src "everything.v:23.11-23.16" + wire width 9 $sub$everything.v:23$3_Y + attribute \src "everything.v:27.9-27.22" + wire $eq$everything.v:27$4_Y + attribute \src "everything.v:21.11-21.16" + cell $add $add$everything.v:21$2 + parameter \A_SIGNED 0 + parameter \B_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 9 + connect \A \A + connect \B \B + connect \Y $add$everything.v:21$2_Y + end + attribute \src "everything.v:23.11-23.16" + cell $sub $sub$everything.v:23$3 + parameter \A_SIGNED 0 + parameter \B_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 9 + connect \A \A + connect \B \B + connect \Y $sub$everything.v:23$3_Y + end + attribute \src "everything.v:27.9-27.22" + cell $eq $eq$everything.v:27$4 + parameter \A_SIGNED 0 + parameter \B_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A $1\tmp[8:0] [7:0] + connect \B 0 + connect \Y $eq$everything.v:27$4_Y + end + attribute \src "everything.v:17.2-31.5" + process $proc$everything.v:17$1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\tmp[8:0] $1\tmp[8:0] + assign $0\CF[0:0] $1\tmp[8:0] [8] + assign $0\ZF[0:0] $eq$everything.v:27$4_Y + assign $0\SF[0:0] $1\tmp[8:0] [7] + assign $0\result[7:0] $1\tmp[8:0] [7:0] + attribute \src "everything.v:19.3-24.10" + switch \operation + attribute \src "everything.v:19.19-19.19" + case 4'0000 + assign { } { } + assign $1\tmp[8:0] $add$everything.v:21$2_Y + attribute \src "everything.v:21.17-21.17" + case 4'0001 + assign { } { } + assign $1\tmp[8:0] $sub$everything.v:23$3_Y + case + assign $1\tmp[8:0] \tmp + end + sync posedge \clk + update \result $0\result[7:0] + update \CF $0\CF[0:0] + update \ZF $0\ZF[0:0] + update \SF $0\SF[0:0] + update \tmp $0\tmp[8:0] + end +end +attribute \src "everything.v:34.1-40.10" +attribute \cells_not_processed 1 +module \foo + attribute \src "everything.v:35.17-35.18" + wire width 8 input 1 \a + attribute \src "everything.v:35.32-35.33" + wire width 8 input 2 \b + attribute \src "everything.v:35.48-35.49" + wire width 8 output 3 \y + attribute \src "everything.v:37.16-37.18" + wire width 8 \bb + attribute \src "everything.v:39.16-39.22" + wire width 8 $add$everything.v:39$5_Y + attribute \src "everything.v:39.16-39.22" + cell $add $add$everything.v:39$5 + parameter \A_SIGNED 0 + parameter \B_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \a + connect \B \bb + connect \Y $add$everything.v:39$5_Y + end + connect \b \bb + connect \y $add$everything.v:39$5_Y +end +attribute \cells_not_processed 1 +attribute \src "everything.v:1.1-32.10" +module \zzz + attribute \src "everything.v:27.9-27.22" + wire $eq$everything.v:27$4_Y + attribute \src "everything.v:23.11-23.16" + wire width 9 $sub$everything.v:23$3_Y + attribute \src "everything.v:21.11-21.16" + wire width 9 $add$everything.v:21$2_Y + attribute \src "everything.v:17.2-31.5" + wire width 9 $1\tmp[8:0] + attribute \src "everything.v:17.2-31.5" + wire width 9 $0\tmp[8:0] + attribute \src "everything.v:17.2-31.5" + wire $0\SF[0:0] + attribute \src "everything.v:17.2-31.5" + wire $0\ZF[0:0] + attribute \src "everything.v:17.2-31.5" + wire $0\CF[0:0] + attribute \src "everything.v:17.2-31.5" + wire width 8 $0\result[7:0] + attribute \src "everything.v:15.12-15.15" + wire width 9 \tmp + attribute \src "everything.v:9.13-9.15" + wire output 8 \SF + attribute \src "everything.v:8.13-8.15" + wire output 7 \ZF + attribute \src "everything.v:7.13-7.15" + wire output 6 \CF + attribute \src "everything.v:6.19-6.25" + wire width 8 output 5 \result + attribute \src "everything.v:5.14-5.23" + wire width 4 input 4 \operation + attribute \src "everything.v:4.14-4.15" + wire width 8 input 3 \B + attribute \src "everything.v:3.14-3.15" + wire width 8 input 2 \A + attribute \src "everything.v:2.8-2.11" + wire input 1 \clk + wire $procmux$8_CMP + wire width 9 $procmux$7_Y + wire $procmux$9_CMP + attribute \src "everything.v:27.9-27.22" + cell $logic_not $eq$everything.v:27$4 + parameter \A_SIGNED 0 + parameter \Y_WIDTH 1 + parameter \A_WIDTH 8 + connect \A $1\tmp[8:0] [7:0] + connect \Y $eq$everything.v:27$4_Y + end + attribute \src "everything.v:23.11-23.16" + cell $sub $sub$everything.v:23$3 + parameter \A_SIGNED 0 + parameter \B_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 9 + connect \A \A + connect \B \B + connect \Y $sub$everything.v:23$3_Y + end + attribute \src "everything.v:21.11-21.16" + cell $add $add$everything.v:21$2 + parameter \A_SIGNED 0 + parameter \B_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 9 + connect \A \A + connect \B \B + connect \Y $add$everything.v:21$2_Y + end + attribute \src "everything.v:19.3-24.10" + attribute \full_case 1 + cell $eq $procmux$8_CMP0 + parameter \A_SIGNED 0 + parameter \B_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 4'0001 + connect \Y $procmux$8_CMP + end + attribute \src "everything.v:19.3-24.10" + attribute \full_case 1 + cell $pmux $procmux$7 + parameter \WIDTH 9 + parameter \S_WIDTH 2 + connect \A \tmp + connect \B { $add$everything.v:21$2_Y $sub$everything.v:23$3_Y } + connect \S { $procmux$9_CMP $procmux$8_CMP } + connect \Y $procmux$7_Y + end + attribute \src "everything.v:19.3-24.10" + attribute \full_case 1 + cell $logic_not $procmux$9_CMP0 + parameter \A_SIGNED 0 + parameter \Y_WIDTH 1 + parameter \A_WIDTH 4 + connect \A \operation + connect \Y $procmux$9_CMP + end + attribute \src "everything.v:17.2-31.5" + cell $dff $procdff$10 + parameter \WIDTH 8 + parameter \CLK_POLARITY 1'1 + connect \D $procmux$7_Y [7:0] + connect \Q \result + connect \CLK \clk + end + attribute \src "everything.v:17.2-31.5" + cell $dff $procdff$11 + parameter \WIDTH 1 + parameter \CLK_POLARITY 1'1 + connect \D $procmux$7_Y [8] + connect \Q \CF + connect \CLK \clk + end + attribute \src "everything.v:17.2-31.5" + cell $dff $procdff$12 + parameter \WIDTH 1 + parameter \CLK_POLARITY 1'1 + connect \D $eq$everything.v:27$4_Y + connect \Q \ZF + connect \CLK \clk + end + attribute \src "everything.v:17.2-31.5" + cell $dff $procdff$13 + parameter \WIDTH 1 + parameter \CLK_POLARITY 1'1 + connect \D $procmux$7_Y [7] + connect \Q \SF + connect \CLK \clk + end + attribute \src "everything.v:17.2-31.5" + cell $dff $procdff$14 + parameter \WIDTH 9 + parameter \CLK_POLARITY 1'1 + connect \D $procmux$7_Y + connect \Q \tmp + connect \CLK \clk + end + connect $0\result[7:0] $1\tmp[8:0] [7:0] + connect $0\SF[0:0] $1\tmp[8:0] [7] + connect $0\ZF[0:0] $eq$everything.v:27$4_Y + connect $0\CF[0:0] $1\tmp[8:0] [8] + connect $0\tmp[8:0] $1\tmp[8:0] + connect $1\tmp[8:0] $procmux$7_Y +end diff --git a/tests/rtlil/roundtrip-text.sh b/tests/rtlil/roundtrip-text.sh new file mode 100644 index 00000000000..7dd0327cac9 --- /dev/null +++ b/tests/rtlil/roundtrip-text.sh @@ -0,0 +1,30 @@ +set -euo pipefail +YS=../../yosys + +# write_rtlil and dump are equivalent +$YS -p "read_verilog -sv everything.v; copy alu zzz; proc zzz; dump -o roundtrip-text.dump.tmp.il; write_rtlil roundtrip-text.write.tmp.il" +sed '/^$/d' -i.bak roundtrip-text.dump.tmp.il +sed '/^$/d' -i.bak roundtrip-text.write.tmp.il +# Trim first line ("Generated by Yosys ...") +tail -n +2 roundtrip-text.write.tmp.il > roundtrip-text.write-nogen.tmp.il +diff roundtrip-text.dump.tmp.il roundtrip-text.write-nogen.tmp.il +diff roundtrip-text.dump.tmp.il roundtrip-text.ref.il + +# Loading and writing it out again doesn't change the RTLIL +$YS -p "read_rtlil roundtrip-text.dump.tmp.il; write_rtlil roundtrip-text.reload.tmp.il" +sed '/^$/d' -i.bak roundtrip-text.reload.tmp.il +tail -n +2 roundtrip-text.reload.tmp.il > roundtrip-text.reload-nogen.tmp.il +diff roundtrip-text.dump.tmp.il roundtrip-text.reload-nogen.tmp.il + +# Hashing differences don't change the RTLIL +$YS --hash-seed=2345678 -p "read_rtlil roundtrip-text.dump.tmp.il; write_rtlil roundtrip-text.reload-hash.tmp.il" +sed '/^$/d' -i.bak roundtrip-text.reload-hash.tmp.il +tail -n +2 roundtrip-text.reload-hash.tmp.il > roundtrip-text.reload-hash-nogen.tmp.il +diff roundtrip-text.dump.tmp.il roundtrip-text.reload-hash-nogen.tmp.il + +echo "Without ABC, we don't get any irreproducibility and can pin that" +echo "Has this test case started failing for you? Consider updating the reference" +$YS -p "read_verilog -sv everything.v; synth -noabc; write_rtlil roundtrip-text.synth.tmp.il" +sed '/^$/d' -i.bak roundtrip-text.synth.tmp.il +tail -n +2 roundtrip-text.synth.tmp.il > roundtrip-text.synth-nogen.tmp.il +diff roundtrip-text.synth-nogen.tmp.il roundtrip-text.synth.ref.il diff --git a/tests/rtlil/roundtrip-text.synth.ref.il b/tests/rtlil/roundtrip-text.synth.ref.il new file mode 100644 index 00000000000..04b27b1c120 --- /dev/null +++ b/tests/rtlil/roundtrip-text.synth.ref.il @@ -0,0 +1,1194 @@ +autoidx 511 +attribute \src "everything.v:34.1-40.10" +module \foo + attribute \src "everything.v:35.48-35.49" + wire width 8 output 3 \y + attribute \src "everything.v:37.16-37.18" + wire width 8 \bb + attribute \src "everything.v:35.32-35.33" + wire width 8 input 2 \b + attribute \src "everything.v:35.17-35.18" + wire width 8 input 1 \a + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$150_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$147_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$173_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$170_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$167_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$164_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$151_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$148_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$155_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$149_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$146_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$143_Y + attribute \unused_bits "7" + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:214.23-214.24" + attribute \force_downto 1 + wire width 8 $auto$alumacc.cc:495:replace_alu$21.lcu.G + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:270.23-270.24" + attribute \force_downto 1 + wire width 8 $auto$alumacc.cc:495:replace_alu$21.X + attribute \unused_bits "7" + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:274.23-274.25" + attribute \force_downto 1 + wire width 8 $auto$alumacc.cc:495:replace_alu$21.CO + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$219 + connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [6] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$173_Y + connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [6] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$218 + connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [4] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$170_Y + connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [4] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$217 + connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [2] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$167_Y + connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [2] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$216 + connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [5] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$164_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$150_Y + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$213 + connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [3] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$155_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$147_Y + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$211 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$150_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$149_Y + connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [5] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$210 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$147_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$146_Y + connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [3] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$209 + connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [1] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$143_Y + connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [1] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$207 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$173_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [5] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [6] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$206 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$170_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [3] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [4] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$205 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$167_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [1] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [2] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$204 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$164_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [3] + connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$151_Y + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$201 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$151_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.X [4] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [5] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$200 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$148_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.X [2] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [3] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$197 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$155_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [1] + connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$148_Y + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$195 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$149_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.lcu.G [4] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [5] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$194 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$146_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.lcu.G [2] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [3] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$193 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$143_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [0] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [1] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$138 + connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [6] + connect \B \b [6] + connect \A \a [6] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$137 + connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [5] + connect \B \b [5] + connect \A \a [5] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$136 + connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [4] + connect \B \b [4] + connect \A \a [4] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$135 + connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [3] + connect \B \b [3] + connect \A \a [3] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$134 + connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [2] + connect \B \b [2] + connect \A \a [2] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$133 + connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [1] + connect \B \b [1] + connect \A \a [1] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$132 + connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [0] + connect \B \b [0] + connect \A \a [0] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$131 + connect \Y $auto$alumacc.cc:495:replace_alu$21.X [7] + connect \B \b [7] + connect \A \a [7] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$130 + connect \Y $auto$alumacc.cc:495:replace_alu$21.X [6] + connect \B \b [6] + connect \A \a [6] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$129 + connect \Y $auto$alumacc.cc:495:replace_alu$21.X [5] + connect \B \b [5] + connect \A \a [5] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$128 + connect \Y $auto$alumacc.cc:495:replace_alu$21.X [4] + connect \B \b [4] + connect \A \a [4] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$127 + connect \Y $auto$alumacc.cc:495:replace_alu$21.X [3] + connect \B \b [3] + connect \A \a [3] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$126 + connect \Y $auto$alumacc.cc:495:replace_alu$21.X [2] + connect \B \b [2] + connect \A \a [2] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$125 + connect \Y $auto$alumacc.cc:495:replace_alu$21.X [1] + connect \B \b [1] + connect \A \a [1] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$124 + connect \Y \y [0] + connect \B \b [0] + connect \A \a [0] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$122 + connect \Y \y [7] + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [6] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [7] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$121 + connect \Y \y [6] + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [5] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [6] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$120 + connect \Y \y [5] + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [4] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [5] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$119 + connect \Y \y [4] + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [3] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [4] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$118 + connect \Y \y [3] + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [2] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [3] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$117 + connect \Y \y [2] + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [1] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [2] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$116 + connect \Y \y [1] + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [0] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [1] + end + connect $auto$alumacc.cc:495:replace_alu$21.X [0] \y [0] + connect $auto$alumacc.cc:495:replace_alu$21.lcu.G [0] $auto$alumacc.cc:495:replace_alu$21.CO [0] + connect \bb \b +end +attribute \src "everything.v:1.1-32.10" +module \alu + attribute \src "everything.v:15.12-15.15" + wire width 9 \tmp + attribute \src "everything.v:6.19-6.25" + wire width 8 output 5 \result + attribute \src "everything.v:5.14-5.23" + wire width 4 input 4 \operation + attribute \src "everything.v:2.8-2.11" + wire input 1 \clk + attribute \src "everything.v:8.13-8.15" + wire output 7 \ZF + attribute \src "everything.v:9.13-9.15" + wire output 8 \SF + attribute \src "everything.v:7.13-7.15" + wire output 6 \CF + attribute \src "everything.v:4.14-4.15" + wire width 8 input 3 \B + attribute \src "everything.v:3.14-3.15" + wire width 8 input 2 \A + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + attribute \src "/home/emil/pulls/yosys/share/techmap.v:270.26-270.27" + attribute \force_downto 1 + wire width 9 $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y + attribute \src "/home/emil/pulls/yosys/share/techmap.v:274.23-274.25" + attribute \force_downto 1 + wire width 9 $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO + attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.21-279.23" + attribute \force_downto 1 + wire width 9 $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$347_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$341_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$338_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$335_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$361_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$358_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$355_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$352_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$349_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$346_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$343_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$340_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$337_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$334_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$331_Y + wire $procmux$9_CMP + wire $procmux$8_CMP + wire $auto$simplemap.cc:254:simplemap_eqne$247 + wire $auto$simplemap.cc:166:logic_reduce$268 + wire width 2 $auto$simplemap.cc:166:logic_reduce$265 + wire $auto$simplemap.cc:166:logic_reduce$235 + wire width 2 $auto$simplemap.cc:166:logic_reduce$232 + wire width 4 $auto$simplemap.cc:166:logic_reduce$227 + wire width 2 $auto$simplemap.cc:125:simplemap_reduce$249 + wire $auto$rtlil.cc:3196:NotGate$497 + wire $auto$opt_dff.cc:247:make_patterns_logic$505 + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:214.23-214.24" + attribute \force_downto 1 + wire width 9 $auto$alumacc.cc:495:replace_alu$18.lcu.G + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:270.26-270.27" + attribute \force_downto 1 + wire width 9 $auto$alumacc.cc:495:replace_alu$18.Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:270.23-270.24" + attribute \force_downto 1 + wire width 9 $auto$alumacc.cc:495:replace_alu$18.X + attribute \unused_bits "8" + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:274.23-274.25" + attribute \force_downto 1 + wire width 9 $auto$alumacc.cc:495:replace_alu$18.CO + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.21-279.23" + attribute \force_downto 1 + wire width 9 $auto$alumacc.cc:495:replace_alu$18.BB + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:268.22-268.23" + attribute \force_downto 1 + wire width 9 $auto$alumacc.cc:495:replace_alu$18.B + attribute \src "everything.v:17.2-31.5" + wire width 8 $0\result[7:0] + attribute \src "everything.v:17.2-31.5" + wire $0\ZF[0:0] + attribute \src "everything.v:17.2-31.5" + wire $0\SF[0:0] + attribute \src "everything.v:17.2-31.5" + wire $0\CF[0:0] + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$481 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [6] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [5] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$480 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [4] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$479 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [2] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$478 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [5] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] + connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$477 + connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y + connect \B $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$476 + connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [7] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$475 + connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [5] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$474 + connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [3] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$473 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [8] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] + connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$471 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] + connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$467 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [1] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$427 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [7] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [6] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [7] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$426 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [6] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [5] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$425 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [5] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [4] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [5] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$424 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [4] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$423 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [3] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [2] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [3] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$422 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [2] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$421 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [1] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [1] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$418 + connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [6] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$361_Y + connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [6] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$417 + connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [4] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$358_Y + connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [4] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$416 + connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [2] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$355_Y + connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [2] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$415 + connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [5] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$352_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$338_Y + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$414 + connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [7] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$349_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$347_Y + end + attribute \src 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$techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$335_Y + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$411 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$341_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$340_Y + connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [7] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$410 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$338_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$337_Y + connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [5] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$409 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$335_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$334_Y + connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [3] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$408 + connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [1] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$331_Y + connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [1] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:231.10-231.28" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$407 + connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [0] + connect \B $auto$alumacc.cc:495:replace_alu$18.X [0] + connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [0] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$405 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$361_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [5] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [6] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$404 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$358_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [4] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$403 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$355_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [1] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [2] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$402 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$352_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$401 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$400 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.X [6] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [7] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$399 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.X [4] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [5] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$398 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.X [2] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [3] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$397 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$349_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$396 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$346_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$338_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$395 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$343_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [1] + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$394 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$340_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.lcu.G [6] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [7] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$393 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$337_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.lcu.G [4] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [5] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$392 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$334_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.lcu.G [2] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [3] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$391 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$331_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [0] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [1] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$326 + connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [7] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [7] + connect \A \A [7] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$325 + connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [6] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [6] + connect \A \A [6] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$324 + connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [5] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [5] + connect \A \A [5] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$323 + connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [4] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [4] + connect \A \A [4] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$322 + connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [3] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [3] + connect \A \A [3] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$321 + connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [2] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [2] + connect \A \A [2] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$320 + connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [1] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [1] + connect \A \A [1] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$319 + connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [0] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] + connect \A \A [0] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$317 + connect \Y $auto$alumacc.cc:495:replace_alu$18.X [7] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [7] + connect \A \A [7] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$316 + connect \Y $auto$alumacc.cc:495:replace_alu$18.X [6] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [6] + connect \A \A [6] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$315 + connect \Y $auto$alumacc.cc:495:replace_alu$18.X [5] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [5] + connect \A \A [5] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$314 + connect \Y $auto$alumacc.cc:495:replace_alu$18.X [4] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [4] + connect \A \A [4] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$313 + connect \Y $auto$alumacc.cc:495:replace_alu$18.X [3] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [3] + connect \A \A [3] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$312 + connect \Y $auto$alumacc.cc:495:replace_alu$18.X [2] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [2] + connect \A \A [2] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$311 + connect \Y $auto$alumacc.cc:495:replace_alu$18.X [1] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [1] + connect \A \A [1] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$310 + connect \Y $auto$alumacc.cc:495:replace_alu$18.X [0] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] + connect \A \A [0] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$308 + connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [8] + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [7] + connect \A $auto$alumacc.cc:495:replace_alu$18.BB [8] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$307 + connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [7] + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [6] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [7] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$306 + connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [6] + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [5] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [6] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$305 + connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [5] + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [4] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [5] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$304 + connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [4] + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [4] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$303 + connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [3] + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [2] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [3] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$302 + connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [2] + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [1] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [2] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$301 + connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [1] + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [0] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [1] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$464 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [7] + connect \A \B [7] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$463 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] + connect \A \B [6] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$462 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [5] + connect \A \B [5] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$461 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] + connect \A \B [4] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$460 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [3] + connect \A \B [3] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$459 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] + connect \A \B [2] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$458 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [1] + connect \A \B [1] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$384 + connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [8] + connect \A $auto$alumacc.cc:495:replace_alu$18.B [8] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$383 + connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [7] + connect \A $auto$alumacc.cc:495:replace_alu$18.B [7] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$382 + connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [6] + connect \A $auto$alumacc.cc:495:replace_alu$18.B [6] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$381 + connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [5] + connect \A $auto$alumacc.cc:495:replace_alu$18.B [5] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$380 + connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [4] + connect \A $auto$alumacc.cc:495:replace_alu$18.B [4] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$379 + connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [3] + connect \A $auto$alumacc.cc:495:replace_alu$18.B [3] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$378 + connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [2] + connect \A $auto$alumacc.cc:495:replace_alu$18.B [2] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$377 + connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [1] + connect \A $auto$alumacc.cc:495:replace_alu$18.B [1] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$376 + connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [0] + connect \A \B [0] + end + attribute \src 0'x + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$299 + connect \Y $auto$alumacc.cc:495:replace_alu$18.B [8] + connect \S $auto$simplemap.cc:254:simplemap_eqne$247 + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [8] + connect \A 1'0 + end + attribute \src 0'x + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$298 + connect \Y $auto$alumacc.cc:495:replace_alu$18.B [7] + connect \S $auto$simplemap.cc:254:simplemap_eqne$247 + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [7] + connect \A \B [7] + end + attribute \src 0'x + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$297 + connect \Y $auto$alumacc.cc:495:replace_alu$18.B [6] + connect \S $auto$simplemap.cc:254:simplemap_eqne$247 + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [6] + connect \A \B [6] + end + attribute \src 0'x + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$296 + connect \Y $auto$alumacc.cc:495:replace_alu$18.B [5] + connect \S $auto$simplemap.cc:254:simplemap_eqne$247 + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [5] + connect \A \B [5] + end + attribute \src 0'x + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$295 + connect \Y $auto$alumacc.cc:495:replace_alu$18.B [4] + connect \S $auto$simplemap.cc:254:simplemap_eqne$247 + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [4] + connect \A \B [4] + end + attribute \src 0'x + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$294 + connect \Y $auto$alumacc.cc:495:replace_alu$18.B [3] + connect \S $auto$simplemap.cc:254:simplemap_eqne$247 + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [3] + connect \A \B [3] + end + attribute \src 0'x + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$293 + connect \Y $auto$alumacc.cc:495:replace_alu$18.B [2] + connect \S $auto$simplemap.cc:254:simplemap_eqne$247 + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [2] + connect \A \B [2] + end + attribute \src 0'x + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$292 + connect \Y $auto$alumacc.cc:495:replace_alu$18.B [1] + connect \S $auto$simplemap.cc:254:simplemap_eqne$247 + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [1] + connect \A \B [1] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$264 + connect \Y $0\CF[0:0] + connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $auto$alumacc.cc:495:replace_alu$18.Y [8] + connect \A 1'x + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$263 + connect \Y $0\SF[0:0] + connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $auto$alumacc.cc:495:replace_alu$18.Y [7] + connect \A \tmp [7] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$262 + connect \Y $0\result[7:0] [6] + connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $auto$alumacc.cc:495:replace_alu$18.Y [6] + connect \A \tmp [6] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$261 + connect \Y $0\result[7:0] [5] + connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $auto$alumacc.cc:495:replace_alu$18.Y [5] + connect \A \tmp [5] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$260 + connect \Y $0\result[7:0] [4] + connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $auto$alumacc.cc:495:replace_alu$18.Y [4] + connect \A \tmp [4] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$259 + connect \Y $0\result[7:0] [3] + connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $auto$alumacc.cc:495:replace_alu$18.Y [3] + connect \A \tmp [3] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$258 + connect \Y $0\result[7:0] [2] + connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $auto$alumacc.cc:495:replace_alu$18.Y [2] + connect \A \tmp [2] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$257 + connect \Y $0\result[7:0] [1] + connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $auto$alumacc.cc:495:replace_alu$18.Y [1] + connect \A \tmp [1] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$256 + connect \Y $0\result[7:0] [0] + connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $auto$alumacc.cc:495:replace_alu$18.Y [0] + connect \A \tmp [0] + end + attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" + cell $_NOT_ $auto$simplemap.cc:204:simplemap_lognot$270 + connect \Y $procmux$9_CMP + connect \A $auto$simplemap.cc:166:logic_reduce$268 + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_NOT_ $auto$simplemap.cc:204:simplemap_lognot$255 + connect \Y $procmux$8_CMP + connect \A $auto$simplemap.cc:254:simplemap_eqne$247 + end + attribute \src "everything.v:27.9-27.22" + cell $_NOT_ $auto$simplemap.cc:204:simplemap_lognot$237 + connect \Y $0\ZF[0:0] + connect \A $auto$simplemap.cc:166:logic_reduce$235 + end + attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$269 + connect \Y $auto$simplemap.cc:166:logic_reduce$268 + connect \B $auto$simplemap.cc:125:simplemap_reduce$249 [1] + connect \A $auto$simplemap.cc:166:logic_reduce$265 [0] + end + attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$267 + connect \Y $auto$simplemap.cc:125:simplemap_reduce$249 [1] + connect \B \operation [3] + connect \A \operation [2] + end + attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$266 + connect \Y $auto$simplemap.cc:166:logic_reduce$265 [0] + connect \B \operation [1] + connect \A \operation [0] + end + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$236 + connect \Y $auto$simplemap.cc:166:logic_reduce$235 + connect \B $auto$simplemap.cc:166:logic_reduce$232 [1] + connect \A $auto$simplemap.cc:166:logic_reduce$232 [0] + end + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$234 + connect \Y $auto$simplemap.cc:166:logic_reduce$232 [1] + connect \B $auto$simplemap.cc:166:logic_reduce$227 [3] + connect \A $auto$simplemap.cc:166:logic_reduce$227 [2] + end + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$233 + connect \Y $auto$simplemap.cc:166:logic_reduce$232 [0] + connect \B $auto$simplemap.cc:166:logic_reduce$227 [1] + connect \A $auto$simplemap.cc:166:logic_reduce$227 [0] + end + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$231 + connect \Y $auto$simplemap.cc:166:logic_reduce$227 [3] + connect \B $0\SF[0:0] + connect \A $0\result[7:0] [6] + end + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$230 + connect \Y $auto$simplemap.cc:166:logic_reduce$227 [2] + connect \B $0\result[7:0] [5] + connect \A $0\result[7:0] [4] + end + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$229 + connect \Y $auto$simplemap.cc:166:logic_reduce$227 [1] + connect \B $0\result[7:0] [3] + connect \A $0\result[7:0] [2] + end + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$228 + connect \Y $auto$simplemap.cc:166:logic_reduce$227 [0] + connect \B $0\result[7:0] [1] + connect \A $0\result[7:0] [0] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_OR_ $auto$simplemap.cc:134:simplemap_reduce$253 + connect \Y $auto$simplemap.cc:254:simplemap_eqne$247 + connect \B $auto$simplemap.cc:125:simplemap_reduce$249 [1] + connect \A $auto$simplemap.cc:125:simplemap_reduce$249 [0] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_OR_ $auto$simplemap.cc:134:simplemap_reduce$250 + connect \Y $auto$simplemap.cc:125:simplemap_reduce$249 [0] + connect \B \operation [1] + connect \A $auto$rtlil.cc:3196:NotGate$497 + end + attribute \src 0'x + cell $_OR_ $auto$simplemap.cc:134:simplemap_reduce$226 + connect \Y $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $procmux$9_CMP + connect \A $procmux$8_CMP + end + cell $_NOT_ $auto$opt_expr.cc:617:replace_const_cells$502 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [8] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [8] + end + cell $_NOT_ $auto$opt_expr.cc:617:replace_const_cells$500 + connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [0] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [0] + end + cell $_NOT_ $auto$opt_expr.cc:617:replace_const_cells$496 + connect \Y $auto$rtlil.cc:3196:NotGate$497 + connect \A \operation [0] + end + attribute \src "everything.v:17.2-31.5" + cell $_DFFE_PP_ $auto$ff.cc:266:slice$504 + connect \Q \CF + connect \E $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \D $0\CF[0:0] + connect \C \clk + end + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$ff.cc:266:slice$289 + connect \Q \tmp [7] + connect \D $0\SF[0:0] + connect \C \clk + end + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$ff.cc:266:slice$288 + connect \Q \tmp [6] + connect \D $0\result[7:0] [6] + connect \C \clk + end + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$ff.cc:266:slice$287 + connect \Q \tmp [5] + connect \D $0\result[7:0] [5] + connect \C \clk + end + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$ff.cc:266:slice$286 + connect \Q \tmp [4] + connect \D $0\result[7:0] [4] + connect \C \clk + end + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$ff.cc:266:slice$285 + connect \Q \tmp [3] + connect \D $0\result[7:0] [3] + connect \C \clk + end + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$ff.cc:266:slice$284 + connect \Q \tmp [2] + connect \D $0\result[7:0] [2] + connect \C \clk + end + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$ff.cc:266:slice$283 + connect \Q \tmp [1] + connect \D $0\result[7:0] [1] + connect \C \clk + end + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$ff.cc:266:slice$282 + connect \Q \tmp [0] + connect \D $0\result[7:0] [0] + connect \C \clk + end + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$ff.cc:266:slice$280 + connect \Q \ZF + connect \D $0\ZF[0:0] + connect \C \clk + end + connect $0\result[7:0] [7] $0\SF[0:0] + connect $auto$alumacc.cc:495:replace_alu$18.B [0] \B [0] + connect $auto$alumacc.cc:495:replace_alu$18.X [8] $auto$alumacc.cc:495:replace_alu$18.BB [8] + connect $auto$alumacc.cc:495:replace_alu$18.lcu.G [8] 1'0 + connect $auto$simplemap.cc:166:logic_reduce$265 [1] $auto$simplemap.cc:125:simplemap_reduce$249 [1] + connect { $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [8] $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [0] } { 1'1 $auto$alumacc.cc:495:replace_alu$18.BB [0] } + connect { $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [7] $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [0] } { $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [8] $auto$alumacc.cc:495:replace_alu$18.BB [0] } + connect $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [0] \B [0] + connect \SF \tmp [7] + connect \result \tmp [7:0] + connect \tmp [8] \CF +end diff --git a/tests/rtlil/run-test.sh b/tests/rtlil/run-test.sh new file mode 100755 index 00000000000..70b282a9a56 --- /dev/null +++ b/tests/rtlil/run-test.sh @@ -0,0 +1,4 @@ +#!/usr/bin/env bash +set -eu +source ../gen-tests-makefile.sh +generate_mk --bash From fdbdd193c1245a4fc3ecbf70bac26d18a11e3b75 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 19:56:28 +0200 Subject: [PATCH 09/18] rtlil: add roundtrip test for design -stash and design -save, fix #5321 --- kernel/rtlil.cc | 1 + tests/rtlil/roundtrip-design.sh | 8 ++++++++ tests/rtlil/roundtrip-text.ref.il | 6 +++--- 3 files changed, 12 insertions(+), 3 deletions(-) create mode 100644 tests/rtlil/roundtrip-design.sh diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 035701cb986..050fc6bd118 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -5993,6 +5993,7 @@ RTLIL::CaseRule *RTLIL::CaseRule::clone() const RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule; new_caserule->compare = compare; new_caserule->actions = actions; + new_caserule->attributes = attributes; for (auto &it : switches) new_caserule->switches.push_back(it->clone()); return new_caserule; diff --git a/tests/rtlil/roundtrip-design.sh b/tests/rtlil/roundtrip-design.sh new file mode 100644 index 00000000000..beacddd8f09 --- /dev/null +++ b/tests/rtlil/roundtrip-design.sh @@ -0,0 +1,8 @@ +set -euo pipefail +YS=../../yosys + +$YS -p "read_verilog -sv everything.v; write_rtlil roundtrip-design-push.tmp.il; design -push; design -pop; write_rtlil roundtrip-design-pop.tmp.il" +diff roundtrip-design-push.tmp.il roundtrip-design-pop.tmp.il + +$YS -p "read_verilog -sv everything.v; write_rtlil roundtrip-design-save.tmp.il; design -save foo; design -load foo; write_rtlil roundtrip-design-load.tmp.il" +diff roundtrip-design-save.tmp.il roundtrip-design-load.tmp.il diff --git a/tests/rtlil/roundtrip-text.ref.il b/tests/rtlil/roundtrip-text.ref.il index d67cb362640..cc45f53dd61 100644 --- a/tests/rtlil/roundtrip-text.ref.il +++ b/tests/rtlil/roundtrip-text.ref.il @@ -203,7 +203,7 @@ module \zzz connect \B \B connect \Y $add$everything.v:21$2_Y end - attribute \src "everything.v:19.3-24.10" + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" attribute \full_case 1 cell $eq $procmux$8_CMP0 parameter \A_SIGNED 0 @@ -215,7 +215,7 @@ module \zzz connect \B 4'0001 connect \Y $procmux$8_CMP end - attribute \src "everything.v:19.3-24.10" + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" attribute \full_case 1 cell $pmux $procmux$7 parameter \WIDTH 9 @@ -225,7 +225,7 @@ module \zzz connect \S { $procmux$9_CMP $procmux$8_CMP } connect \Y $procmux$7_Y end - attribute \src "everything.v:19.3-24.10" + attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" attribute \full_case 1 cell $logic_not $procmux$9_CMP0 parameter \A_SIGNED 0 From 70e681ba7ddcb3e1ee8fb6eb748252a8c63f6148 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 20:36:31 +0200 Subject: [PATCH 10/18] rtlil: move test temporary files to temp directory --- tests/rtlil/.gitignore | 3 +-- tests/rtlil/roundtrip-design.sh | 10 +++++---- tests/rtlil/roundtrip-text.sh | 38 +++++++++++++++++---------------- 3 files changed, 27 insertions(+), 24 deletions(-) diff --git a/tests/rtlil/.gitignore b/tests/rtlil/.gitignore index e1661c060a3..abe251a7683 100644 --- a/tests/rtlil/.gitignore +++ b/tests/rtlil/.gitignore @@ -1,2 +1 @@ -*.tmp.il -*.tmp.il.bak \ No newline at end of file +/temp \ No newline at end of file diff --git a/tests/rtlil/roundtrip-design.sh b/tests/rtlil/roundtrip-design.sh index beacddd8f09..018e363c7f5 100644 --- a/tests/rtlil/roundtrip-design.sh +++ b/tests/rtlil/roundtrip-design.sh @@ -1,8 +1,10 @@ set -euo pipefail YS=../../yosys -$YS -p "read_verilog -sv everything.v; write_rtlil roundtrip-design-push.tmp.il; design -push; design -pop; write_rtlil roundtrip-design-pop.tmp.il" -diff roundtrip-design-push.tmp.il roundtrip-design-pop.tmp.il +mkdir -p temp -$YS -p "read_verilog -sv everything.v; write_rtlil roundtrip-design-save.tmp.il; design -save foo; design -load foo; write_rtlil roundtrip-design-load.tmp.il" -diff roundtrip-design-save.tmp.il roundtrip-design-load.tmp.il +$YS -p "read_verilog -sv everything.v; write_rtlil temp/roundtrip-design-push.il; design -push; design -pop; write_rtlil temp/roundtrip-design-pop.il" +diff temp/roundtrip-design-push.il temp/roundtrip-design-pop.il + +$YS -p "read_verilog -sv everything.v; write_rtlil temp/roundtrip-design-save.il; design -save foo; design -load foo; write_rtlil temp/roundtrip-design-load.il" +diff temp/roundtrip-design-save.il temp/roundtrip-design-load.il diff --git a/tests/rtlil/roundtrip-text.sh b/tests/rtlil/roundtrip-text.sh index 7dd0327cac9..45db7ee726b 100644 --- a/tests/rtlil/roundtrip-text.sh +++ b/tests/rtlil/roundtrip-text.sh @@ -1,30 +1,32 @@ set -euo pipefail YS=../../yosys +mkdir -p temp + # write_rtlil and dump are equivalent -$YS -p "read_verilog -sv everything.v; copy alu zzz; proc zzz; dump -o roundtrip-text.dump.tmp.il; write_rtlil roundtrip-text.write.tmp.il" -sed '/^$/d' -i.bak roundtrip-text.dump.tmp.il -sed '/^$/d' -i.bak roundtrip-text.write.tmp.il +$YS -p "read_verilog -sv everything.v; copy alu zzz; proc zzz; dump -o temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.write.il" +sed '/^$/d' -i.bak temp/roundtrip-text.dump.il +sed '/^$/d' -i.bak temp/roundtrip-text.write.il # Trim first line ("Generated by Yosys ...") -tail -n +2 roundtrip-text.write.tmp.il > roundtrip-text.write-nogen.tmp.il -diff roundtrip-text.dump.tmp.il roundtrip-text.write-nogen.tmp.il -diff roundtrip-text.dump.tmp.il roundtrip-text.ref.il +tail -n +2 temp/roundtrip-text.write.il > temp/roundtrip-text.write-nogen.il +diff temp/roundtrip-text.dump.il temp/roundtrip-text.write-nogen.il +diff temp/roundtrip-text.dump.il roundtrip-text.ref.il # Loading and writing it out again doesn't change the RTLIL -$YS -p "read_rtlil roundtrip-text.dump.tmp.il; write_rtlil roundtrip-text.reload.tmp.il" -sed '/^$/d' -i.bak roundtrip-text.reload.tmp.il -tail -n +2 roundtrip-text.reload.tmp.il > roundtrip-text.reload-nogen.tmp.il -diff roundtrip-text.dump.tmp.il roundtrip-text.reload-nogen.tmp.il +$YS -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload.il" +sed '/^$/d' -i.bak temp/roundtrip-text.reload.il +tail -n +2 temp/roundtrip-text.reload.il > temp/roundtrip-text.reload-nogen.il +diff temp/roundtrip-text.dump.il temp/roundtrip-text.reload-nogen.il # Hashing differences don't change the RTLIL -$YS --hash-seed=2345678 -p "read_rtlil roundtrip-text.dump.tmp.il; write_rtlil roundtrip-text.reload-hash.tmp.il" -sed '/^$/d' -i.bak roundtrip-text.reload-hash.tmp.il -tail -n +2 roundtrip-text.reload-hash.tmp.il > roundtrip-text.reload-hash-nogen.tmp.il -diff roundtrip-text.dump.tmp.il roundtrip-text.reload-hash-nogen.tmp.il +$YS --hash-seed=2345678 -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload-hash.il" +sed '/^$/d' -i.bak temp/roundtrip-text.reload-hash.il +tail -n +2 temp/roundtrip-text.reload-hash.il > temp/roundtrip-text.reload-hash-nogen.il +diff temp/roundtrip-text.dump.il temp/roundtrip-text.reload-hash-nogen.il echo "Without ABC, we don't get any irreproducibility and can pin that" echo "Has this test case started failing for you? Consider updating the reference" -$YS -p "read_verilog -sv everything.v; synth -noabc; write_rtlil roundtrip-text.synth.tmp.il" -sed '/^$/d' -i.bak roundtrip-text.synth.tmp.il -tail -n +2 roundtrip-text.synth.tmp.il > roundtrip-text.synth-nogen.tmp.il -diff roundtrip-text.synth-nogen.tmp.il roundtrip-text.synth.ref.il +$YS -p "read_verilog -sv everything.v; synth -noabc; write_rtlil temp/roundtrip-text.synth.il" +sed '/^$/d' -i.bak temp/roundtrip-text.synth.il +tail -n +2 temp/roundtrip-text.synth.il > temp/roundtrip-text.synth-nogen.il +diff temp/roundtrip-text.synth-nogen.il roundtrip-text.synth.ref.il From 175e024033e06f1696a52488e33811b194c9c1b3 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 20:43:52 +0200 Subject: [PATCH 11/18] functional: in test, rely less on wreduce doing a perfect job --- tests/functional/test_functional.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/functional/test_functional.py b/tests/functional/test_functional.py index 7a09966d897..d4ebc34846a 100644 --- a/tests/functional/test_functional.py +++ b/tests/functional/test_functional.py @@ -24,7 +24,7 @@ def compile_cpp(in_path, out_path, args): run(['g++', '-g', '-std=c++17'] + args + [str(in_path), '-o', str(out_path)]) def yosys_synth(verilog_file, rtlil_file): - yosys(f"read_verilog {quote(verilog_file)} ; prep ; write_rtlil {quote(rtlil_file)}") + yosys(f"read_verilog {quote(verilog_file)} ; prep ; setundef -undriven ; write_rtlil {quote(rtlil_file)}") # simulate an rtlil file with yosys, comparing with a given vcd file, and writing out the yosys simulation results into a second vcd file def yosys_sim(rtlil_file, vcd_reference_file, vcd_out_file, preprocessing = ""): @@ -91,4 +91,4 @@ def test_print_graph(tmp_path): tb_file = base_path / 'tests/functional/picorv32_tb.v' cpu_file = base_path / 'tests/functional/picorv32.v' # currently we only check that we can print the graph without getting an error, not that it prints anything sensibl - yosys(f"read_verilog {quote(tb_file)} {quote(cpu_file)}; prep -top gold; flatten; clk2fflogic; test_generic") + yosys(f"read_verilog {quote(tb_file)} {quote(cpu_file)}; prep -top gold; setundef -undriven ; flatten; clk2fflogic; test_generic") From 73747f6928591a93c723beec1060bd8f1a85cf56 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 3 Sep 2025 01:57:17 +0200 Subject: [PATCH 12/18] read_verilog: add -relativeshare for synthesis reproducibility testing --- frontends/verilog/verilog_frontend.cc | 17 +++++++++++++++ passes/techmap/techmap.cc | 9 ++++++++ techlibs/common/synth.cc | 30 ++++++++++++++++++++------- techlibs/fabulous/synth_fabulous.cc | 2 +- tests/functional/test_functional.py | 4 ++-- 5 files changed, 51 insertions(+), 11 deletions(-) diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 23189127121..0b5e93a1925 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -229,6 +229,10 @@ struct VerilogFrontend : public Frontend { log(" add 'dir' to the directories which are used when searching include\n"); log(" files\n"); log("\n"); + log(" -relativeshare\n"); + log(" use paths relative to share directory for source locations\n"); + log(" where possible (experimental).\n"); + log("\n"); log("The command 'verilog_defaults' can be used to register default options for\n"); log("subsequent calls to 'read_verilog'.\n"); log("\n"); @@ -273,6 +277,7 @@ struct VerilogFrontend : public Frontend { bool flag_nowb = false; bool flag_nosynthesis = false; bool flag_yydebug = false; + bool flag_relative_share = false; define_map_t defines_map; std::list include_dirs; @@ -450,6 +455,11 @@ struct VerilogFrontend : public Frontend { attributes.push_back(RTLIL::escape_id(args[++argidx])); continue; } + if (arg == "-relativeshare") { + flag_relative_share = true; + log_experimental("read_verilog -relativeshare"); + continue; + } if (arg == "-D" && argidx+1 < args.size()) { std::string name = args[++argidx], value; size_t equal = name.find('='); @@ -490,6 +500,13 @@ struct VerilogFrontend : public Frontend { log("Parsing %s%s input from `%s' to AST representation.\n", parse_mode.formal ? "formal " : "", parse_mode.sv ? "SystemVerilog" : "Verilog", filename.c_str()); + log("verilog frontend filename %s\n", filename.c_str()); + if (flag_relative_share) { + auto share_path = proc_share_dirname(); + if (filename.substr(0, share_path.length()) == share_path) + filename = std::string("+/") + filename.substr(share_path.length()); + log("new filename %s\n", filename.c_str()); + } AST::sv_mode_but_global_and_used_for_literally_one_condition = parse_mode.sv; std::string code_after_preproc; diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 30b8e17ab5a..281a8795aa1 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -1032,6 +1032,10 @@ struct TechmapPass : public Pass { log(" -dont_map \n"); log(" leave the given cell type unmapped by ignoring any mapping rules for it\n"); log("\n"); + log(" -relativeshare\n"); + log(" use paths relative to share directory for source locations\n"); + log(" where possible (experimental).\n"); + log("\n"); log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n"); log("match cells with a type that match the text value of this attribute. Otherwise\n"); log("the module name will be used to match the cell. Multiple space-separated cell\n"); @@ -1185,6 +1189,11 @@ struct TechmapPass : public Pass { verilog_frontend += " -I " + args[++argidx]; continue; } + if (args[argidx] == "-relativeshare") { + verilog_frontend += " -relativeshare"; + log_experimental("techmap -relativeshare"); + continue; + } if (args[argidx] == "-assert") { worker.assert_mode = true; continue; diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index 9c85fbbc706..0dbb7cbec7a 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -98,13 +98,17 @@ struct SynthPass : public ScriptPass { log(" mapping library in the `techmap` step. this option can be\n"); log(" repeated.\n"); log("\n"); + log(" -relativeshare\n"); + log(" use paths relative to share directory for source locations\n"); + log(" where possible (experimental).\n"); + log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); } string top_module, fsm_opts, memory_opts, abc; - bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap, booth, hieropt; + bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap, booth, hieropt, relative_share; int lut; std::vector techmap_maps; @@ -124,6 +128,7 @@ struct SynthPass : public ScriptPass { flowmap = false; booth = false; hieropt = false; + relative_share = false; abc = "abc"; techmap_maps.clear(); } @@ -211,6 +216,11 @@ struct SynthPass : public ScriptPass { hieropt = true; continue; } + if (args[argidx] == "-relativeshare") { + relative_share = true; + log_experimental("synth -relativeshare"); + continue; + } break; } extra_args(args, argidx, design); @@ -239,6 +249,10 @@ struct SynthPass : public ScriptPass { else hieropt_flag = hieropt ? " -hier" : ""; + std::string techmap_cmd = "techmap"; + if (relative_share) + techmap_cmd += " -relativeshare"; + if (check_label("begin")) { if (help_mode) { run("hierarchy -check [-top | -auto-top]"); @@ -268,9 +282,9 @@ struct SynthPass : public ScriptPass { run("peepopt"); run("opt_clean"); if (help_mode) - run("techmap -map +/cmp2lut.v -map +/cmp2lcu.v", " (if -lut)"); + run(techmap_cmd + " -map +/cmp2lut.v -map +/cmp2lcu.v", " (if -lut)"); else if (lut) - run(stringf("techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=%d", lut)); + run(stringf("%s -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=%d", techmap_cmd, lut)); if (booth || help_mode) run("booth", " (if -booth)"); if (!noalumacc) @@ -287,22 +301,22 @@ struct SynthPass : public ScriptPass { run("memory_map"); run("opt -full"); if (help_mode) { - run("techmap", " (unless -extra-map)"); - run("techmap -map +/techmap.v -map ", " (if -extra-map)"); + run(techmap_cmd, " (unless -extra-map)"); + run(techmap_cmd + " -map +/techmap.v -map ", " (if -extra-map)"); } else { std::string techmap_opts; if (!techmap_maps.empty()) techmap_opts += " -map +/techmap.v"; for (auto fn : techmap_maps) techmap_opts += stringf(" -map %s", fn); - run("techmap" + techmap_opts); + run(techmap_cmd + techmap_opts); } if (help_mode) { - run("techmap -map +/gate2lut.v", "(if -noabc and -lut)"); + run(techmap_cmd + " -map +/gate2lut.v", "(if -noabc and -lut)"); run("clean; opt_lut", " (if -noabc and -lut)"); run("flowmap -maxlut K", " (if -flowmap and -lut)"); } else if (noabc && lut) { - run(stringf("techmap -map +/gate2lut.v -D LUT_WIDTH=%d", lut)); + run(stringf("%s -map +/gate2lut.v -D LUT_WIDTH=%d", techmap_cmd, lut)); run("clean; opt_lut"); } else if (flowmap) { run(stringf("flowmap -maxlut %d", lut)); diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc index 0e6553fa1c1..60f2a6816cd 100644 --- a/techlibs/fabulous/synth_fabulous.cc +++ b/techlibs/fabulous/synth_fabulous.cc @@ -69,7 +69,7 @@ struct SynthPass : public ScriptPass log(" use the specified Verilog file for extra primitives (can be specified multiple\n"); log(" times).\n"); log("\n"); - log(" -extra-map \n"); + log(" -extra-map \n"); log(" use the specified Verilog file for extra techmap rules (can be specified multiple\n"); log(" times).\n"); log("\n"); diff --git a/tests/functional/test_functional.py b/tests/functional/test_functional.py index d4ebc34846a..e4c78a1fb1b 100644 --- a/tests/functional/test_functional.py +++ b/tests/functional/test_functional.py @@ -24,7 +24,7 @@ def compile_cpp(in_path, out_path, args): run(['g++', '-g', '-std=c++17'] + args + [str(in_path), '-o', str(out_path)]) def yosys_synth(verilog_file, rtlil_file): - yosys(f"read_verilog {quote(verilog_file)} ; prep ; setundef -undriven ; write_rtlil {quote(rtlil_file)}") + yosys(f"read_verilog {quote(verilog_file)} ; prep ; setundef -undriven -undef ; write_rtlil {quote(rtlil_file)}") # simulate an rtlil file with yosys, comparing with a given vcd file, and writing out the yosys simulation results into a second vcd file def yosys_sim(rtlil_file, vcd_reference_file, vcd_out_file, preprocessing = ""): @@ -91,4 +91,4 @@ def test_print_graph(tmp_path): tb_file = base_path / 'tests/functional/picorv32_tb.v' cpu_file = base_path / 'tests/functional/picorv32.v' # currently we only check that we can print the graph without getting an error, not that it prints anything sensibl - yosys(f"read_verilog {quote(tb_file)} {quote(cpu_file)}; prep -top gold; setundef -undriven ; flatten; clk2fflogic; test_generic") + yosys(f"read_verilog {quote(tb_file)} {quote(cpu_file)}; prep -top gold; setundef -undriven -undef ; flatten; clk2fflogic; test_generic") From 7e6126f7533c313b61dada458764c6d822e7f3ca Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 3 Sep 2025 01:58:08 +0200 Subject: [PATCH 13/18] rtlil: fix roundtrip test by eliminating absolute paths from src attributes with -relativeshare --- tests/rtlil/roundtrip-text.sh | 2 +- tests/rtlil/roundtrip-text.synth.ref.il | 562 ++++++++++++------------ 2 files changed, 282 insertions(+), 282 deletions(-) diff --git a/tests/rtlil/roundtrip-text.sh b/tests/rtlil/roundtrip-text.sh index 45db7ee726b..c475a9d9a76 100644 --- a/tests/rtlil/roundtrip-text.sh +++ b/tests/rtlil/roundtrip-text.sh @@ -26,7 +26,7 @@ diff temp/roundtrip-text.dump.il temp/roundtrip-text.reload-hash-nogen.il echo "Without ABC, we don't get any irreproducibility and can pin that" echo "Has this test case started failing for you? Consider updating the reference" -$YS -p "read_verilog -sv everything.v; synth -noabc; write_rtlil temp/roundtrip-text.synth.il" +$YS -p "read_verilog -sv everything.v; synth -relativeshare -noabc; write_rtlil temp/roundtrip-text.synth.il" sed '/^$/d' -i.bak temp/roundtrip-text.synth.il tail -n +2 temp/roundtrip-text.synth.il > temp/roundtrip-text.synth-nogen.il diff temp/roundtrip-text.synth-nogen.il roundtrip-text.synth.ref.il diff --git a/tests/rtlil/roundtrip-text.synth.ref.il b/tests/rtlil/roundtrip-text.synth.ref.il index 04b27b1c120..ab48affc6d1 100644 --- a/tests/rtlil/roundtrip-text.synth.ref.il +++ b/tests/rtlil/roundtrip-text.synth.ref.il @@ -9,276 +9,276 @@ module \foo wire width 8 input 2 \b attribute \src "everything.v:35.17-35.18" wire width 8 input 1 \a - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$150_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$147_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$173_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$170_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$167_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$164_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$151_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$148_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$155_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$149_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$146_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$143_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$150_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$147_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$173_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$170_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$167_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$164_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$151_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$148_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$155_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$149_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$146_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$143_Y attribute \unused_bits "7" - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:214.23-214.24" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:214.23-214.24" attribute \force_downto 1 wire width 8 $auto$alumacc.cc:495:replace_alu$21.lcu.G - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:270.23-270.24" + attribute \src "everything.v:39.16-39.22|+/techmap.v:270.23-270.24" attribute \force_downto 1 wire width 8 $auto$alumacc.cc:495:replace_alu$21.X attribute \unused_bits "7" - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:274.23-274.25" + attribute \src "everything.v:39.16-39.22|+/techmap.v:274.23-274.25" attribute \force_downto 1 wire width 8 $auto$alumacc.cc:495:replace_alu$21.CO - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$219 connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [6] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$173_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$173_Y connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [6] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$218 connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [4] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$170_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$170_Y connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [4] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$217 connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [2] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$167_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$167_Y connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [2] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$216 connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [5] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$164_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$150_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$164_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$150_Y end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$213 connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [3] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$155_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$147_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$155_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$147_Y end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$211 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$150_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$149_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$150_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$149_Y connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [5] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$210 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$147_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$146_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$147_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$146_Y connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [3] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$209 connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [1] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$143_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$143_Y connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [1] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$207 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$173_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$173_Y connect \B $auto$alumacc.cc:495:replace_alu$21.CO [5] connect \A $auto$alumacc.cc:495:replace_alu$21.X [6] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$206 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$170_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$170_Y connect \B $auto$alumacc.cc:495:replace_alu$21.CO [3] connect \A $auto$alumacc.cc:495:replace_alu$21.X [4] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$205 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$167_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$167_Y connect \B $auto$alumacc.cc:495:replace_alu$21.CO [1] connect \A $auto$alumacc.cc:495:replace_alu$21.X [2] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$204 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$164_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$164_Y connect \B $auto$alumacc.cc:495:replace_alu$21.CO [3] - connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$151_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$151_Y end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$201 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$151_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$151_Y connect \B $auto$alumacc.cc:495:replace_alu$21.X [4] connect \A $auto$alumacc.cc:495:replace_alu$21.X [5] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$200 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$148_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$148_Y connect \B $auto$alumacc.cc:495:replace_alu$21.X [2] connect \A $auto$alumacc.cc:495:replace_alu$21.X [3] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$197 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$155_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$155_Y connect \B $auto$alumacc.cc:495:replace_alu$21.CO [1] - connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$148_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$148_Y end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$195 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$149_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$149_Y connect \B $auto$alumacc.cc:495:replace_alu$21.lcu.G [4] connect \A $auto$alumacc.cc:495:replace_alu$21.X [5] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$194 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$146_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$146_Y connect \B $auto$alumacc.cc:495:replace_alu$21.lcu.G [2] connect \A $auto$alumacc.cc:495:replace_alu$21.X [3] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$193 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$143_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$143_Y connect \B $auto$alumacc.cc:495:replace_alu$21.CO [0] connect \A $auto$alumacc.cc:495:replace_alu$21.X [1] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$138 connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [6] connect \B \b [6] connect \A \a [6] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$137 connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [5] connect \B \b [5] connect \A \a [5] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$136 connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [4] connect \B \b [4] connect \A \a [4] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$135 connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [3] connect \B \b [3] connect \A \a [3] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$134 connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [2] connect \B \b [2] connect \A \a [2] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$133 connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [1] connect \B \b [1] connect \A \a [1] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$132 connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [0] connect \B \b [0] connect \A \a [0] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$131 connect \Y $auto$alumacc.cc:495:replace_alu$21.X [7] connect \B \b [7] connect \A \a [7] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$130 connect \Y $auto$alumacc.cc:495:replace_alu$21.X [6] connect \B \b [6] connect \A \a [6] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$129 connect \Y $auto$alumacc.cc:495:replace_alu$21.X [5] connect \B \b [5] connect \A \a [5] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$128 connect \Y $auto$alumacc.cc:495:replace_alu$21.X [4] connect \B \b [4] connect \A \a [4] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$127 connect \Y $auto$alumacc.cc:495:replace_alu$21.X [3] connect \B \b [3] connect \A \a [3] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$126 connect \Y $auto$alumacc.cc:495:replace_alu$21.X [2] connect \B \b [2] connect \A \a [2] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$125 connect \Y $auto$alumacc.cc:495:replace_alu$21.X [1] connect \B \b [1] connect \A \a [1] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$124 connect \Y \y [0] connect \B \b [0] connect \A \a [0] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$122 connect \Y \y [7] connect \B $auto$alumacc.cc:495:replace_alu$21.CO [6] connect \A $auto$alumacc.cc:495:replace_alu$21.X [7] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$121 connect \Y \y [6] connect \B $auto$alumacc.cc:495:replace_alu$21.CO [5] connect \A $auto$alumacc.cc:495:replace_alu$21.X [6] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$120 connect \Y \y [5] connect \B $auto$alumacc.cc:495:replace_alu$21.CO [4] connect \A $auto$alumacc.cc:495:replace_alu$21.X [5] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$119 connect \Y \y [4] connect \B $auto$alumacc.cc:495:replace_alu$21.CO [3] connect \A $auto$alumacc.cc:495:replace_alu$21.X [4] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$118 connect \Y \y [3] connect \B $auto$alumacc.cc:495:replace_alu$21.CO [2] connect \A $auto$alumacc.cc:495:replace_alu$21.X [3] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$117 connect \Y \y [2] connect \B $auto$alumacc.cc:495:replace_alu$21.CO [1] connect \A $auto$alumacc.cc:495:replace_alu$21.X [2] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$116 connect \Y \y [1] connect \B $auto$alumacc.cc:495:replace_alu$21.CO [0] @@ -308,61 +308,61 @@ module \alu wire width 8 input 3 \B attribute \src "everything.v:3.14-3.15" wire width 8 input 2 \A - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y - attribute \src "/home/emil/pulls/yosys/share/techmap.v:270.26-270.27" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$348_Y + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$342_Y + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$339_Y + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$336_Y + attribute \src "+/techmap.v:270.26-270.27" attribute \force_downto 1 wire width 9 $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y - attribute \src "/home/emil/pulls/yosys/share/techmap.v:274.23-274.25" + attribute \src "+/techmap.v:274.23-274.25" attribute \force_downto 1 wire width 9 $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO - attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.21-279.23" + attribute \src "+/techmap.v:279.21-279.23" attribute \force_downto 1 wire width 9 $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$347_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$341_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$338_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$335_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$361_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$358_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$355_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$352_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$349_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$346_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$343_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$340_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$337_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$334_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$331_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$347_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$341_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$338_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$335_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$361_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$358_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$355_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$352_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$348_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$342_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$339_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$336_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$349_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$346_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$343_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$340_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$337_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$334_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$331_Y wire $procmux$9_CMP wire $procmux$8_CMP wire $auto$simplemap.cc:254:simplemap_eqne$247 @@ -374,23 +374,23 @@ module \alu wire width 2 $auto$simplemap.cc:125:simplemap_reduce$249 wire $auto$rtlil.cc:3196:NotGate$497 wire $auto$opt_dff.cc:247:make_patterns_logic$505 - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:214.23-214.24" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:214.23-214.24" attribute \force_downto 1 wire width 9 $auto$alumacc.cc:495:replace_alu$18.lcu.G - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:270.26-270.27" + attribute \src "everything.v:23.11-23.16|+/techmap.v:270.26-270.27" attribute \force_downto 1 wire width 9 $auto$alumacc.cc:495:replace_alu$18.Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:270.23-270.24" + attribute \src "everything.v:23.11-23.16|+/techmap.v:270.23-270.24" attribute \force_downto 1 wire width 9 $auto$alumacc.cc:495:replace_alu$18.X attribute \unused_bits "8" - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:274.23-274.25" + attribute \src "everything.v:23.11-23.16|+/techmap.v:274.23-274.25" attribute \force_downto 1 wire width 9 $auto$alumacc.cc:495:replace_alu$18.CO - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.21-279.23" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.21-279.23" attribute \force_downto 1 wire width 9 $auto$alumacc.cc:495:replace_alu$18.BB - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:268.22-268.23" + attribute \src "everything.v:23.11-23.16|+/techmap.v:268.22-268.23" attribute \force_downto 1 wire width 9 $auto$alumacc.cc:495:replace_alu$18.B attribute \src "everything.v:17.2-31.5" @@ -401,496 +401,496 @@ module \alu wire $0\SF[0:0] attribute \src "everything.v:17.2-31.5" wire $0\CF[0:0] - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$481 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [6] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [5] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$480 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [4] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$479 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [2] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$478 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [5] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] - connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$339_Y end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$477 - connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y - connect \B $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y - connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$348_Y + connect \B $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$339_Y + connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$342_Y end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$476 - connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$342_Y connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [7] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$475 - connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$339_Y connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [5] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$474 - connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$336_Y connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [3] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$473 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [8] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] - connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y + connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$348_Y end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$471 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] - connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$336_Y end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$467 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [1] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$427 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [7] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [6] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [7] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$426 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [6] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [5] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$425 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [5] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [4] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [5] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$424 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [4] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$423 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [3] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [2] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [3] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$422 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [2] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$421 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [1] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [1] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$418 connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [6] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$361_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$361_Y connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [6] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$417 connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [4] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$358_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$358_Y connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [4] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$416 connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [2] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$355_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$355_Y connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [2] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$415 connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [5] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$352_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$338_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$352_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$338_Y end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$414 connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [7] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$349_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$347_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$349_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$347_Y end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$413 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$347_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$346_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$341_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$347_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$346_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$341_Y end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$412 connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [3] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$343_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$335_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$343_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$335_Y end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$411 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$341_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$340_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$341_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$340_Y connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [7] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$410 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$338_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$337_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$338_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$337_Y connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [5] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$409 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$335_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$334_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$335_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$334_Y connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [3] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$408 connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [1] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$331_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$331_Y connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [1] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:231.10-231.28" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:231.10-231.28" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$407 connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [0] connect \B $auto$alumacc.cc:495:replace_alu$18.X [0] connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [0] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$405 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$361_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$361_Y connect \B $auto$alumacc.cc:495:replace_alu$18.CO [5] connect \A $auto$alumacc.cc:495:replace_alu$18.X [6] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$404 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$358_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$358_Y connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] connect \A $auto$alumacc.cc:495:replace_alu$18.X [4] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$403 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$355_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$355_Y connect \B $auto$alumacc.cc:495:replace_alu$18.CO [1] connect \A $auto$alumacc.cc:495:replace_alu$18.X [2] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$402 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$352_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$352_Y connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$339_Y end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$401 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$348_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$339_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$342_Y end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$400 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$342_Y connect \B $auto$alumacc.cc:495:replace_alu$18.X [6] connect \A $auto$alumacc.cc:495:replace_alu$18.X [7] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$399 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$339_Y connect \B $auto$alumacc.cc:495:replace_alu$18.X [4] connect \A $auto$alumacc.cc:495:replace_alu$18.X [5] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$398 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$336_Y connect \B $auto$alumacc.cc:495:replace_alu$18.X [2] connect \A $auto$alumacc.cc:495:replace_alu$18.X [3] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$397 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$349_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$349_Y connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$348_Y end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$396 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$346_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$338_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$346_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$338_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$342_Y end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$395 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$343_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$343_Y connect \B $auto$alumacc.cc:495:replace_alu$18.CO [1] - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$336_Y end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$394 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$340_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$340_Y connect \B $auto$alumacc.cc:495:replace_alu$18.lcu.G [6] connect \A $auto$alumacc.cc:495:replace_alu$18.X [7] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$393 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$337_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$337_Y connect \B $auto$alumacc.cc:495:replace_alu$18.lcu.G [4] connect \A $auto$alumacc.cc:495:replace_alu$18.X [5] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$392 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$334_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$334_Y connect \B $auto$alumacc.cc:495:replace_alu$18.lcu.G [2] connect \A $auto$alumacc.cc:495:replace_alu$18.X [3] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$391 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$331_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$331_Y connect \B $auto$alumacc.cc:495:replace_alu$18.CO [0] connect \A $auto$alumacc.cc:495:replace_alu$18.X [1] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$326 connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [7] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [7] connect \A \A [7] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$325 connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [6] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [6] connect \A \A [6] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$324 connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [5] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [5] connect \A \A [5] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$323 connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [4] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [4] connect \A \A [4] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$322 connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [3] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [3] connect \A \A [3] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$321 connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [2] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [2] connect \A \A [2] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$320 connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [1] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [1] connect \A \A [1] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$319 connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [0] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] connect \A \A [0] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$317 connect \Y $auto$alumacc.cc:495:replace_alu$18.X [7] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [7] connect \A \A [7] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$316 connect \Y $auto$alumacc.cc:495:replace_alu$18.X [6] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [6] connect \A \A [6] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$315 connect \Y $auto$alumacc.cc:495:replace_alu$18.X [5] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [5] connect \A \A [5] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$314 connect \Y $auto$alumacc.cc:495:replace_alu$18.X [4] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [4] connect \A \A [4] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$313 connect \Y $auto$alumacc.cc:495:replace_alu$18.X [3] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [3] connect \A \A [3] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$312 connect \Y $auto$alumacc.cc:495:replace_alu$18.X [2] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [2] connect \A \A [2] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$311 connect \Y $auto$alumacc.cc:495:replace_alu$18.X [1] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [1] connect \A \A [1] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$310 connect \Y $auto$alumacc.cc:495:replace_alu$18.X [0] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] connect \A \A [0] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$308 connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [8] connect \B $auto$alumacc.cc:495:replace_alu$18.CO [7] connect \A $auto$alumacc.cc:495:replace_alu$18.BB [8] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$307 connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [7] connect \B $auto$alumacc.cc:495:replace_alu$18.CO [6] connect \A $auto$alumacc.cc:495:replace_alu$18.X [7] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$306 connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [6] connect \B $auto$alumacc.cc:495:replace_alu$18.CO [5] connect \A $auto$alumacc.cc:495:replace_alu$18.X [6] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$305 connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [5] connect \B $auto$alumacc.cc:495:replace_alu$18.CO [4] connect \A $auto$alumacc.cc:495:replace_alu$18.X [5] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$304 connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [4] connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] connect \A $auto$alumacc.cc:495:replace_alu$18.X [4] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$303 connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [3] connect \B $auto$alumacc.cc:495:replace_alu$18.CO [2] connect \A $auto$alumacc.cc:495:replace_alu$18.X [3] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$302 connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [2] connect \B $auto$alumacc.cc:495:replace_alu$18.CO [1] connect \A $auto$alumacc.cc:495:replace_alu$18.X [2] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$301 connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [1] connect \B $auto$alumacc.cc:495:replace_alu$18.CO [0] connect \A $auto$alumacc.cc:495:replace_alu$18.X [1] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$464 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [7] connect \A \B [7] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$463 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] connect \A \B [6] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$462 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [5] connect \A \B [5] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$461 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] connect \A \B [4] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$460 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [3] connect \A \B [3] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$459 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] connect \A \B [2] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$458 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [1] connect \A \B [1] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$384 connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [8] connect \A $auto$alumacc.cc:495:replace_alu$18.B [8] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$383 connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [7] connect \A $auto$alumacc.cc:495:replace_alu$18.B [7] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$382 connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [6] connect \A $auto$alumacc.cc:495:replace_alu$18.B [6] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$381 connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [5] connect \A $auto$alumacc.cc:495:replace_alu$18.B [5] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$380 connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [4] connect \A $auto$alumacc.cc:495:replace_alu$18.B [4] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$379 connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [3] connect \A $auto$alumacc.cc:495:replace_alu$18.B [3] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$378 connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [2] connect \A $auto$alumacc.cc:495:replace_alu$18.B [2] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$377 connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [1] connect \A $auto$alumacc.cc:495:replace_alu$18.B [1] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$376 connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [0] connect \A \B [0] From 85bcdee23248b258f164e0cf3dad5afc4bd81199 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 3 Sep 2025 15:42:57 +0200 Subject: [PATCH 14/18] rtlil: fix roundtrip test on macOS due to sed non-POSIX non-sense --- tests/rtlil/roundtrip-text.sh | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/tests/rtlil/roundtrip-text.sh b/tests/rtlil/roundtrip-text.sh index c475a9d9a76..7a979879c28 100644 --- a/tests/rtlil/roundtrip-text.sh +++ b/tests/rtlil/roundtrip-text.sh @@ -3,10 +3,17 @@ YS=../../yosys mkdir -p temp +# non-POSIX sed -i inconsistency workaround +remove_empty_lines() { + local file="$1" + sed '/^$/d' "$file" > temp/tmp + mv temp/tmp "$file" +} + # write_rtlil and dump are equivalent $YS -p "read_verilog -sv everything.v; copy alu zzz; proc zzz; dump -o temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.write.il" -sed '/^$/d' -i.bak temp/roundtrip-text.dump.il -sed '/^$/d' -i.bak temp/roundtrip-text.write.il +remove_empty_lines temp/roundtrip-text.dump.il +remove_empty_lines temp/roundtrip-text.write.il # Trim first line ("Generated by Yosys ...") tail -n +2 temp/roundtrip-text.write.il > temp/roundtrip-text.write-nogen.il diff temp/roundtrip-text.dump.il temp/roundtrip-text.write-nogen.il @@ -14,19 +21,19 @@ diff temp/roundtrip-text.dump.il roundtrip-text.ref.il # Loading and writing it out again doesn't change the RTLIL $YS -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload.il" -sed '/^$/d' -i.bak temp/roundtrip-text.reload.il +remove_empty_lines temp/roundtrip-text.reload.il tail -n +2 temp/roundtrip-text.reload.il > temp/roundtrip-text.reload-nogen.il diff temp/roundtrip-text.dump.il temp/roundtrip-text.reload-nogen.il # Hashing differences don't change the RTLIL $YS --hash-seed=2345678 -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload-hash.il" -sed '/^$/d' -i.bak temp/roundtrip-text.reload-hash.il +remove_empty_lines temp/roundtrip-text.reload-hash.il tail -n +2 temp/roundtrip-text.reload-hash.il > temp/roundtrip-text.reload-hash-nogen.il diff temp/roundtrip-text.dump.il temp/roundtrip-text.reload-hash-nogen.il echo "Without ABC, we don't get any irreproducibility and can pin that" echo "Has this test case started failing for you? Consider updating the reference" $YS -p "read_verilog -sv everything.v; synth -relativeshare -noabc; write_rtlil temp/roundtrip-text.synth.il" -sed '/^$/d' -i.bak temp/roundtrip-text.synth.il +remove_empty_lines temp/roundtrip-text.synth.il tail -n +2 temp/roundtrip-text.synth.il > temp/roundtrip-text.synth-nogen.il diff temp/roundtrip-text.synth-nogen.il roundtrip-text.synth.ref.il From e4d4de10202a6757795d221deaca9837814cd5a0 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 16 Sep 2025 17:41:55 +0200 Subject: [PATCH 15/18] driver: add --no-private-id-locs and NEWER_ID --- kernel/driver.cc | 2 ++ kernel/yosys.cc | 13 ++++++++++++- kernel/yosys_common.h | 15 +++++++++++++++ 3 files changed, 29 insertions(+), 1 deletion(-) diff --git a/kernel/driver.cc b/kernel/driver.cc index bbe4e46f381..1274d5fc51b 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -292,6 +292,7 @@ int main(int argc, char **argv) cxxopts::value>(), "") ("g,debug", "globally enable debug log messages") ("perffile", "write a JSON performance log to ", cxxopts::value(), "") + ("no-private-id-locs", "turn off putting source file locations into object IDs") ; options.parse_positional({"infile"}); @@ -436,6 +437,7 @@ int main(int argc, char **argv) log_experimentals_ignored.insert(ignores.begin(), ignores.end()); } if (result.count("perffile")) perffile = result["perffile"].as(); + if (result.count("no-private-id-locs")) yosys_private_id_locs = false; if (result.count("infile")) { frontend_files = result["infile"].as>(); } diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 95beca75c49..78d9ebd08df 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -82,6 +82,7 @@ YOSYS_NAMESPACE_BEGIN int autoidx = 1; int yosys_xtrace = 0; bool yosys_write_versions = true; +bool yosys_private_id_locs = true; const char* yosys_maybe_version() { if (yosys_write_versions) return yosys_version_str; @@ -272,6 +273,16 @@ void yosys_shutdown() } RTLIL::IdString new_id(std::string file, int line, std::string func) +{ + return newer_id(file, line, func); +} + +RTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std::string suffix) +{ + return newer_id_suffix(file, line, func, suffix); +} + +RTLIL::IdString newer_id(std::string file, int line, std::string func) { #ifdef _WIN32 size_t pos = file.find_last_of("/\\"); @@ -288,7 +299,7 @@ RTLIL::IdString new_id(std::string file, int line, std::string func) return stringf("$auto$%s:%d:%s$%d", file, line, func, autoidx++); } -RTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std::string suffix) +RTLIL::IdString newer_id_suffix(std::string file, int line, std::string func, std::string suffix) { #ifdef _WIN32 size_t pos = file.find_last_of("/\\"); diff --git a/kernel/yosys_common.h b/kernel/yosys_common.h index fd84dd74e3b..01f4da3a401 100644 --- a/kernel/yosys_common.h +++ b/kernel/yosys_common.h @@ -268,8 +268,13 @@ inline int GetSize(RTLIL::Wire *wire); extern int autoidx; extern int yosys_xtrace; extern bool yosys_write_versions; +extern bool yosys_private_id_locs; +RTLIL::IdString newer_id(std::string file, int line, std::string func); +RTLIL::IdString newer_id_suffix(std::string file, int line, std::string func, std::string suffix); +[[deprecated("Use NEWER_ID instead of NEW_ID")]] RTLIL::IdString new_id(std::string file, int line, std::string func); +[[deprecated("Use NEWER_ID_SUFFIX instead of NEW_ID_SUFFIX")]] RTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std::string suffix); #define NEW_ID \ @@ -277,6 +282,16 @@ RTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std: #define NEW_ID_SUFFIX(suffix) \ YOSYS_NAMESPACE_PREFIX new_id_suffix(__FILE__, __LINE__, __FUNCTION__, suffix) +#define NEWER_ID \ + (YOSYS_NAMESPACE_PREFIX yosys_private_id_locs ? \ + YOSYS_NAMESPACE_PREFIX newer_id(__FILE__, __LINE__, __FUNCTION__) : \ + YOSYS_NAMESPACE_PREFIX newer_id("?", 0, "?")) + +#define NEWER_ID_SUFFIX(suffix) \ + (YOSYS_NAMESPACE_PREFIX yosys_private_id_locs ? \ + YOSYS_NAMESPACE_PREFIX newer_id_suffix(__FILE__, __LINE__, __FUNCTION__, suffix) : \ + YOSYS_NAMESPACE_PREFIX newer_id_suffix("?", 0, "?", suffix)) + namespace ID = RTLIL::ID; From d2b28d7a25de024aab86cd00eaa2d28db3dfe41e Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 16 Sep 2025 17:43:02 +0200 Subject: [PATCH 16/18] s/NEW_ID/NEWER_ID/g --- backends/aiger2/aiger.cc | 8 +- backends/verilog/verilog_backend.cc | 2 +- .../source/code_examples/extensions/my_cmd.cc | 6 +- frontends/aiger/aigerparse.cc | 10 +- frontends/ast/genrtlil.cc | 10 +- frontends/blif/blifparse.cc | 24 +-- frontends/json/jsonparse.cc | 2 +- frontends/liberty/liberty.cc | 52 ++--- frontends/verific/verific.cc | 46 ++--- frontends/verific/verificsva.cc | 90 ++++----- guidelines/GettingStarted | 4 +- kernel/ff.cc | 104 +++++----- kernel/ffmerge.cc | 4 +- kernel/mem.cc | 90 ++++----- kernel/rtlil.cc | 46 ++--- passes/cmds/abstract.cc | 16 +- passes/cmds/add.cc | 2 +- passes/cmds/bugpoint.cc | 2 +- passes/cmds/chformal.cc | 24 +-- passes/cmds/connect.cc | 2 +- passes/cmds/dft_tag.cc | 84 ++++----- passes/cmds/glift.cc | 2 +- passes/cmds/portarcs.cc | 2 +- passes/cmds/rename.cc | 4 +- passes/cmds/scatter.cc | 2 +- passes/cmds/setundef.cc | 8 +- passes/cmds/splice.cc | 10 +- passes/cmds/xprop.cc | 178 +++++++++--------- passes/equiv/equiv_add.cc | 14 +- passes/equiv/equiv_make.cc | 24 +-- passes/equiv/equiv_miter.cc | 12 +- passes/equiv/equiv_purge.cc | 4 +- passes/equiv/equiv_struct.cc | 4 +- passes/fsm/fsm_map.cc | 26 +-- passes/hierarchy/flatten.cc | 2 +- passes/hierarchy/hierarchy.cc | 12 +- passes/hierarchy/submod.cc | 4 +- passes/memory/memory_bmux2rom.cc | 2 +- passes/memory/memory_bram.cc | 16 +- passes/memory/memory_dff.cc | 6 +- passes/memory/memory_libmap.cc | 28 +-- passes/memory/memory_map.cc | 4 +- passes/memory/memory_memx.cc | 12 +- passes/memory/memory_share.cc | 16 +- passes/opt/muxpack.cc | 2 +- passes/opt/opt_demorgan.cc | 8 +- passes/opt/opt_dff.cc | 60 +++--- passes/opt/opt_expr.cc | 68 +++---- passes/opt/opt_hier.cc | 4 +- passes/opt/opt_mem.cc | 2 +- passes/opt/opt_mem_feedback.cc | 4 +- passes/opt/opt_reduce.cc | 4 +- passes/opt/opt_share.cc | 12 +- passes/opt/peepopt_formal_clockgateff.pmg | 4 +- passes/opt/peepopt_shiftmul_left.pmg | 6 +- passes/opt/pmux2shiftx.cc | 12 +- passes/opt/share.cc | 92 ++++----- passes/opt/wreduce.cc | 2 +- passes/pmgen/README.md | 6 +- passes/pmgen/generate.h | 4 +- passes/pmgen/test_pmgen.cc | 14 +- passes/pmgen/test_pmgen.pmg | 42 ++--- passes/proc/proc_dff.cc | 16 +- passes/proc/proc_dlatch.cc | 10 +- passes/proc/proc_memwr.cc | 6 +- passes/proc/proc_rom.cc | 4 +- passes/sat/assertpmux.cc | 18 +- passes/sat/async2sync.cc | 110 +++++------ passes/sat/clk2fflogic.cc | 60 +++--- passes/sat/cutpoint.cc | 16 +- passes/sat/expose.cc | 8 +- passes/sat/fmcombine.cc | 20 +- passes/sat/fminit.cc | 22 +-- passes/sat/formalff.cc | 18 +- passes/sat/freduce.cc | 6 +- passes/sat/miter.cc | 62 +++--- passes/sat/mutate.cc | 18 +- passes/sat/qbfsat.cc | 4 +- passes/sat/recover_names.cc | 2 +- passes/sat/supercover.cc | 6 +- passes/sat/synthprop.cc | 18 +- passes/techmap/abc9_ops.cc | 24 +-- passes/techmap/aigmap.cc | 12 +- passes/techmap/alumacc.cc | 28 +-- passes/techmap/bmuxmap.cc | 12 +- passes/techmap/booth.cc | 154 +++++++-------- passes/techmap/bufnorm.cc | 4 +- passes/techmap/bwmuxmap.cc | 8 +- passes/techmap/clkbufmap.cc | 10 +- passes/techmap/clockgate.cc | 6 +- passes/techmap/constmap.cc | 4 +- passes/techmap/demuxmap.cc | 8 +- passes/techmap/dfflegalize.cc | 42 ++--- passes/techmap/dfflibmap.cc | 10 +- passes/techmap/extract_counter.cc | 8 +- passes/techmap/extract_fa.cc | 36 ++-- passes/techmap/extract_reduce.cc | 6 +- passes/techmap/extractinv.cc | 4 +- passes/techmap/flowmap.cc | 4 +- passes/techmap/hilomap.cc | 8 +- passes/techmap/insbuf.cc | 2 +- passes/techmap/iopadmap.cc | 4 +- passes/techmap/lut2mux.cc | 12 +- passes/techmap/maccmap.cc | 40 ++-- passes/techmap/muxcover.cc | 16 +- passes/techmap/pmuxtree.cc | 10 +- passes/techmap/shregmap.cc | 4 +- passes/techmap/simplemap.cc | 48 ++--- passes/techmap/techmap.cc | 4 +- passes/techmap/tribuf.cc | 12 +- passes/tests/test_cell.cc | 6 +- techlibs/anlogic/anlogic_fixcarry.cc | 6 +- techlibs/efinix/efinix_fixcarry.cc | 4 +- techlibs/gatemate/gatemate_foldinv.cc | 2 +- techlibs/ice40/ice40_dsp.cc | 30 +-- techlibs/ice40/ice40_dsp.pmg | 2 +- techlibs/ice40/ice40_wrapcarry.cc | 6 +- techlibs/microchip/microchip_dffopt.cc | 10 +- techlibs/microchip/microchip_dsp.cc | 16 +- techlibs/microchip/microchip_dsp_cascade.pmg | 2 +- techlibs/nanoxplore/nx_carry.cc | 8 +- techlibs/quicklogic/ql_bram_merge.cc | 2 +- techlibs/quicklogic/ql_dsp_macc.cc | 10 +- techlibs/quicklogic/ql_dsp_simd.cc | 4 +- techlibs/quicklogic/ql_ioff.cc | 4 +- techlibs/xilinx/xilinx_dffopt.cc | 14 +- techlibs/xilinx/xilinx_dsp.cc | 42 ++--- techlibs/xilinx/xilinx_dsp_cascade.pmg | 6 +- techlibs/xilinx/xilinx_srl.cc | 4 +- techlibs/xilinx/xilinx_srl.pmg | 44 ++--- 130 files changed, 1276 insertions(+), 1276 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index c7ed3b81f0f..99dbffc3e35 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -1040,7 +1040,7 @@ struct XAigerWriter : AigerWriter { for (auto [cursor, box, def] : opaque_boxes) append_box_ports(box, cursor, false); - holes_module = design->addModule(NEW_ID); + holes_module = design->addModule(NEWER_ID); std::vector holes_pis; int boxes_ci_num = 0, boxes_co_num = 0; @@ -1058,7 +1058,7 @@ struct XAigerWriter : AigerWriter { for (auto [cursor, box, def] : nonopaque_boxes) { // use `def->name` not `box->type` as we want the derived type - Cell *holes_wb = holes_module->addCell(NEW_ID, def->name); + Cell *holes_wb = holes_module->addCell(NEWER_ID, def->name); int holes_pi_idx = 0; if (map_file.is_open()) { @@ -1097,7 +1097,7 @@ struct XAigerWriter : AigerWriter { SigSpec in_conn; for (int i = 0; i < port->width; i++) { while (holes_pi_idx >= (int) holes_pis.size()) { - Wire *w = holes_module->addWire(NEW_ID, 1); + Wire *w = holes_module->addWire(NEWER_ID, 1); w->port_input = true; holes_module->ports.push_back(w->name); holes_pis.push_back(w); @@ -1126,7 +1126,7 @@ struct XAigerWriter : AigerWriter { boxes_ci_num += port->width; // holes - Wire *w = holes_module->addWire(NEW_ID, port->width); + Wire *w = holes_module->addWire(NEWER_ID, port->width); w->port_output = true; holes_module->ports.push_back(w->name); holes_wb->setPort(port_id, w); diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index b03639b8d35..987dc3ae109 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -2372,7 +2372,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) } f << stringf(");\n"); if (!systemverilog && !module->processes.empty()) { - initial_id = NEW_ID; + initial_id = NEWER_ID; f << indent + " " << "reg " << id(initial_id) << " = 0;\n"; } diff --git a/docs/source/code_examples/extensions/my_cmd.cc b/docs/source/code_examples/extensions/my_cmd.cc index d52268b4af2..9b09a8eec42 100644 --- a/docs/source/code_examples/extensions/my_cmd.cc +++ b/docs/source/code_examples/extensions/my_cmd.cc @@ -38,9 +38,9 @@ struct Test1Pass : public Pass { y->port_output = true; y->port_id = 2; - RTLIL::Wire *a_inv = module->addWire(NEW_ID, 4); - module->addNeg(NEW_ID, a, a_inv, true); - module->addMux(NEW_ID, a, a_inv, RTLIL::SigSpec(a, 3), y); + RTLIL::Wire *a_inv = module->addWire(NEWER_ID, 4); + module->addNeg(NEWER_ID, a, a_inv, true); + module->addMux(NEWER_ID, a, a_inv, RTLIL::SigSpec(a, 3), y); module->fixup_ports(); } diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 70d94faffea..8b8e31f1950 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -559,9 +559,9 @@ void AigerReader::parse_aiger_ascii() RTLIL::Wire *d_wire = createWireIfNotExists(module, l2); if (clk_wire) - module->addDffGate(NEW_ID, clk_wire, d_wire, q_wire); + module->addDffGate(NEWER_ID, clk_wire, d_wire, q_wire); else - module->addFfGate(NEW_ID, d_wire, q_wire); + module->addFfGate(NEWER_ID, d_wire, q_wire); // Reset logic is optional in AIGER 1.9 if (f.peek() == ' ') { @@ -683,9 +683,9 @@ void AigerReader::parse_aiger_binary() RTLIL::Wire *d_wire = createWireIfNotExists(module, l2); if (clk_wire) - module->addDff(NEW_ID, clk_wire, d_wire, q_wire); + module->addDff(NEWER_ID, clk_wire, d_wire, q_wire); else - module->addFf(NEW_ID, d_wire, q_wire); + module->addFf(NEWER_ID, d_wire, q_wire); // Reset logic is optional in AIGER 1.9 if (f.peek() == ' ') { @@ -795,7 +795,7 @@ void AigerReader::post_process() log_assert(q->port_input); q->port_input = false; - Cell* ff = module->addFfGate(NEW_ID, d, q); + Cell* ff = module->addFfGate(NEWER_ID, d, q); ff->attributes[ID::abc9_mergeability] = mergeability[i]; q->attributes[ID::init] = initial_state[i]; } diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 262dda43ba3..815e81ba1f9 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -822,7 +822,7 @@ struct AST_INTERNAL::ProcessGenerator RTLIL::SigSpec check = ast->children[0]->genWidthRTLIL(-1, false, &subst_rvalue_map.stdmap()); if (GetSize(check) != 1) - check = current_module->ReduceBool(NEW_ID, check); + check = current_module->ReduceBool(NEWER_ID, check); Wire *en = current_module->addWire(cellname.str() + "_EN", 1); set_src_attr(en, ast); @@ -1626,11 +1626,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) RTLIL::SigSpec shift_val = fake_ast->children[1]->genRTLIL(fake_ast_width, fake_ast_sign); if (source_offset != 0) { - shift_val = current_module->Sub(NEW_ID, shift_val, source_offset, fake_ast_sign); + shift_val = current_module->Sub(NEWER_ID, shift_val, source_offset, fake_ast_sign); fake_ast->children[1]->is_signed = true; } if (id2ast->range_swapped) { - shift_val = current_module->Sub(NEW_ID, RTLIL::SigSpec(source_width - width), shift_val, fake_ast_sign); + shift_val = current_module->Sub(NEWER_ID, RTLIL::SigSpec(source_width - width), shift_val, fake_ast_sign); fake_ast->children[1]->is_signed = true; } if (GetSize(shift_val) >= 32) @@ -2028,7 +2028,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) RTLIL::SigSpec check = children[0]->genRTLIL(); if (GetSize(check) != 1) - check = current_module->ReduceBool(NEW_ID, check); + check = current_module->ReduceBool(NEWER_ID, check); RTLIL::Cell *cell = current_module->addCell(cellname, ID($check)); set_src_attr(cell, this); @@ -2130,7 +2130,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } else if (arg->is_signed) { // non-trivial signed nodes are indirected through // signed wires to enable sign extension - RTLIL::IdString wire_name = NEW_ID; + RTLIL::IdString wire_name = NEWER_ID; RTLIL::Wire *wire = current_module->addWire(wire_name, GetSize(sig)); wire->is_signed = true; current_module->connect(wire, sig); diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index 741dd07d6d2..33ba4d27393 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -363,19 +363,19 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool goto no_latch_clock; if (!strcmp(edge, "re")) - cell = module->addDff(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q)); + cell = module->addDff(NEWER_ID, blif_wire(clock), blif_wire(d), blif_wire(q)); else if (!strcmp(edge, "fe")) - cell = module->addDff(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false); + cell = module->addDff(NEWER_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false); else if (!strcmp(edge, "ah")) - cell = module->addDlatch(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q)); + cell = module->addDlatch(NEWER_ID, blif_wire(clock), blif_wire(d), blif_wire(q)); else if (!strcmp(edge, "al")) - cell = module->addDlatch(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false); + cell = module->addDlatch(NEWER_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false); else { no_latch_clock: if (dff_name.empty()) { - cell = module->addFf(NEW_ID, blif_wire(d), blif_wire(q)); + cell = module->addFf(NEWER_ID, blif_wire(d), blif_wire(q)); } else { - cell = module->addCell(NEW_ID, dff_name); + cell = module->addCell(NEWER_ID, dff_name); cell->setPort(ID::D, blif_wire(d)); cell->setPort(ID::Q, blif_wire(q)); } @@ -394,7 +394,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool goto error; IdString celltype = RTLIL::escape_id(p); - RTLIL::Cell *cell = module->addCell(NEW_ID, celltype); + RTLIL::Cell *cell = module->addCell(NEWER_ID, celltype); RTLIL::Module *cell_mod = design->module(celltype); dict> cell_wideports_cache; @@ -441,7 +441,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool if (it.second.count(idx)) sig.append(it.second.at(idx)); else - sig.append(module->addWire(NEW_ID)); + sig.append(module->addWire(NEWER_ID)); } cell->setPort(it.first, sig); @@ -517,7 +517,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool if (sop_mode) { - sopcell = module->addCell(NEW_ID, ID($sop)); + sopcell = module->addCell(NEWER_ID, ID($sop)); sopcell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size()); sopcell->parameters[ID::DEPTH] = 0; sopcell->parameters[ID::TABLE] = RTLIL::Const(); @@ -533,7 +533,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool } else { - RTLIL::Cell *cell = module->addCell(NEW_ID, ID($lut)); + RTLIL::Cell *cell = module->addCell(NEWER_ID, ID($lut)); cell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size()); cell->parameters[ID::LUT] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size()); cell->setPort(ID::A, input_sig); @@ -586,8 +586,8 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool sopmode = (*output == '1'); if (!sopmode) { SigSpec outnet = sopcell->getPort(ID::Y); - SigSpec tempnet = module->addWire(NEW_ID); - module->addNotGate(NEW_ID, tempnet, outnet); + SigSpec tempnet = module->addWire(NEWER_ID); + module->addNotGate(NEWER_ID, tempnet, outnet); sopcell->setPort(ID::Y, tempnet); } } else diff --git a/frontends/json/jsonparse.cc b/frontends/json/jsonparse.cc index 743ac5d9efe..a7244691b85 100644 --- a/frontends/json/jsonparse.cc +++ b/frontends/json/jsonparse.cc @@ -549,7 +549,7 @@ void json_import(Design *design, string &modname, JsonNode *node) if (bitval_node->type == 'N') { int bitidx = bitval_node->data_number; if (signal_bits.count(bitidx) == 0) - signal_bits[bitidx] = module->addWire(NEW_ID); + signal_bits[bitidx] = module->addWire(NEWER_ID); sig.append(signal_bits.at(bitidx)); } else log_error("JSON cells node '%s' connection '%s' has invalid bit value on bit %d.\n", diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index 72ad8b2b725..1e9052b11ba 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -58,7 +58,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector &stack int top = int(stack.size())-1; if (0 <= top-1 && stack[top].type == 0 && stack[top-1].type == '!') { - token_t t = token_t(0, module->NotGate(NEW_ID, stack[top].sig)); + token_t t = token_t(0, module->NotGate(NEWER_ID, stack[top].sig)); stack.pop_back(); stack.pop_back(); stack.push_back(t); @@ -66,7 +66,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector &stack } if (0 <= top-1 && stack[top].type == '\'' && stack[top-1].type == 0) { - token_t t = token_t(0, module->NotGate(NEW_ID, stack[top-1].sig)); + token_t t = token_t(0, module->NotGate(NEWER_ID, stack[top-1].sig)); stack.pop_back(); stack.pop_back(); stack.push_back(t); @@ -81,7 +81,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector &stack } if (0 <= top-2 && stack[top-2].type == 1 && stack[top-1].type == '^' && stack[top].type == 1) { - token_t t = token_t(1, module->XorGate(NEW_ID, stack[top-2].sig, stack[top].sig)); + token_t t = token_t(1, module->XorGate(NEWER_ID, stack[top-2].sig, stack[top].sig)); stack.pop_back(); stack.pop_back(); stack.pop_back(); @@ -97,7 +97,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector &stack } if (0 <= top-1 && stack[top-1].type == 2 && stack[top].type == 2) { - token_t t = token_t(2, module->AndGate(NEW_ID, stack[top-1].sig, stack[top].sig)); + token_t t = token_t(2, module->AndGate(NEWER_ID, stack[top-1].sig, stack[top].sig)); stack.pop_back(); stack.pop_back(); stack.push_back(t); @@ -105,7 +105,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector &stack } if (0 <= top-2 && stack[top-2].type == 2 && (stack[top-1].type == '*' || stack[top-1].type == '&') && stack[top].type == 2) { - token_t t = token_t(2, module->AndGate(NEW_ID, stack[top-2].sig, stack[top].sig)); + token_t t = token_t(2, module->AndGate(NEWER_ID, stack[top-2].sig, stack[top].sig)); stack.pop_back(); stack.pop_back(); stack.pop_back(); @@ -121,7 +121,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector &stack } if (0 <= top-2 && stack[top-2].type == 3 && (stack[top-1].type == '+' || stack[top-1].type == '|') && stack[top].type == 3) { - token_t t = token_t(3, module->OrGate(NEW_ID, stack[top-2].sig, stack[top].sig)); + token_t t = token_t(3, module->OrGate(NEWER_ID, stack[top-2].sig, stack[top].sig)); stack.pop_back(); stack.pop_back(); stack.pop_back(); @@ -183,11 +183,11 @@ static RTLIL::SigSpec create_tristate(RTLIL::Module *module, RTLIL::SigSpec func { RTLIL::SigSpec three_state = parse_func_expr(module, three_state_expr); - RTLIL::Cell *cell = module->addCell(NEW_ID, ID($tribuf)); + RTLIL::Cell *cell = module->addCell(NEWER_ID, ID($tribuf)); cell->setParam(ID::WIDTH, GetSize(func)); cell->setPort(ID::A, func); - cell->setPort(ID::EN, module->NotGate(NEW_ID, three_state)); - cell->setPort(ID::Y, module->addWire(NEW_ID)); + cell->setPort(ID::EN, module->NotGate(NEWER_ID, three_state)); + cell->setPort(ID::Y, module->addWire(NEWER_ID)); return cell->getPort(ID::Y); } @@ -236,11 +236,11 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node) } } - RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_)); + RTLIL::Cell *cell = module->addCell(NEWER_ID, ID($_NOT_)); cell->setPort(ID::A, iq_sig); cell->setPort(ID::Y, iqn_sig); - cell = module->addCell(NEW_ID, ""); + cell = module->addCell(NEWER_ID, ""); cell->setPort(ID::D, data_sig); cell->setPort(ID::Q, iq_sig); cell->setPort(ID::C, clk_sig); @@ -319,7 +319,7 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla } } - RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_)); + RTLIL::Cell *cell = module->addCell(NEWER_ID, ID($_NOT_)); cell->setPort(ID::A, iq_sig); cell->setPort(ID::Y, iqn_sig); @@ -330,9 +330,9 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla if (clear_polarity == true || clear_polarity != enable_polarity) { - RTLIL::Cell *inv = module->addCell(NEW_ID, ID($_NOT_)); + RTLIL::Cell *inv = module->addCell(NEWER_ID, ID($_NOT_)); inv->setPort(ID::A, clear_sig); - inv->setPort(ID::Y, module->addWire(NEW_ID)); + inv->setPort(ID::Y, module->addWire(NEWER_ID)); if (clear_polarity == true) clear_negative = inv->getPort(ID::Y); @@ -340,15 +340,15 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla clear_enable = inv->getPort(ID::Y); } - RTLIL::Cell *data_gate = module->addCell(NEW_ID, ID($_AND_)); + RTLIL::Cell *data_gate = module->addCell(NEWER_ID, ID($_AND_)); data_gate->setPort(ID::A, data_sig); data_gate->setPort(ID::B, clear_negative); - data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID)); + data_gate->setPort(ID::Y, data_sig = module->addWire(NEWER_ID)); - RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? ID($_OR_) : ID($_AND_)); + RTLIL::Cell *enable_gate = module->addCell(NEWER_ID, enable_polarity ? ID($_OR_) : ID($_AND_)); enable_gate->setPort(ID::A, enable_sig); enable_gate->setPort(ID::B, clear_enable); - enable_gate->setPort(ID::Y, enable_sig = module->addWire(NEW_ID)); + enable_gate->setPort(ID::Y, enable_sig = module->addWire(NEWER_ID)); } if (preset_sig.size() == 1) @@ -358,9 +358,9 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla if (preset_polarity == false || preset_polarity != enable_polarity) { - RTLIL::Cell *inv = module->addCell(NEW_ID, ID($_NOT_)); + RTLIL::Cell *inv = module->addCell(NEWER_ID, ID($_NOT_)); inv->setPort(ID::A, preset_sig); - inv->setPort(ID::Y, module->addWire(NEW_ID)); + inv->setPort(ID::Y, module->addWire(NEWER_ID)); if (preset_polarity == false) preset_positive = inv->getPort(ID::Y); @@ -368,18 +368,18 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla preset_enable = inv->getPort(ID::Y); } - RTLIL::Cell *data_gate = module->addCell(NEW_ID, ID($_OR_)); + RTLIL::Cell *data_gate = module->addCell(NEWER_ID, ID($_OR_)); data_gate->setPort(ID::A, data_sig); data_gate->setPort(ID::B, preset_positive); - data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID)); + data_gate->setPort(ID::Y, data_sig = module->addWire(NEWER_ID)); - RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? ID($_OR_) : ID($_AND_)); + RTLIL::Cell *enable_gate = module->addCell(NEWER_ID, enable_polarity ? ID($_OR_) : ID($_AND_)); enable_gate->setPort(ID::A, enable_sig); enable_gate->setPort(ID::B, preset_enable); - enable_gate->setPort(ID::Y, enable_sig = module->addWire(NEW_ID)); + enable_gate->setPort(ID::Y, enable_sig = module->addWire(NEWER_ID)); } - cell = module->addCell(NEW_ID, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N')); + cell = module->addCell(NEWER_ID, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N')); cell->setPort(ID::D, data_sig); cell->setPort(ID::Q, iq_sig); cell->setPort(ID::E, enable_sig); @@ -734,7 +734,7 @@ struct LibertyFrontend : public Frontend { if (wi->port_input) { for (auto wo : module->wires()) if (wo->port_output) { - RTLIL::Cell *spec = module->addCell(NEW_ID, ID($specify2)); + RTLIL::Cell *spec = module->addCell(NEWER_ID, ID($specify2)); spec->setParam(ID::SRC_WIDTH, wi->width); spec->setParam(ID::DST_WIDTH, wo->width); spec->setParam(ID::T_FALL_MAX, 1000); diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 8bb34582ee6..bbd7faca609 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -759,8 +759,8 @@ bool VerificImporter::import_netlist_instance_gates(Instance *inst, RTLIL::IdStr if (inst->GetAsyncCond()->IsGnd()) { module->addDlatch(inst_name, net_map_at(inst->GetControl()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput())); } else { - RTLIL::SigSpec sig_set = module->And(NEW_ID, net_map_at(inst->GetAsyncCond()), net_map_at(inst->GetAsyncVal())); - RTLIL::SigSpec sig_clr = module->And(NEW_ID, net_map_at(inst->GetAsyncCond()), module->Not(NEW_ID, net_map_at(inst->GetAsyncVal()))); + RTLIL::SigSpec sig_set = module->And(NEWER_ID, net_map_at(inst->GetAsyncCond()), net_map_at(inst->GetAsyncVal())); + RTLIL::SigSpec sig_clr = module->And(NEWER_ID, net_map_at(inst->GetAsyncCond()), module->Not(NEWER_ID, net_map_at(inst->GetAsyncVal()))); module->addDlatchsr(inst_name, net_map_at(inst->GetControl()), sig_set, sig_clr, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput())); } return true; @@ -896,8 +896,8 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr if (inst->GetAsyncCond()->IsGnd()) { cell = module->addDlatch(inst_name, net_map_at(inst->GetControl()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput())); } else { - RTLIL::SigSpec sig_set = module->And(NEW_ID, net_map_at(inst->GetAsyncCond()), net_map_at(inst->GetAsyncVal())); - RTLIL::SigSpec sig_clr = module->And(NEW_ID, net_map_at(inst->GetAsyncCond()), module->Not(NEW_ID, net_map_at(inst->GetAsyncVal()))); + RTLIL::SigSpec sig_set = module->And(NEWER_ID, net_map_at(inst->GetAsyncCond()), net_map_at(inst->GetAsyncVal())); + RTLIL::SigSpec sig_clr = module->And(NEWER_ID, net_map_at(inst->GetAsyncCond()), module->Not(NEWER_ID, net_map_at(inst->GetAsyncVal()))); cell = module->addDlatchsr(inst_name, net_map_at(inst->GetControl()), sig_set, sig_clr, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput())); } import_attributes(cell->attributes, inst); @@ -1000,9 +1000,9 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr } if (inst->Type() == OPER_REDUCE_NAND) { - Wire *tmp = module->addWire(NEW_ID); + Wire *tmp = module->addWire(NEWER_ID); cell = module->addReduceAnd(inst_name, IN, tmp, SIGNED); - module->addNot(NEW_ID, tmp, net_map_at(inst->GetOutput())); + module->addNot(NEWER_ID, tmp, net_map_at(inst->GetOutput())); import_attributes(cell->attributes, inst); return true; } @@ -1219,8 +1219,8 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr for (offset = 0; offset < GetSize(sig_acond); offset += width) { for (width = 1; offset+width < GetSize(sig_acond); width++) if (sig_acond[offset] != sig_acond[offset+width]) break; - RTLIL::SigSpec sig_set = module->Mux(NEW_ID, RTLIL::SigSpec(0, width), sig_adata.extract(offset, width), sig_acond[offset]); - RTLIL::SigSpec sig_clr = module->Mux(NEW_ID, RTLIL::SigSpec(0, width), module->Not(NEW_ID, sig_adata.extract(offset, width)), sig_acond[offset]); + RTLIL::SigSpec sig_set = module->Mux(NEWER_ID, RTLIL::SigSpec(0, width), sig_adata.extract(offset, width), sig_acond[offset]); + RTLIL::SigSpec sig_clr = module->Mux(NEWER_ID, RTLIL::SigSpec(0, width), module->Not(NEWER_ID, sig_adata.extract(offset, width)), sig_acond[offset]); cell = module->addDlatchsr(module->uniquify(inst_name), net_map_at(inst->GetControl()), sig_set, sig_clr, sig_d.extract(offset, width), sig_q.extract(offset, width)); import_attributes(cell->attributes, inst); @@ -1374,8 +1374,8 @@ void VerificImporter::merge_past_ffs_clock(pool &candidates, SigBi if (chunk.wire == nullptr || GetSize(sig_d) == 1) continue; - SigSpec sig_q = module->addWire(NEW_ID, GetSize(sig_d)); - RTLIL::Cell *new_ff = module->addDff(NEW_ID, clock, sig_d, sig_q, clock_pol); + SigSpec sig_q = module->addWire(NEWER_ID, GetSize(sig_d)); + RTLIL::Cell *new_ff = module->addDff(NEWER_ID, clock, sig_d, sig_q, clock_pol); if (verific_verbose) log(" merging single-bit past_ffs into new %d-bit ff %s.\n", GetSize(sig_d), log_id(new_ff)); @@ -2470,7 +2470,7 @@ Cell *VerificClocking::addDff(IdString name, SigSpec sig_d, SigSpec sig_q, Const if (s.is_wire()) { s.as_wire()->attributes[ID::init] = init_value; } else { - Wire *w = module->addWire(NEW_ID, GetSize(s)); + Wire *w = module->addWire(NEWER_ID, GetSize(s)); w->attributes[ID::init] = init_value; module->connect(s, w); s = w; @@ -2478,14 +2478,14 @@ Cell *VerificClocking::addDff(IdString name, SigSpec sig_d, SigSpec sig_q, Const }; if (enable_sig != State::S1) - sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig); + sig_d = module->Mux(NEWER_ID, sig_q, sig_d, enable_sig); if (disable_sig != State::S0) { log_assert(GetSize(sig_q) == GetSize(init_value)); if (gclk) { - Wire *pre_d = module->addWire(NEW_ID, GetSize(sig_d)); - Wire *post_q_w = module->addWire(NEW_ID, GetSize(sig_q)); + Wire *pre_d = module->addWire(NEWER_ID, GetSize(sig_d)); + Wire *post_q_w = module->addWire(NEWER_ID, GetSize(sig_q)); Const initval(State::Sx, GetSize(sig_q)); int offset = 0; @@ -2501,8 +2501,8 @@ Cell *VerificClocking::addDff(IdString name, SigSpec sig_d, SigSpec sig_q, Const if (!initval.is_fully_undef()) post_q_w->attributes[ID::init] = initval; - module->addMux(NEW_ID, sig_d, init_value, disable_sig, pre_d); - module->addMux(NEW_ID, post_q_w, init_value, disable_sig, sig_q); + module->addMux(NEWER_ID, sig_d, init_value, disable_sig, pre_d); + module->addMux(NEWER_ID, post_q_w, init_value, disable_sig, sig_q); SigSpec post_q(post_q_w); set_init_attribute(post_q); @@ -2529,7 +2529,7 @@ Cell *VerificClocking::addAdff(IdString name, RTLIL::SigSpec sig_arst, SigSpec s // FIXME: Adffe if (enable_sig != State::S1) - sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig); + sig_d = module->Mux(NEWER_ID, sig_q, sig_d, enable_sig); return module->addAdff(name, clock_sig, sig_arst, sig_d, sig_q, arst_value, posedge); } @@ -2541,7 +2541,7 @@ Cell *VerificClocking::addDffsr(IdString name, RTLIL::SigSpec sig_set, RTLIL::Si // FIXME: Dffsre if (enable_sig != State::S1) - sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig); + sig_d = module->Mux(NEWER_ID, sig_q, sig_d, enable_sig); return module->addDffsr(name, clock_sig, sig_set, sig_clr, sig_d, sig_q, posedge); } @@ -2552,11 +2552,11 @@ Cell *VerificClocking::addAldff(IdString name, RTLIL::SigSpec sig_aload, RTLIL:: // FIXME: Aldffe if (enable_sig != State::S1) - sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig); + sig_d = module->Mux(NEWER_ID, sig_q, sig_d, enable_sig); if (gclk) { - Wire *pre_d = module->addWire(NEW_ID, GetSize(sig_d)); - Wire *post_q = module->addWire(NEW_ID, GetSize(sig_q)); + Wire *pre_d = module->addWire(NEWER_ID, GetSize(sig_d)); + Wire *post_q = module->addWire(NEWER_ID, GetSize(sig_q)); Const initval(State::Sx, GetSize(sig_q)); int offset = 0; @@ -2572,8 +2572,8 @@ Cell *VerificClocking::addAldff(IdString name, RTLIL::SigSpec sig_aload, RTLIL:: if (!initval.is_fully_undef()) post_q->attributes[ID::init] = initval; - module->addMux(NEW_ID, sig_d, sig_adata, sig_aload, pre_d); - module->addMux(NEW_ID, post_q, sig_adata, sig_aload, sig_q); + module->addMux(NEWER_ID, sig_d, sig_adata, sig_aload, pre_d); + module->addMux(NEWER_ID, post_q, sig_adata, sig_aload, sig_q); return module->addFf(name, pre_d, post_q); } diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index cc5f07004a8..405e37670c7 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -166,7 +166,7 @@ struct SvaFsm if (disable_sig == State::S0) disable_sig = sig; else - disable_sig = module->Or(NEW_ID, disable_sig, sig); + disable_sig = module->Or(NEWER_ID, disable_sig, sig); } void popDisable() @@ -187,7 +187,7 @@ struct SvaFsm if (throughout_sig == State::S1) throughout_sig = sig; else - throughout_sig = module->And(NEW_ID, throughout_sig, sig); + throughout_sig = module->And(NEWER_ID, throughout_sig, sig); } void popThroughout() @@ -232,7 +232,7 @@ struct SvaFsm if (throughout_sig != State::S1) { if (ctrl != State::S1) - ctrl = module->And(NEW_ID, throughout_sig, ctrl); + ctrl = module->And(NEWER_ID, throughout_sig, ctrl); else ctrl = throughout_sig; } @@ -254,7 +254,7 @@ struct SvaFsm if (throughout_sig != State::S1) { if (ctrl != State::S1) - ctrl = module->And(NEW_ID, throughout_sig, ctrl); + ctrl = module->And(NEWER_ID, throughout_sig, ctrl); else ctrl = throughout_sig; } @@ -287,19 +287,19 @@ struct SvaFsm SigBit not_disable = State::S1; if (disable_sig != State::S0) - not_disable = module->Not(NEW_ID, disable_sig); + not_disable = module->Not(NEWER_ID, disable_sig); for (int i = 0; i < GetSize(nodes); i++) { - Wire *w = module->addWire(NEW_ID); + Wire *w = module->addWire(NEWER_ID); state_wire[i] = w; state_sig[i] = w; if (i == startNode) - state_sig[i] = module->Or(NEW_ID, state_sig[i], trigger_sig); + state_sig[i] = module->Or(NEWER_ID, state_sig[i], trigger_sig); if (disable_sig != State::S0) - state_sig[i] = module->And(NEW_ID, state_sig[i], not_disable); + state_sig[i] = module->And(NEWER_ID, state_sig[i], not_disable); } } @@ -327,9 +327,9 @@ struct SvaFsm SigBit ctrl = state_sig[node]; if (it.second != State::S1) - ctrl = module->And(NEW_ID, ctrl, it.second); + ctrl = module->And(NEWER_ID, ctrl, it.second); - state_sig[target] = module->Or(NEW_ID, state_sig[target], ctrl); + state_sig[target] = module->Or(NEWER_ID, state_sig[target], ctrl); } } } @@ -342,7 +342,7 @@ struct SvaFsm for (int i = 0; i < GetSize(nodes); i++) { for (auto &it : nodes[i].edges) - activate_sig[it.first].append(module->And(NEW_ID, state_sig[i], it.second)); + activate_sig[it.first].append(module->And(NEWER_ID, state_sig[i], it.second)); } for (int i = 0; i < GetSize(nodes); i++) { @@ -351,7 +351,7 @@ struct SvaFsm else if (GetSize(activate_sig[i]) == 1) next_state_sig[i] = activate_sig[i]; else - next_state_sig[i] = module->ReduceOr(NEW_ID, activate_sig[i]); + next_state_sig[i] = module->ReduceOr(NEWER_ID, activate_sig[i]); } } @@ -360,7 +360,7 @@ struct SvaFsm for (int i = 0; i < GetSize(nodes); i++) { if (next_state_sig[i] != State::S0) { - clocking.addDff(NEW_ID, next_state_sig[i], state_wire[i], State::S0); + clocking.addDff(NEWER_ID, next_state_sig[i], state_wire[i], State::S0); } else { module->connect(state_wire[i], State::S0); } @@ -626,9 +626,9 @@ struct SvaFsm if (sig_b == State::S1) cond_eq_cache[key] = sig_a; else if (sig_b == State::S0) - cond_eq_cache[key] = module->Not(NEW_ID, sig_a); + cond_eq_cache[key] = module->Not(NEWER_ID, sig_a); else - cond_eq_cache[key] = module->Eq(NEW_ID, sig_a, sig_b); + cond_eq_cache[key] = module->Eq(NEWER_ID, sig_a, sig_b); if (verific_verbose >= 2) { log(" Cond: %s := %s == %s\n", log_signal(cond_eq_cache[key]), @@ -665,11 +665,11 @@ struct SvaFsm for (auto &it : dnodes) { SvaDFsmNode &dnode = it.second; - dnode.ffoutwire = module->addWire(NEW_ID); + dnode.ffoutwire = module->addWire(NEWER_ID); dnode.statesig = dnode.ffoutwire; if (it.first == vector{startNode}) - dnode.statesig = module->Or(NEW_ID, dnode.statesig, trigger_sig); + dnode.statesig = module->Or(NEWER_ID, dnode.statesig, trigger_sig); } for (auto &it : dnodes) @@ -708,10 +708,10 @@ struct SvaFsm module->connect(dnode.ffoutwire, State::S0); } else if (GetSize(dnode.nextstate) == 1) { - clocking.addDff(NEW_ID, dnode.nextstate, dnode.ffoutwire, State::S0); + clocking.addDff(NEWER_ID, dnode.nextstate, dnode.ffoutwire, State::S0); } else { - SigSpec nextstate = module->ReduceOr(NEW_ID, dnode.nextstate); - clocking.addDff(NEW_ID, nextstate, dnode.ffoutwire, State::S0); + SigSpec nextstate = module->ReduceOr(NEWER_ID, dnode.nextstate); + clocking.addDff(NEWER_ID, nextstate, dnode.ffoutwire, State::S0); } } @@ -722,7 +722,7 @@ struct SvaFsm else if (GetSize(accept_sig) == 1) final_accept_sig = accept_sig; else - final_accept_sig = module->ReduceOr(NEW_ID, accept_sig); + final_accept_sig = module->ReduceOr(NEWER_ID, accept_sig); *accept_p = final_accept_sig; } @@ -733,7 +733,7 @@ struct SvaFsm else if (GetSize(reject_sig) == 1) final_reject_sig = reject_sig; else - final_reject_sig = module->ReduceOr(NEW_ID, reject_sig); + final_reject_sig = module->ReduceOr(NEWER_ID, reject_sig); *reject_p = final_reject_sig; } } @@ -1135,14 +1135,14 @@ struct VerificSvaImporter return parse_expression(inst->GetInput()); if (inst->Type() == PRIM_SVA_NOT) - return module->Not(NEW_ID, parse_expression(inst->GetInput())); + return module->Not(NEWER_ID, parse_expression(inst->GetInput())); if (inst->Type() == PRIM_SVA_SEQ_OR || inst->Type() == PRIM_SVA_OR) - return module->Or(NEW_ID, parse_expression(inst->GetInput1()), parse_expression(inst->GetInput2())); + return module->Or(NEWER_ID, parse_expression(inst->GetInput1()), parse_expression(inst->GetInput2())); if (inst->Type() == PRIM_SVA_SEQ_AND || inst->Type() == PRIM_SVA_AND || inst->Type() == PRIM_SVA_INTERSECT || inst->Type() == PRIM_SVA_WITHIN || inst->Type() == PRIM_SVA_THROUGHOUT || inst->Type() == PRIM_SVA_SEQ_CONCAT) - return module->And(NEW_ID, parse_expression(inst->GetInput1()), parse_expression(inst->GetInput2())); + return module->And(NEWER_ID, parse_expression(inst->GetInput1()), parse_expression(inst->GetInput2())); log_abort(); } @@ -1364,7 +1364,7 @@ struct VerificSvaImporter int node = fsm.createNode(start_node); SigBit cond = parse_expression(body_net); - SigBit not_cond = module->Not(NEW_ID, cond); + SigBit not_cond = module->Not(NEWER_ID, cond); for (int i = 0; i < sva_low; i++) { @@ -1526,7 +1526,7 @@ struct VerificSvaImporter if (clocking.cond_net != nullptr) { trig = importer->net_map_at(clocking.cond_net); if (!clocking.cond_pol) - trig = module->Not(NEW_ID, trig); + trig = module->Not(NEWER_ID, trig); } else { trig = State::S1; } @@ -1594,21 +1594,21 @@ struct VerificSvaImporter if (clocking.cond_net != nullptr) { trig = importer->net_map_at(clocking.cond_net); if (!clocking.cond_pol) - trig = module->Not(NEW_ID, trig); + trig = module->Not(NEWER_ID, trig); } if (inst == nullptr) { if (trig != State::S1) { if (accept_p != nullptr) - *accept_p = module->And(NEW_ID, trig, importer->net_map_at(net)); + *accept_p = module->And(NEWER_ID, trig, importer->net_map_at(net)); if (reject_p != nullptr) - *reject_p = module->And(NEW_ID, trig, module->Not(NEW_ID, importer->net_map_at(net))); + *reject_p = module->And(NEWER_ID, trig, module->Not(NEWER_ID, importer->net_map_at(net))); } else { if (accept_p != nullptr) *accept_p = importer->net_map_at(net); if (reject_p != nullptr) - *reject_p = module->Not(NEW_ID, importer->net_map_at(net)); + *reject_p = module->Not(NEWER_ID, importer->net_map_at(net)); } } else @@ -1652,7 +1652,7 @@ struct VerificSvaImporter } SigBit until_sig = until_net ? parse_expression(until_net) : RTLIL::S0; - SigBit not_until_sig = module->Not(NEW_ID, until_sig); + SigBit not_until_sig = module->Not(NEWER_ID, until_sig); antecedent_fsm.createEdge(node, node, not_until_sig); antecedent_fsm.createLink(node, antecedent_fsm.acceptNode, until_with ? State::S1 : not_until_sig); @@ -1732,7 +1732,7 @@ struct VerificSvaImporter } } - RTLIL::IdString root_name = module->uniquify(importer->mode_names || is_user_declared ? RTLIL::escape_id(root->Name()) : NEW_ID); + RTLIL::IdString root_name = module->uniquify(importer->mode_names || is_user_declared ? RTLIL::escape_id(root->Name()) : NEWER_ID); // parse SVA sequence into trigger signal @@ -1745,7 +1745,7 @@ struct VerificSvaImporter parser_error(stringf("Failed to parse SVA clocking"), root); if (mode_assert || mode_assume) { - reject_bit = module->Not(NEW_ID, parse_expression(root->GetInput())); + reject_bit = module->Not(NEWER_ID, parse_expression(root->GetInput())); } else { accept_bit = parse_expression(root->GetInput()); } @@ -1768,16 +1768,16 @@ struct VerificSvaImporter sig_a_q = sig_a; sig_en_q = sig_en; } else { - sig_a_q = module->addWire(NEW_ID); - sig_en_q = module->addWire(NEW_ID); - clocking.addDff(NEW_ID, sig_a, sig_a_q, State::S0); - clocking.addDff(NEW_ID, sig_en, sig_en_q, State::S0); + sig_a_q = module->addWire(NEWER_ID); + sig_en_q = module->addWire(NEWER_ID); + clocking.addDff(NEWER_ID, sig_a, sig_a_q, State::S0); + clocking.addDff(NEWER_ID, sig_en, sig_en_q, State::S0); } // accept in disable case if (clocking.disable_sig != State::S0) - sig_a_q = module->Or(NEW_ID, sig_a_q, clocking.disable_sig); + sig_a_q = module->Or(NEWER_ID, sig_a_q, clocking.disable_sig); // generate fair/live cell @@ -1806,8 +1806,8 @@ struct VerificSvaImporter } else { - SigBit sig_a = module->Not(NEW_ID, reject_bit); - SigBit sig_en = module->Or(NEW_ID, accept_bit, reject_bit); + SigBit sig_a = module->Not(NEWER_ID, reject_bit); + SigBit sig_en = module->Or(NEWER_ID, accept_bit, reject_bit); // add final FF stage @@ -1817,10 +1817,10 @@ struct VerificSvaImporter sig_a_q = sig_a; sig_en_q = sig_en; } else { - sig_a_q = module->addWire(NEW_ID); - sig_en_q = module->addWire(NEW_ID); - clocking.addDff(NEW_ID, sig_a, sig_a_q, State::S0); - clocking.addDff(NEW_ID, sig_en, sig_en_q, State::S0); + sig_a_q = module->addWire(NEWER_ID); + sig_en_q = module->addWire(NEWER_ID); + clocking.addDff(NEWER_ID, sig_a, sig_a_q, State::S0); + clocking.addDff(NEWER_ID, sig_en, sig_en_q, State::S0); } // generate assert/assume/cover cell diff --git a/guidelines/GettingStarted b/guidelines/GettingStarted index 17fe325233d..a064ec7c429 100644 --- a/guidelines/GettingStarted +++ b/guidelines/GettingStarted @@ -98,8 +98,8 @@ single signal bit can have multiple valid names. The SigMap object can be used to map SigSpecs or SigBits to unique SigSpecs and SigBits that consistently only use one wire from such a group of connected wires. For example: - SigBit a = module->addWire(NEW_ID); - SigBit b = module->addWire(NEW_ID); + SigBit a = module->addWire(NEWER_ID); + SigBit b = module->addWire(NEWER_ID); module->connect(a, b); log("%d\n", a == b); // will print 0 diff --git a/kernel/ff.cc b/kernel/ff.cc index a72e6a65c5a..0cfdf1dd9f5 100644 --- a/kernel/ff.cc +++ b/kernel/ff.cc @@ -263,7 +263,7 @@ FfData::FfData(FfInitVals *initvals, Cell *cell_) : FfData(cell_->module, initva } FfData FfData::slice(const std::vector &bits) { - FfData res(module, initvals, NEW_ID); + FfData res(module, initvals, NEWER_ID); res.sig_clk = sig_clk; res.sig_ce = sig_ce; res.sig_aload = sig_aload; @@ -417,21 +417,21 @@ void FfData::aload_to_sr() { pol_clr = false; pol_set = true; if (pol_aload) { - sig_clr = module->Mux(NEW_ID, Const(State::S1, width), sig_ad, sig_aload); - sig_set = module->Mux(NEW_ID, Const(State::S0, width), sig_ad, sig_aload); + sig_clr = module->Mux(NEWER_ID, Const(State::S1, width), sig_ad, sig_aload); + sig_set = module->Mux(NEWER_ID, Const(State::S0, width), sig_ad, sig_aload); } else { - sig_clr = module->Mux(NEW_ID, sig_ad, Const(State::S1, width), sig_aload); - sig_set = module->Mux(NEW_ID, sig_ad, Const(State::S0, width), sig_aload); + sig_clr = module->Mux(NEWER_ID, sig_ad, Const(State::S1, width), sig_aload); + sig_set = module->Mux(NEWER_ID, sig_ad, Const(State::S0, width), sig_aload); } } else { pol_clr = pol_aload; pol_set = pol_aload; if (pol_aload) { - sig_clr = module->AndnotGate(NEW_ID, sig_aload, sig_ad); - sig_set = module->AndGate(NEW_ID, sig_aload, sig_ad); + sig_clr = module->AndnotGate(NEWER_ID, sig_aload, sig_ad); + sig_set = module->AndGate(NEWER_ID, sig_aload, sig_ad); } else { - sig_clr = module->OrGate(NEW_ID, sig_aload, sig_ad); - sig_set = module->OrnotGate(NEW_ID, sig_aload, sig_ad); + sig_clr = module->OrGate(NEWER_ID, sig_aload, sig_ad); + sig_set = module->OrnotGate(NEWER_ID, sig_aload, sig_ad); } } } @@ -444,31 +444,31 @@ void FfData::convert_ce_over_srst(bool val) { if (!is_fine) { if (pol_ce) { if (pol_srst) { - sig_ce = module->Or(NEW_ID, sig_ce, sig_srst); + sig_ce = module->Or(NEWER_ID, sig_ce, sig_srst); } else { - SigSpec tmp = module->Not(NEW_ID, sig_srst); - sig_ce = module->Or(NEW_ID, sig_ce, tmp); + SigSpec tmp = module->Not(NEWER_ID, sig_srst); + sig_ce = module->Or(NEWER_ID, sig_ce, tmp); } } else { if (pol_srst) { - SigSpec tmp = module->Not(NEW_ID, sig_srst); - sig_ce = module->And(NEW_ID, sig_ce, tmp); + SigSpec tmp = module->Not(NEWER_ID, sig_srst); + sig_ce = module->And(NEWER_ID, sig_ce, tmp); } else { - sig_ce = module->And(NEW_ID, sig_ce, sig_srst); + sig_ce = module->And(NEWER_ID, sig_ce, sig_srst); } } } else { if (pol_ce) { if (pol_srst) { - sig_ce = module->OrGate(NEW_ID, sig_ce, sig_srst); + sig_ce = module->OrGate(NEWER_ID, sig_ce, sig_srst); } else { - sig_ce = module->OrnotGate(NEW_ID, sig_ce, sig_srst); + sig_ce = module->OrnotGate(NEWER_ID, sig_ce, sig_srst); } } else { if (pol_srst) { - sig_ce = module->AndnotGate(NEW_ID, sig_ce, sig_srst); + sig_ce = module->AndnotGate(NEWER_ID, sig_ce, sig_srst); } else { - sig_ce = module->AndGate(NEW_ID, sig_ce, sig_srst); + sig_ce = module->AndGate(NEWER_ID, sig_ce, sig_srst); } } } @@ -477,31 +477,31 @@ void FfData::convert_ce_over_srst(bool val) { if (!is_fine) { if (pol_srst) { if (pol_ce) { - sig_srst = cell->module->And(NEW_ID, sig_srst, sig_ce); + sig_srst = cell->module->And(NEWER_ID, sig_srst, sig_ce); } else { - SigSpec tmp = module->Not(NEW_ID, sig_ce); - sig_srst = cell->module->And(NEW_ID, sig_srst, tmp); + SigSpec tmp = module->Not(NEWER_ID, sig_ce); + sig_srst = cell->module->And(NEWER_ID, sig_srst, tmp); } } else { if (pol_ce) { - SigSpec tmp = module->Not(NEW_ID, sig_ce); - sig_srst = cell->module->Or(NEW_ID, sig_srst, tmp); + SigSpec tmp = module->Not(NEWER_ID, sig_ce); + sig_srst = cell->module->Or(NEWER_ID, sig_srst, tmp); } else { - sig_srst = cell->module->Or(NEW_ID, sig_srst, sig_ce); + sig_srst = cell->module->Or(NEWER_ID, sig_srst, sig_ce); } } } else { if (pol_srst) { if (pol_ce) { - sig_srst = cell->module->AndGate(NEW_ID, sig_srst, sig_ce); + sig_srst = cell->module->AndGate(NEWER_ID, sig_srst, sig_ce); } else { - sig_srst = cell->module->AndnotGate(NEW_ID, sig_srst, sig_ce); + sig_srst = cell->module->AndnotGate(NEWER_ID, sig_srst, sig_ce); } } else { if (pol_ce) { - sig_srst = cell->module->OrnotGate(NEW_ID, sig_srst, sig_ce); + sig_srst = cell->module->OrnotGate(NEWER_ID, sig_srst, sig_ce); } else { - sig_srst = cell->module->OrGate(NEW_ID, sig_srst, sig_ce); + sig_srst = cell->module->OrGate(NEWER_ID, sig_srst, sig_ce); } } } @@ -518,14 +518,14 @@ void FfData::unmap_ce() { if (!is_fine) { if (pol_ce) - sig_d = module->Mux(NEW_ID, sig_q, sig_d, sig_ce); + sig_d = module->Mux(NEWER_ID, sig_q, sig_d, sig_ce); else - sig_d = module->Mux(NEW_ID, sig_d, sig_q, sig_ce); + sig_d = module->Mux(NEWER_ID, sig_d, sig_q, sig_ce); } else { if (pol_ce) - sig_d = module->MuxGate(NEW_ID, sig_q, sig_d, sig_ce); + sig_d = module->MuxGate(NEWER_ID, sig_q, sig_d, sig_ce); else - sig_d = module->MuxGate(NEW_ID, sig_d, sig_q, sig_ce); + sig_d = module->MuxGate(NEWER_ID, sig_d, sig_q, sig_ce); } has_ce = false; } @@ -538,14 +538,14 @@ void FfData::unmap_srst() { if (!is_fine) { if (pol_srst) - sig_d = module->Mux(NEW_ID, sig_d, val_srst, sig_srst); + sig_d = module->Mux(NEWER_ID, sig_d, val_srst, sig_srst); else - sig_d = module->Mux(NEW_ID, val_srst, sig_d, sig_srst); + sig_d = module->Mux(NEWER_ID, val_srst, sig_d, sig_srst); } else { if (pol_srst) - sig_d = module->MuxGate(NEW_ID, sig_d, val_srst[0], sig_srst); + sig_d = module->MuxGate(NEWER_ID, sig_d, val_srst[0], sig_srst); else - sig_d = module->MuxGate(NEW_ID, val_srst[0], sig_d, sig_srst); + sig_d = module->MuxGate(NEWER_ID, val_srst[0], sig_d, sig_srst); } has_srst = false; } @@ -718,7 +718,7 @@ void FfData::flip_bits(const pool &bits) { flip_rst_bits(bits); - Wire *new_q = module->addWire(NEW_ID, width); + Wire *new_q = module->addWire(NEWER_ID, width); if (has_sr && cell) { log_warning("Flipping D/Q/init and inserting priority fixup to legalize %s.%s [%s].\n", log_id(module->name), log_id(cell->name), log_id(cell->type)); @@ -730,15 +730,15 @@ void FfData::flip_bits(const pool &bits) { SigSpec new_sig_clr; if (pol_set) { if (pol_clr) { - new_sig_clr = module->AndnotGate(NEW_ID, sig_set, sig_clr); + new_sig_clr = module->AndnotGate(NEWER_ID, sig_set, sig_clr); } else { - new_sig_clr = module->AndGate(NEW_ID, sig_set, sig_clr); + new_sig_clr = module->AndGate(NEWER_ID, sig_set, sig_clr); } } else { if (pol_clr) { - new_sig_clr = module->OrGate(NEW_ID, sig_set, sig_clr); + new_sig_clr = module->OrGate(NEWER_ID, sig_set, sig_clr); } else { - new_sig_clr = module->OrnotGate(NEW_ID, sig_set, sig_clr); + new_sig_clr = module->OrnotGate(NEWER_ID, sig_set, sig_clr); } } pol_set = pol_clr; @@ -747,10 +747,10 @@ void FfData::flip_bits(const pool &bits) { sig_clr = new_sig_clr; } if (has_clk || has_gclk) - sig_d = module->NotGate(NEW_ID, sig_d); + sig_d = module->NotGate(NEWER_ID, sig_d); if (has_aload) - sig_ad = module->NotGate(NEW_ID, sig_ad); - module->addNotGate(NEW_ID, new_q, sig_q); + sig_ad = module->NotGate(NEWER_ID, sig_ad); + module->addNotGate(NEWER_ID, new_q, sig_q); } else { @@ -758,17 +758,17 @@ void FfData::flip_bits(const pool &bits) { SigSpec not_clr; if (!pol_clr) { not_clr = sig_clr; - sig_clr = module->Not(NEW_ID, sig_clr); + sig_clr = module->Not(NEWER_ID, sig_clr); pol_clr = true; } else { - not_clr = module->Not(NEW_ID, sig_clr); + not_clr = module->Not(NEWER_ID, sig_clr); } if (!pol_set) { - sig_set = module->Not(NEW_ID, sig_set); + sig_set = module->Not(NEWER_ID, sig_set); pol_set = true; } - SigSpec masked_set = module->And(NEW_ID, sig_set, not_clr); + SigSpec masked_set = module->And(NEWER_ID, sig_set, not_clr); for (auto bit: bits) { sig_set[bit] = sig_clr[bit]; sig_clr[bit] = masked_set[bit]; @@ -780,10 +780,10 @@ void FfData::flip_bits(const pool &bits) { mask.set(bit, State::S1); if (has_clk || has_gclk) - sig_d = module->Xor(NEW_ID, sig_d, mask); + sig_d = module->Xor(NEWER_ID, sig_d, mask); if (has_aload) - sig_ad = module->Xor(NEW_ID, sig_ad, mask); - module->addXor(NEW_ID, new_q, mask, sig_q); + sig_ad = module->Xor(NEWER_ID, sig_ad, mask); + module->addXor(NEWER_ID, new_q, mask, sig_q); } sig_q = new_q; diff --git a/kernel/ffmerge.cc b/kernel/ffmerge.cc index 632cba05cfc..9e82b20fbff 100644 --- a/kernel/ffmerge.cc +++ b/kernel/ffmerge.cc @@ -29,7 +29,7 @@ bool FfMergeHelper::is_output_unused(RTLIL::SigSpec sig) { } bool FfMergeHelper::find_output_ff(RTLIL::SigSpec sig, FfData &ff, pool> &bits) { - ff = FfData(module, initvals, NEW_ID); + ff = FfData(module, initvals, NEWER_ID); sigmap->apply(sig); bool found = false; @@ -157,7 +157,7 @@ bool FfMergeHelper::find_output_ff(RTLIL::SigSpec sig, FfData &ff, pool> &bits) { - ff = FfData(module, initvals, NEW_ID); + ff = FfData(module, initvals, NEWER_ID); sigmap->apply(sig); bool found = false; diff --git a/kernel/mem.cc b/kernel/mem.cc index 02d12dea439..f34c0e5551e 100644 --- a/kernel/mem.cc +++ b/kernel/mem.cc @@ -122,7 +122,7 @@ void Mem::emit() { } if (!cell) { if (memid.empty()) - memid = NEW_ID; + memid = NEWER_ID; cell = module->addCell(memid, ID($mem_v2)); } cell->type = ID($mem_v2); @@ -291,7 +291,7 @@ void Mem::emit() { } if (!mem) { if (memid.empty()) - memid = NEW_ID; + memid = NEWER_ID; mem = new RTLIL::Memory; mem->name = memid; module->memories[memid] = mem; @@ -302,7 +302,7 @@ void Mem::emit() { mem->attributes = attributes; for (auto &port : rd_ports) { if (!port.cell) - port.cell = module->addCell(NEW_ID, ID($memrd_v2)); + port.cell = module->addCell(NEWER_ID, ID($memrd_v2)); port.cell->type = ID($memrd_v2); port.cell->attributes = port.attributes; port.cell->parameters[ID::MEMID] = memid.str(); @@ -327,7 +327,7 @@ void Mem::emit() { int idx = 0; for (auto &port : wr_ports) { if (!port.cell) - port.cell = module->addCell(NEW_ID, ID($memwr_v2)); + port.cell = module->addCell(NEWER_ID, ID($memwr_v2)); port.cell->type = ID($memwr_v2); port.cell->attributes = port.attributes; if (port.cell->parameters.count(ID::PRIORITY)) @@ -348,7 +348,7 @@ void Mem::emit() { for (auto &init : inits) { bool v2 = !init.en.is_fully_ones(); if (!init.cell) - init.cell = module->addCell(NEW_ID, v2 ? ID($meminit_v2) : ID($meminit)); + init.cell = module->addCell(NEWER_ID, v2 ? ID($meminit_v2) : ID($meminit)); else init.cell->type = v2 ? ID($meminit_v2) : ID($meminit); init.cell->attributes = init.attributes; @@ -1127,7 +1127,7 @@ void Mem::emulate_priority(int idx1, int idx2, FfInitVals *initvals) addr1 = port1.sub_addr(sub); else addr2 = port2.sub_addr(sub); - SigSpec addr_eq = module->Eq(NEW_ID, addr1, addr2); + SigSpec addr_eq = module->Eq(NEWER_ID, addr1, addr2); int ewidth = width << min_wide_log2; int sub1 = wide1 ? sub : 0; int sub2 = wide1 ? 0 : sub; @@ -1139,9 +1139,9 @@ void Mem::emulate_priority(int idx1, int idx2, FfInitVals *initvals) if (cache.count(key)) { en1 = cache[key]; } else { - SigBit active2 = module->And(NEW_ID, addr_eq, en2); - SigBit nactive2 = module->Not(NEW_ID, active2); - en1 = cache[key] = module->And(NEW_ID, en1, nactive2); + SigBit active2 = module->And(NEWER_ID, addr_eq, en2); + SigBit nactive2 = module->Not(NEWER_ID, active2); + en1 = cache[key] = module->And(NEWER_ID, en1, nactive2); } } } @@ -1165,8 +1165,8 @@ void Mem::emulate_transparency(int widx, int ridx, FfInitVals *initvals) { // The write data FF doesn't need full reset/init behavior, as it'll be masked by // the mux whenever this would be relevant. It does, however, need to have the same // clock enable signal as the read port. - SigSpec wdata_q = module->addWire(NEW_ID, GetSize(wport.data)); - module->addDffe(NEW_ID, rport.clk, rport.en, wport.data, wdata_q, rport.clk_polarity, true); + SigSpec wdata_q = module->addWire(NEWER_ID, GetSize(wport.data)); + module->addDffe(NEWER_ID, rport.clk, rport.en, wport.data, wdata_q, rport.clk_polarity, true); for (int sub = 0; sub < (1 << max_wide_log2); sub += (1 << min_wide_log2)) { SigSpec raddr = rport.addr; SigSpec waddr = wport.addr; @@ -1177,26 +1177,26 @@ void Mem::emulate_transparency(int widx, int ridx, FfInitVals *initvals) { raddr = rport.sub_addr(sub); SigSpec addr_eq; if (raddr != waddr) - addr_eq = module->Eq(NEW_ID, raddr, waddr); + addr_eq = module->Eq(NEWER_ID, raddr, waddr); int pos = 0; int ewidth = width << min_wide_log2; int wsub = wide_write ? sub : 0; int rsub = wide_write ? 0 : sub; - SigSpec rdata_a = module->addWire(NEW_ID, ewidth); + SigSpec rdata_a = module->addWire(NEWER_ID, ewidth); while (pos < ewidth) { int epos = pos; while (epos < ewidth && wport.en[epos + wsub * width] == wport.en[pos + wsub * width]) epos++; SigSpec cond; if (raddr != waddr) - cond = module->And(NEW_ID, wport.en[pos + wsub * width], addr_eq); + cond = module->And(NEWER_ID, wport.en[pos + wsub * width], addr_eq); else cond = wport.en[pos + wsub * width]; - SigSpec cond_q = module->addWire(NEW_ID); + SigSpec cond_q = module->addWire(NEWER_ID); // The FF for storing the bypass enable signal must be carefully // constructed to preserve the overall init/reset/enable behavior // of the whole port. - FfData ff(module, initvals, NEW_ID); + FfData ff(module, initvals, NEWER_ID); ff.width = 1; ff.sig_q = cond_q; ff.sig_d = cond; @@ -1230,7 +1230,7 @@ void Mem::emulate_transparency(int widx, int ridx, FfInitVals *initvals) { SigSpec cur = rdata_a.extract(pos, epos-pos); SigSpec other = wdata_q.extract(pos + wsub * width, epos-pos); SigSpec dest = rport.data.extract(pos + rsub * width, epos-pos); - module->addMux(NEW_ID, cur, other, cond_q, dest); + module->addMux(NEWER_ID, cur, other, cond_q, dest); pos = epos; } rport.data.replace(rsub * width, rdata_a); @@ -1376,8 +1376,8 @@ void Mem::widen_wr_port(int idx, int wide_log2) { } else { // May or may not write to this subword. new_data.append(port.data); - SigSpec addr_eq = module->Eq(NEW_ID, addr_lo, cur_addr_lo); - SigSpec en = module->Mux(NEW_ID, Const(State::S0, GetSize(port.data)), port.en, addr_eq); + SigSpec addr_eq = module->Eq(NEWER_ID, addr_lo, cur_addr_lo); + SigSpec en = module->Mux(NEWER_ID, Const(State::S0, GetSize(port.data)), port.en, addr_eq); new_en.append(en); } } @@ -1392,11 +1392,11 @@ void Mem::emulate_rden(int idx, FfInitVals *initvals) { auto &port = rd_ports[idx]; log_assert(port.clk_enable); emulate_rd_ce_over_srst(idx); - Wire *new_data = module->addWire(NEW_ID, GetSize(port.data)); - Wire *prev_data = module->addWire(NEW_ID, GetSize(port.data)); - Wire *sel = module->addWire(NEW_ID); - FfData ff_sel(module, initvals, NEW_ID); - FfData ff_data(module, initvals, NEW_ID); + Wire *new_data = module->addWire(NEWER_ID, GetSize(port.data)); + Wire *prev_data = module->addWire(NEWER_ID, GetSize(port.data)); + Wire *sel = module->addWire(NEWER_ID); + FfData ff_sel(module, initvals, NEWER_ID); + FfData ff_data(module, initvals, NEWER_ID); ff_sel.width = 1; ff_sel.has_clk = true; ff_sel.sig_clk = port.clk; @@ -1444,7 +1444,7 @@ void Mem::emulate_rden(int idx, FfInitVals *initvals) { } ff_sel.emit(); ff_data.emit(); - module->addMux(NEW_ID, prev_data, new_data, sel, port.data); + module->addMux(NEWER_ID, prev_data, new_data, sel, port.data); port.data = new_data; port.en = State::S1; } @@ -1452,9 +1452,9 @@ void Mem::emulate_rden(int idx, FfInitVals *initvals) { void Mem::emulate_reset(int idx, bool emu_init, bool emu_arst, bool emu_srst, FfInitVals *initvals) { auto &port = rd_ports[idx]; if (emu_init && !port.init_value.is_fully_undef()) { - Wire *sel = module->addWire(NEW_ID); - FfData ff_sel(module, initvals, NEW_ID); - Wire *new_data = module->addWire(NEW_ID, GetSize(port.data)); + Wire *sel = module->addWire(NEWER_ID); + FfData ff_sel(module, initvals, NEWER_ID); + Wire *new_data = module->addWire(NEWER_ID, GetSize(port.data)); ff_sel.width = 1; ff_sel.has_clk = true; ff_sel.sig_clk = port.clk; @@ -1493,14 +1493,14 @@ void Mem::emulate_reset(int idx, bool emu_init, bool emu_arst, bool emu_srst, Ff } } ff_sel.emit(); - module->addMux(NEW_ID, port.init_value, new_data, sel, port.data); + module->addMux(NEWER_ID, port.init_value, new_data, sel, port.data); port.data = new_data; port.init_value = Const(State::Sx, GetSize(port.data)); } if (emu_arst && port.arst != State::S0) { - Wire *sel = module->addWire(NEW_ID); - FfData ff_sel(module, initvals, NEW_ID); - Wire *new_data = module->addWire(NEW_ID, GetSize(port.data)); + Wire *sel = module->addWire(NEWER_ID); + FfData ff_sel(module, initvals, NEWER_ID); + Wire *new_data = module->addWire(NEWER_ID, GetSize(port.data)); ff_sel.width = 1; ff_sel.has_clk = true; ff_sel.sig_clk = port.clk; @@ -1533,14 +1533,14 @@ void Mem::emulate_reset(int idx, bool emu_init, bool emu_arst, bool emu_srst, Ff } } ff_sel.emit(); - module->addMux(NEW_ID, port.arst_value, new_data, sel, port.data); + module->addMux(NEWER_ID, port.arst_value, new_data, sel, port.data); port.data = new_data; port.arst = State::S0; } if (emu_srst && port.srst != State::S0) { - Wire *sel = module->addWire(NEW_ID); - FfData ff_sel(module, initvals, NEW_ID); - Wire *new_data = module->addWire(NEW_ID, GetSize(port.data)); + Wire *sel = module->addWire(NEWER_ID); + FfData ff_sel(module, initvals, NEWER_ID); + Wire *new_data = module->addWire(NEWER_ID, GetSize(port.data)); ff_sel.width = 1; ff_sel.has_clk = true; ff_sel.sig_clk = port.clk; @@ -1568,7 +1568,7 @@ void Mem::emulate_reset(int idx, bool emu_init, bool emu_arst, bool emu_srst, Ff ff_sel.val_arst = State::S1; } ff_sel.emit(); - module->addMux(NEW_ID, port.srst_value, new_data, sel, port.data); + module->addMux(NEWER_ID, port.srst_value, new_data, sel, port.data); port.data = new_data; port.srst = State::S0; } @@ -1582,7 +1582,7 @@ void Mem::emulate_rd_ce_over_srst(int idx) { return; } port.ce_over_srst = false; - port.srst = module->And(NEW_ID, port.en, port.srst); + port.srst = module->And(NEWER_ID, port.en, port.srst); } void Mem::emulate_rd_srst_over_ce(int idx) { @@ -1593,7 +1593,7 @@ void Mem::emulate_rd_srst_over_ce(int idx) { return; } port.ce_over_srst = true; - port.en = module->Or(NEW_ID, port.en, port.srst); + port.en = module->Or(NEWER_ID, port.en, port.srst); } bool Mem::emulate_read_first_ok() { @@ -1639,13 +1639,13 @@ void Mem::emulate_read_first(FfInitVals *initvals) { rd_ports[i].transparency_mask[j] = true; } for (auto &port: wr_ports) { - Wire *new_data = module->addWire(NEW_ID, GetSize(port.data)); - Wire *new_addr = module->addWire(NEW_ID, GetSize(port.addr)); + Wire *new_data = module->addWire(NEWER_ID, GetSize(port.data)); + Wire *new_addr = module->addWire(NEWER_ID, GetSize(port.addr)); auto compressed = port.compress_en(); - Wire *new_en = module->addWire(NEW_ID, GetSize(compressed.first)); - FfData ff_data(module, initvals, NEW_ID); - FfData ff_addr(module, initvals, NEW_ID); - FfData ff_en(module, initvals, NEW_ID); + Wire *new_en = module->addWire(NEWER_ID, GetSize(compressed.first)); + FfData ff_data(module, initvals, NEWER_ID); + FfData ff_addr(module, initvals, NEWER_ID); + FfData ff_en(module, initvals, NEWER_ID); ff_data.width = GetSize(port.data); ff_data.has_clk = true; ff_data.sig_clk = port.clk; diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 050fc6bd118..0bc548ea1b9 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3090,7 +3090,7 @@ RTLIL::Process *RTLIL::Module::addProcess(RTLIL::IdString name, const RTLIL::Pro return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed, const std::string &src) { \ - RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \ + RTLIL::SigSpec sig_y = addWire(NEWER_ID, _y_size); \ add ## _func(name, sig_a, sig_y, is_signed, src); \ return sig_y; \ } @@ -3115,7 +3115,7 @@ DEF_METHOD(LogicNot, 1, ID($logic_not)) return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed, const std::string &src) { \ - RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \ + RTLIL::SigSpec sig_y = addWire(NEWER_ID, _y_size); \ add ## _func(name, sig_a, sig_y, is_signed, src); \ return sig_y; \ } @@ -3137,7 +3137,7 @@ DEF_METHOD(Buf, sig_a.size(), ID($buf)) return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \ - RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \ + RTLIL::SigSpec sig_y = addWire(NEWER_ID, _y_size); \ add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \ return sig_y; \ } @@ -3180,7 +3180,7 @@ DEF_METHOD(LogicOr, 1, ID($logic_or)) return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \ - RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \ + RTLIL::SigSpec sig_y = addWire(NEWER_ID, _y_size); \ add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \ return sig_y; \ } @@ -3205,7 +3205,7 @@ DEF_METHOD(Sshr, sig_a.size(), ID($sshr)) return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \ - RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \ + RTLIL::SigSpec sig_y = addWire(NEWER_ID, _y_size); \ add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \ return sig_y; \ } @@ -3225,7 +3225,7 @@ DEF_METHOD(Shiftx, sig_a.size(), ID($shiftx)) return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src) { \ - RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \ + RTLIL::SigSpec sig_y = addWire(NEWER_ID, sig_a.size()); \ add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \ return sig_y; \ } @@ -3246,7 +3246,7 @@ DEF_METHOD(Pmux, ID($pmux), 1) return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src) { \ - RTLIL::SigSpec sig_y = addWire(NEW_ID, _demux ? sig_a.size() << sig_s.size() : sig_a.size() >> sig_s.size()); \ + RTLIL::SigSpec sig_y = addWire(NEWER_ID, _demux ? sig_a.size() << sig_s.size() : sig_a.size() >> sig_s.size()); \ add ## _func(name, sig_a, sig_s, sig_y, src); \ return sig_y; \ } @@ -3265,7 +3265,7 @@ DEF_METHOD(Demux, ID($demux), 1) return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src) { \ - RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \ + RTLIL::SigSpec sig_y = addWire(NEWER_ID, sig_a.size()); \ add ## _func(name, sig_a, sig_s, sig_y, src); \ return sig_y; \ } @@ -3281,7 +3281,7 @@ DEF_METHOD(Bweqx, ID($bweqx)) return cell; \ } \ RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const std::string &src) { \ - RTLIL::SigBit sig2 = addWire(NEW_ID); \ + RTLIL::SigBit sig2 = addWire(NEWER_ID); \ add ## _func(name, sig1, sig2, src); \ return sig2; \ } @@ -3295,7 +3295,7 @@ DEF_METHOD(Bweqx, ID($bweqx)) return cell; \ } \ RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \ - RTLIL::SigBit sig3 = addWire(NEW_ID); \ + RTLIL::SigBit sig3 = addWire(NEWER_ID); \ add ## _func(name, sig1, sig2, sig3, src); \ return sig3; \ } @@ -3310,7 +3310,7 @@ DEF_METHOD(Bweqx, ID($bweqx)) return cell; \ } \ RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \ - RTLIL::SigBit sig4 = addWire(NEW_ID); \ + RTLIL::SigBit sig4 = addWire(NEWER_ID); \ add ## _func(name, sig1, sig2, sig3, sig4, src); \ return sig4; \ } @@ -3326,7 +3326,7 @@ DEF_METHOD(Bweqx, ID($bweqx)) return cell; \ } \ RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \ - RTLIL::SigBit sig5 = addWire(NEW_ID); \ + RTLIL::SigBit sig5 = addWire(NEWER_ID); \ add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \ return sig5; \ } @@ -3935,7 +3935,7 @@ RTLIL::Cell* RTLIL::Module::addAnyinit(RTLIL::IdString name, const RTLIL::SigSpe RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src) { - RTLIL::SigSpec sig = addWire(NEW_ID, width); + RTLIL::SigSpec sig = addWire(NEWER_ID, width); Cell *cell = addCell(name, ID($anyconst)); cell->setParam(ID::WIDTH, width); cell->setPort(ID::Y, sig); @@ -3945,7 +3945,7 @@ RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const st RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src) { - RTLIL::SigSpec sig = addWire(NEW_ID, width); + RTLIL::SigSpec sig = addWire(NEWER_ID, width); Cell *cell = addCell(name, ID($anyseq)); cell->setParam(ID::WIDTH, width); cell->setPort(ID::Y, sig); @@ -3955,7 +3955,7 @@ RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std: RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src) { - RTLIL::SigSpec sig = addWire(NEW_ID, width); + RTLIL::SigSpec sig = addWire(NEWER_ID, width); Cell *cell = addCell(name, ID($allconst)); cell->setParam(ID::WIDTH, width); cell->setPort(ID::Y, sig); @@ -3965,7 +3965,7 @@ RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const st RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src) { - RTLIL::SigSpec sig = addWire(NEW_ID, width); + RTLIL::SigSpec sig = addWire(NEWER_ID, width); Cell *cell = addCell(name, ID($allseq)); cell->setParam(ID::WIDTH, width); cell->setPort(ID::Y, sig); @@ -3975,7 +3975,7 @@ RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std: RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src) { - RTLIL::SigSpec sig = addWire(NEW_ID); + RTLIL::SigSpec sig = addWire(NEWER_ID); Cell *cell = addCell(name, ID($initstate)); cell->setPort(ID::Y, sig); cell->set_src_attribute(src); @@ -3984,7 +3984,7 @@ RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string RTLIL::SigSpec RTLIL::Module::SetTag(RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src) { - RTLIL::SigSpec sig = addWire(NEW_ID, sig_a.size()); + RTLIL::SigSpec sig = addWire(NEWER_ID, sig_a.size()); Cell *cell = addCell(name, ID($set_tag)); cell->parameters[ID::WIDTH] = sig_a.size(); cell->parameters[ID::TAG] = tag; @@ -4011,7 +4011,7 @@ RTLIL::Cell* RTLIL::Module::addSetTag(RTLIL::IdString name, const std::string &t RTLIL::SigSpec RTLIL::Module::GetTag(RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src) { - RTLIL::SigSpec sig = addWire(NEW_ID, sig_a.size()); + RTLIL::SigSpec sig = addWire(NEWER_ID, sig_a.size()); Cell *cell = addCell(name, ID($get_tag)); cell->parameters[ID::WIDTH] = sig_a.size(); cell->parameters[ID::TAG] = tag; @@ -4035,7 +4035,7 @@ RTLIL::Cell* RTLIL::Module::addOverwriteTag(RTLIL::IdString name, const std::str RTLIL::SigSpec RTLIL::Module::OriginalTag(RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src) { - RTLIL::SigSpec sig = addWire(NEW_ID, sig_a.size()); + RTLIL::SigSpec sig = addWire(NEWER_ID, sig_a.size()); Cell *cell = addCell(name, ID($original_tag)); cell->parameters[ID::WIDTH] = sig_a.size(); cell->parameters[ID::TAG] = tag; @@ -4047,7 +4047,7 @@ RTLIL::SigSpec RTLIL::Module::OriginalTag(RTLIL::IdString name, const std::strin RTLIL::SigSpec RTLIL::Module::FutureFF(RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src) { - RTLIL::SigSpec sig = addWire(NEW_ID, sig_e.size()); + RTLIL::SigSpec sig = addWire(NEWER_ID, sig_e.size()); Cell *cell = addCell(name, ID($future_ff)); cell->parameters[ID::WIDTH] = sig_e.size(); cell->setPort(ID::A, sig_e); @@ -4255,7 +4255,7 @@ void RTLIL::Module::bufNormalize() for (auto &chunk : sig.chunks()) if (chunk.wire) outWires.insert(chunk.wire); - Wire *wire = addWire(NEW_ID, GetSize(sig)); + Wire *wire = addWire(NEWER_ID, GetSize(sig)); sigmap.add(sig, wire); cell->setPort(portname, wire); @@ -4268,7 +4268,7 @@ void RTLIL::Module::bufNormalize() for (int i = 0; i < GetSize(wire); i++) if (insig[i] == outsig[i]) insig[i] = State::Sx; - addBuf(NEW_ID, insig, outsig); + addBuf(NEWER_ID, insig, outsig); } } } diff --git a/passes/cmds/abstract.cc b/passes/cmds/abstract.cc index e475ba71c97..adae4d0faa7 100644 --- a/passes/cmds/abstract.cc +++ b/passes/cmds/abstract.cc @@ -82,7 +82,7 @@ struct Slice { }; void emit_mux_anyseq(Module* mod, const SigSpec& mux_input, const SigSpec& mux_output, EnableLogic enable) { - auto anyseq = mod->Anyseq(NEW_ID, mux_input.size()); + auto anyseq = mod->Anyseq(NEWER_ID, mux_input.size()); if (enable.bit == (enable.pol ? State::S1 : State::S0)) { mod->connect(mux_output, anyseq); } @@ -94,7 +94,7 @@ void emit_mux_anyseq(Module* mod, const SigSpec& mux_input, const SigSpec& mux_o mux_a = anyseq; mux_b = mux_input; } - (void)mod->addMux(NEW_ID, + (void)mod->addMux(NEWER_ID, mux_a, mux_b, enable.bit, @@ -102,7 +102,7 @@ void emit_mux_anyseq(Module* mod, const SigSpec& mux_input, const SigSpec& mux_o } bool abstract_state_port(FfData& ff, SigSpec& port_sig, std::set offsets, EnableLogic enable) { - Wire* abstracted = ff.module->addWire(NEW_ID, offsets.size()); + Wire* abstracted = ff.module->addWire(NEWER_ID, offsets.size()); SigSpec mux_input; int abstracted_idx = 0; for (int d_idx = 0; d_idx < ff.width; d_idx++) { @@ -213,7 +213,7 @@ unsigned int abstract_state(Module* mod, EnableLogic enable, const std::vector offsets, IdString port_name, EnableLogic enable) { - Wire* to_abstract = mod->addWire(NEW_ID, offsets.size()); + Wire* to_abstract = mod->addWire(NEWER_ID, offsets.size()); SigSpec mux_input; SigSpec mux_output; const SigSpec& old_port = cell->getPort(port_name); @@ -235,7 +235,7 @@ bool abstract_value_cell_port(Module* mod, Cell* cell, std::set offsets, Id } bool abstract_value_mod_port(Module* mod, Wire* wire, std::set offsets, EnableLogic enable) { - Wire* to_abstract = mod->addWire(NEW_ID, wire); + Wire* to_abstract = mod->addWire(NEWER_ID, wire); to_abstract->port_input = true; to_abstract->port_id = wire->port_id; wire->port_input = false; @@ -501,10 +501,10 @@ struct AbstractPass : public Pass { enable_logic = { enable_wire, enable == Enable::ActiveHigh }; } break; case Enable::Initstates: { - SigBit in_init_states = mod->Initstate(NEW_ID); + SigBit in_init_states = mod->Initstate(NEWER_ID); for (int i = 1; i < initstates; i++) { - Wire *in_init_states_q = mod->addWire(NEW_ID); - mod->addFf(NEW_ID, in_init_states, in_init_states_q); + Wire *in_init_states_q = mod->addWire(NEWER_ID); + mod->addFf(NEWER_ID, in_init_states, in_init_states_q); in_init_states_q->attributes[ID::init] = State::S1; in_init_states = in_init_states_q; } diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index 0d395f04319..abd36c831ec 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -41,7 +41,7 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const log_error("Could not find wire with name \"%s\".\n", name); } else { - RTLIL::Cell *formal_cell = module->addCell(NEW_ID, "$" + celltype); + RTLIL::Cell *formal_cell = module->addCell(NEWER_ID, "$" + celltype); formal_cell->setPort(ID::A, wire); if(enable_name == "") { formal_cell->setPort(ID::EN, State::S1); diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc index 897dd845903..687d9c48c1d 100644 --- a/passes/cmds/bugpoint.cc +++ b/passes/cmds/bugpoint.cc @@ -304,7 +304,7 @@ struct BugpointPass : public Pass { if (!stage2 && (cell->input(it.first) || cell->output(it.first)) && index++ == seed) { log_header(design, "Trying to expose cell port %s.%s.%s as module port.\n", log_id(mod), log_id(cell), log_id(it.first)); - RTLIL::Wire *wire = mod->addWire(NEW_ID, port.size()); + RTLIL::Wire *wire = mod->addWire(NEWER_ID, port.size()); wire->set_bool_attribute(ID($bugpoint)); wire->port_input = cell->input(it.first); wire->port_output = cell->output(it.first); diff --git a/passes/cmds/chformal.cc b/passes/cmds/chformal.cc index ccda023c0e8..3e6f48eeafe 100644 --- a/passes/cmds/chformal.cc +++ b/passes/cmds/chformal.cc @@ -337,12 +337,12 @@ struct ChformalPass : public Pass { SigSpec orig_a = cell->getPort(ID::A); SigSpec orig_en = cell->getPort(ID::EN); - Wire *new_a = module->addWire(NEW_ID); - Wire *new_en = module->addWire(NEW_ID); + Wire *new_a = module->addWire(NEWER_ID); + Wire *new_en = module->addWire(NEWER_ID); new_en->attributes[ID::init] = State::S0; - module->addFf(NEW_ID, orig_a, new_a); - module->addFf(NEW_ID, orig_en, new_en); + module->addFf(NEWER_ID, orig_a, new_a); + module->addFf(NEWER_ID, orig_en, new_en); cell->setPort(ID::A, new_a); cell->setPort(ID::EN, new_en); @@ -355,14 +355,14 @@ struct ChformalPass : public Pass { SigSpec en = State::S1; for (int i = 0; i < mode_arg; i++) { - Wire *w = module->addWire(NEW_ID); + Wire *w = module->addWire(NEWER_ID); w->attributes[ID::init] = State::S0; - module->addFf(NEW_ID, en, w); + module->addFf(NEWER_ID, en, w); en = w; } for (auto cell : constr_cells) - cell->setPort(ID::EN, module->LogicAnd(NEW_ID, en, cell->getPort(ID::EN))); + cell->setPort(ID::EN, module->LogicAnd(NEWER_ID, en, cell->getPort(ID::EN))); } else if (mode =='p') @@ -370,7 +370,7 @@ struct ChformalPass : public Pass { for (auto cell : constr_cells) { if (cell->type == ID($check)) { - Cell *cover = module->addCell(NEW_ID_SUFFIX("coverenable"), ID($check)); + Cell *cover = module->addCell(NEWER_ID_SUFFIX("coverenable"), ID($check)); cover->attributes = cell->attributes; cover->parameters = cell->parameters; cover->setParam(ID(FLAVOR), Const("cover")); @@ -381,7 +381,7 @@ struct ChformalPass : public Pass { cover->setPort(ID::A, cell->getPort(ID::EN)); cover->setPort(ID::EN, State::S1); } else { - module->addCover(NEW_ID_SUFFIX("coverenable"), + module->addCover(NEWER_ID_SUFFIX("coverenable"), cell->getPort(ID::EN), State::S1, cell->get_src_attribute()); } } @@ -414,7 +414,7 @@ struct ChformalPass : public Pass { log_error("Cannot lower edge triggered $check cell %s, run async2sync or clk2fflogic first.\n", log_id(cell)); - Cell *plain_cell = module->addCell(NEW_ID, formal_flavor(cell)); + Cell *plain_cell = module->addCell(NEWER_ID, formal_flavor(cell)); plain_cell->attributes = cell->attributes; @@ -425,9 +425,9 @@ struct ChformalPass : public Pass { plain_cell->setPort(ID::EN, sig_en); if (plain_cell->type.in(ID($assert), ID($assume))) - sig_a = module->Not(NEW_ID, sig_a); + sig_a = module->Not(NEWER_ID, sig_a); - SigBit combined_en = module->And(NEW_ID, sig_a, sig_en); + SigBit combined_en = module->And(NEWER_ID, sig_a, sig_en); module->swap_names(cell, plain_cell); diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index 65292ef92e9..911498d5dde 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -30,7 +30,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap & { CellTypes ct(design); - RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size()); + RTLIL::Wire *dummy_wire = module->addWire(NEWER_ID, sig.size()); for (auto cell : module->cells()) for (auto &port : cell->connections_) diff --git a/passes/cmds/dft_tag.cc b/passes/cmds/dft_tag.cc index 5d9756ca054..3122cf0d3ff 100644 --- a/passes/cmds/dft_tag.cc +++ b/passes/cmds/dft_tag.cc @@ -101,7 +101,7 @@ struct DftTagWorker { log_debug("Applying $overwrite_tag %s for signal %s\n", log_id(cell->name), log_signal(cell->getPort(ID::A))); SigSpec orig_signal = cell->getPort(ID::A); SigSpec interposed_signal = divert_users(orig_signal); - auto *set_tag_cell = module->addSetTag(NEW_ID, cell->getParam(ID::TAG).decode_string(), orig_signal, cell->getPort(ID::SET), cell->getPort(ID::CLR), interposed_signal); + auto *set_tag_cell = module->addSetTag(NEWER_ID, cell->getParam(ID::TAG).decode_string(), orig_signal, cell->getPort(ID::SET), cell->getPort(ID::CLR), interposed_signal); modwalker.add_cell(set_tag_cell); // Make sure the next $overwrite_tag sees the new connections design_changed = true; } @@ -123,7 +123,7 @@ struct DftTagWorker { signal_mapped.sort_and_unify(); if (GetSize(signal_mapped) < GetSize(signal)) log_warning("Detected $overwrite_tag on signal %s which contains repeated bits, this can result in unexpected behavior.\n", log_signal(signal)); - SigSpec new_wire = module->addWire(NEW_ID, GetSize(signal)); + SigSpec new_wire = module->addWire(NEWER_ID, GetSize(signal)); for (int i = 0; i < GetSize(new_wire); ++i) divert_users(signal[i], new_wire[i]); return new_wire; @@ -318,7 +318,7 @@ struct DftTagWorker { if (!GetSize(combined)) combined = tag_sig; else - combined = autoOr(NEW_ID, combined, tag_sig); + combined = autoOr(NEWER_ID, combined, tag_sig); } if (!GetSize(combined)) @@ -359,7 +359,7 @@ struct DftTagWorker { // when the outer call for this tag/cell returns for (auto &conn : cell->connections()) if (cell->output(conn.first)) - emit_tag_signal(tag, conn.second, module->addWire(NEW_ID, GetSize(conn.second))); + emit_tag_signal(tag, conn.second, module->addWire(NEWER_ID, GetSize(conn.second))); return; } @@ -486,8 +486,8 @@ struct DftTagWorker { if (cell_tag == tag) { auto &sig_set = cell->getPort(ID::SET); auto &sig_clr = cell->getPort(ID::CLR); - tag_sig_a = autoAnd(NEW_ID, tag_sig_a, autoNot(NEW_ID, sig_clr)); - tag_sig_a = autoOr(NEW_ID, tag_sig_a, sig_set); + tag_sig_a = autoAnd(NEWER_ID, tag_sig_a, autoNot(NEWER_ID, sig_clr)); + tag_sig_a = autoOr(NEWER_ID, tag_sig_a, sig_set); } emit_tag_signal(tag, sig_y, tag_sig_a); @@ -529,9 +529,9 @@ struct DftTagWorker { inv_b ^= true; if (inv_a) - sig_a = autoNot(NEW_ID, sig_a); + sig_a = autoNot(NEWER_ID, sig_a); if (inv_b) - sig_b = autoNot(NEW_ID, sig_b); + sig_b = autoNot(NEWER_ID, sig_b); auto group_sig_a = tag_group_signal(tag, sig_a); auto group_sig_b = tag_group_signal(tag, sig_b); @@ -541,15 +541,15 @@ struct DftTagWorker { // Does this input allow propagating (doesn't fix output or same tag group) - sig_a = autoOr(NEW_ID, sig_a, group_sig_a); - sig_b = autoOr(NEW_ID, sig_b, group_sig_b); + sig_a = autoOr(NEWER_ID, sig_a, group_sig_a); + sig_b = autoOr(NEWER_ID, sig_b, group_sig_b); // Mask input tags by whether the other side allows propagation - tag_sig_a = autoAnd(NEW_ID, tag_sig_a, sig_b); - tag_sig_b = autoAnd(NEW_ID, tag_sig_b, sig_a); + tag_sig_a = autoAnd(NEWER_ID, tag_sig_a, sig_b); + tag_sig_b = autoAnd(NEWER_ID, tag_sig_b, sig_a); - auto tag_sig = autoOr(NEW_ID, tag_sig_a, tag_sig_b); + auto tag_sig = autoOr(NEWER_ID, tag_sig_a, tag_sig_b); emit_tag_signal(tag, sig_y, tag_sig); return; } @@ -566,7 +566,7 @@ struct DftTagWorker { auto tag_sig_a = tag_signal(tag, sig_a); auto tag_sig_b = tag_signal(tag, sig_b); - auto tag_sig = autoOr(NEW_ID, tag_sig_a, tag_sig_b); + auto tag_sig = autoOr(NEWER_ID, tag_sig_a, tag_sig_b); emit_tag_signal(tag, sig_y, tag_sig); return; } @@ -585,23 +585,23 @@ struct DftTagWorker { auto group_sig_b = tag_group_signal(tag, sig_b); auto group_sig_s = tag_group_signal(tag, sig_s); - auto prop_s = autoOr(NEW_ID, - autoXor(NEW_ID, sig_a, sig_b), - autoOr(NEW_ID, group_sig_a, group_sig_b)); + auto prop_s = autoOr(NEWER_ID, + autoXor(NEWER_ID, sig_a, sig_b), + autoOr(NEWER_ID, group_sig_a, group_sig_b)); - auto prop_a = autoOr(NEW_ID, autoNot(NEW_ID, sig_s), group_sig_s); - auto prop_b = autoOr(NEW_ID, sig_s, group_sig_s); + auto prop_a = autoOr(NEWER_ID, autoNot(NEWER_ID, sig_s), group_sig_s); + auto prop_b = autoOr(NEWER_ID, sig_s, group_sig_s); auto tag_sig_a = tag_signal(tag, sig_a); auto tag_sig_b = tag_signal(tag, sig_b); auto tag_sig_s = tag_signal(tag, sig_s); - tag_sig_a = autoAnd(NEW_ID, tag_sig_a, prop_a); - tag_sig_b = autoAnd(NEW_ID, tag_sig_b, prop_b); - tag_sig_s = autoAnd(NEW_ID, tag_sig_s, prop_s); + tag_sig_a = autoAnd(NEWER_ID, tag_sig_a, prop_a); + tag_sig_b = autoAnd(NEWER_ID, tag_sig_b, prop_b); + tag_sig_s = autoAnd(NEWER_ID, tag_sig_s, prop_s); - auto tag_sig = autoOr(NEW_ID, tag_sig_s, - autoOr(NEW_ID, tag_sig_a, tag_sig_b)); + auto tag_sig = autoOr(NEWER_ID, tag_sig_s, + autoOr(NEWER_ID, tag_sig_a, tag_sig_b)); emit_tag_signal(tag, sig_y, tag_sig); return; } @@ -620,15 +620,15 @@ struct DftTagWorker { auto tag_sig_a = tag_signal(tag, sig_a); auto tag_sig_b = tag_signal(tag, sig_b); - auto group_sig = autoOr(NEW_ID, group_sig_a, group_sig_b); + auto group_sig = autoOr(NEWER_ID, group_sig_a, group_sig_b); // The output can only be affected by the tagged inputs if all group-untagged bits are equal - auto masked_a = autoOr(NEW_ID, sig_a, group_sig); - auto masked_b = autoOr(NEW_ID, sig_b, group_sig); + auto masked_a = autoOr(NEWER_ID, sig_a, group_sig); + auto masked_b = autoOr(NEWER_ID, sig_b, group_sig); - auto prop = autoEq(NEW_ID, masked_a, masked_b); + auto prop = autoEq(NEWER_ID, masked_a, masked_b); - auto tag_sig = autoAnd(NEW_ID, prop, autoReduceOr(NEW_ID, {tag_sig_a, tag_sig_b})); + auto tag_sig = autoAnd(NEWER_ID, prop, autoReduceOr(NEWER_ID, {tag_sig_a, tag_sig_b})); tag_sig.extend_u0(GetSize(sig_y), false); emit_tag_signal(tag, sig_y, tag_sig); return; @@ -652,15 +652,15 @@ struct DftTagWorker { auto tag_sig_a = tag_signal(tag, sig_a); auto tag_sig_b = tag_signal(tag, sig_b); - auto group_sig = autoOr(NEW_ID, group_sig_a, group_sig_b); + auto group_sig = autoOr(NEWER_ID, group_sig_a, group_sig_b); // The output can only be affected by the tagged inputs if the greatest possible sig_a is // greater or equal to the least possible sig_b - auto masked_a = autoOr(NEW_ID, sig_a, group_sig); - auto masked_b = autoAnd(NEW_ID, sig_b, autoNot(NEW_ID, group_sig)); + auto masked_a = autoOr(NEWER_ID, sig_a, group_sig); + auto masked_b = autoAnd(NEWER_ID, sig_b, autoNot(NEWER_ID, group_sig)); - auto prop = autoGe(NEW_ID, masked_a, masked_b); + auto prop = autoGe(NEWER_ID, masked_a, masked_b); - auto tag_sig = autoAnd(NEW_ID, prop, autoReduceOr(NEW_ID, {tag_sig_a, tag_sig_b})); + auto tag_sig = autoAnd(NEWER_ID, prop, autoReduceOr(NEWER_ID, {tag_sig_a, tag_sig_b})); tag_sig.extend_u0(GetSize(sig_y), false); emit_tag_signal(tag, sig_y, tag_sig); return; @@ -674,13 +674,13 @@ struct DftTagWorker { auto tag_sig_a = tag_signal(tag, sig_a); if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($logic_not))) - sig_a = autoNot(NEW_ID, sig_a); + sig_a = autoNot(NEWER_ID, sig_a); - auto filled = autoOr(NEW_ID, sig_a, group_sig_a); + auto filled = autoOr(NEWER_ID, sig_a, group_sig_a); - auto prop = autoReduceAnd(NEW_ID, filled); - auto tagged = autoReduceOr(NEW_ID, tag_sig_a); - auto tag_sig = autoAnd(NEW_ID, prop, tagged); + auto prop = autoReduceAnd(NEWER_ID, filled); + auto tagged = autoReduceOr(NEWER_ID, tag_sig_a); + auto tag_sig = autoAnd(NEWER_ID, prop, tagged); tag_sig.extend_u0(GetSize(sig_y), false); emit_tag_signal(tag, sig_y, tag_sig); return; @@ -698,10 +698,10 @@ struct DftTagWorker { auto sig_q = ff.sig_q; auto sig_d = ff.sig_d; - ff.name = NEW_ID; + ff.name = NEWER_ID; ff.cell = nullptr; ff.sig_d = tag_signal(tag, ff.sig_d); - ff.sig_q = module->addWire(NEW_ID, width); + ff.sig_q = module->addWire(NEWER_ID, width); ff.is_anyinit = false; ff.val_init = Const(0, width); ff.emit(); @@ -727,7 +727,7 @@ struct DftTagWorker { } } - SigBit any_tagged = autoReduceOr(NEW_ID, tag_input); + SigBit any_tagged = autoReduceOr(NEWER_ID, tag_input); for (auto &conn : cell->connections()) { if (cell->output(conn.first)) { diff --git a/passes/cmds/glift.cc b/passes/cmds/glift.cc index d7264d392a3..9433594613d 100644 --- a/passes/cmds/glift.cc +++ b/passes/cmds/glift.cc @@ -144,7 +144,7 @@ struct GliftWorker { //In this case, a nonzero hole metamux select value means less logic. //Thus we should invert the ReduceOr over the metamux_select signal. RTLIL::SigSpec pmux_select = module->ReduceOr(metamux_select.as_wire()->name.str() + "_nonzero", metamux_select); - return module->Pmux(NEW_ID, RTLIL::Const(1), RTLIL::Const(0), pmux_select, metamux_select.as_wire()->get_src_attribute()); + return module->Pmux(NEWER_ID, RTLIL::Const(1), RTLIL::Const(0), pmux_select, metamux_select.as_wire()->get_src_attribute()); } else { auto select_width = metamux_select.as_wire()->width; diff --git a/passes/cmds/portarcs.cc b/passes/cmds/portarcs.cc index 36870489a00..f5d7565b0e6 100644 --- a/passes/cmds/portarcs.cc +++ b/passes/cmds/portarcs.cc @@ -291,7 +291,7 @@ struct PortarcsPass : Pass { int *p = annotations.at(canonical_bit(bit)); for (auto i = 0; i < inputs.size(); i++) { if (p[i] >= 0) { - Cell *spec = m->addCell(NEW_ID, ID($specify2)); + Cell *spec = m->addCell(NEWER_ID, ID($specify2)); spec->setParam(ID::SRC_WIDTH, 1); spec->setParam(ID::DST_WIDTH, 1); spec->setParam(ID::T_FALL_MAX, p[i]); diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index c4bb7135e76..c8d6f73b7ab 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -494,11 +494,11 @@ struct RenamePass : public Pass { for (auto wire : module->selected_wires()) if (wire->name.isPublic() && wire->port_id == 0) - new_wire_names[wire] = NEW_ID; + new_wire_names[wire] = NEWER_ID; for (auto cell : module->selected_cells()) if (cell->name.isPublic()) - new_cell_names[cell] = NEW_ID; + new_cell_names[cell] = NEWER_ID; for (auto &it : new_wire_names) module->rename(it.first, it.second); diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc index 017600a46f7..00dbeb0d1fa 100644 --- a/passes/cmds/scatter.cc +++ b/passes/cmds/scatter.cc @@ -51,7 +51,7 @@ struct ScatterPass : public Pass { for (auto cell : module->cells()) { dict new_connections; for (auto conn : cell->connections()) - new_connections.emplace(conn.first, RTLIL::SigSig(conn.second, module->addWire(NEW_ID, GetSize(conn.second)))); + new_connections.emplace(conn.first, RTLIL::SigSig(conn.second, module->addWire(NEWER_ID, GetSize(conn.second)))); for (auto &it : new_connections) { if (ct.cell_output(cell->type, it.first)) module->connect(RTLIL::SigSig(it.second.first, it.second.second)); diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 6d3e30561a7..5a814dd8063 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -345,9 +345,9 @@ struct SetundefPass : public Pass { for (auto &c : sig.chunks()) { RTLIL::SigSpec bits; if (worker.next_bit_mode == MODE_ANYSEQ) - bits = module->Anyseq(NEW_ID, c.width); + bits = module->Anyseq(NEWER_ID, c.width); else if (worker.next_bit_mode == MODE_ANYCONST) - bits = module->Anyconst(NEW_ID, c.width); + bits = module->Anyconst(NEWER_ID, c.width); else for (int i = 0; i < c.width; i++) bits.append(worker.next_bit()); @@ -530,9 +530,9 @@ struct SetundefPass : public Pass { if (width > 0) { if (worker.next_bit_mode == MODE_ANYSEQ) - sig.replace(cursor, module->Anyseq(NEW_ID, width)); + sig.replace(cursor, module->Anyseq(NEWER_ID, width)); else - sig.replace(cursor, module->Anyconst(NEW_ID, width)); + sig.replace(cursor, module->Anyconst(NEWER_ID, width)); cursor += width; } else { cursor++; diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 2993c3d3aa9..8f8872fb952 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -75,12 +75,12 @@ struct SpliceWorker RTLIL::SigSpec new_sig = sig; if (sig_a.size() != sig.size()) { - RTLIL::Cell *cell = module->addCell(NEW_ID, ID($slice)); + RTLIL::Cell *cell = module->addCell(NEWER_ID, ID($slice)); cell->parameters[ID::OFFSET] = offset; cell->parameters[ID::A_WIDTH] = sig_a.size(); cell->parameters[ID::Y_WIDTH] = sig.size(); cell->setPort(ID::A, sig_a); - cell->setPort(ID::Y, module->addWire(NEW_ID, sig.size())); + cell->setPort(ID::Y, module->addWire(NEWER_ID, sig.size())); new_sig = cell->getPort(ID::Y); } @@ -132,12 +132,12 @@ struct SpliceWorker RTLIL::SigSpec new_sig = get_sliced_signal(chunks.front()); for (size_t i = 1; i < chunks.size(); i++) { RTLIL::SigSpec sig2 = get_sliced_signal(chunks[i]); - RTLIL::Cell *cell = module->addCell(NEW_ID, ID($concat)); + RTLIL::Cell *cell = module->addCell(NEWER_ID, ID($concat)); cell->parameters[ID::A_WIDTH] = new_sig.size(); cell->parameters[ID::B_WIDTH] = sig2.size(); cell->setPort(ID::A, new_sig); cell->setPort(ID::B, sig2); - cell->setPort(ID::Y, module->addWire(NEW_ID, new_sig.size() + sig2.size())); + cell->setPort(ID::Y, module->addWire(NEWER_ID, new_sig.size() + sig2.size())); new_sig = cell->getPort(ID::Y); } @@ -232,7 +232,7 @@ struct SpliceWorker for (auto &it : rework_wires) { RTLIL::IdString orig_name = it.first->name; - module->rename(it.first, NEW_ID); + module->rename(it.first, NEWER_ID); RTLIL::Wire *new_port = module->addWire(orig_name, it.first); it.first->port_id = 0; diff --git a/passes/cmds/xprop.cc b/passes/cmds/xprop.cc index 8b2e7ae08b4..a5aa2ff9387 100644 --- a/passes/cmds/xprop.cc +++ b/passes/cmds/xprop.cc @@ -55,18 +55,18 @@ struct XpropWorker Module *module; void invert() { std::swap(is_0, is_1); } - void auto_0() { connect_0(module->Not(NEW_ID, module->Or(NEW_ID, is_1, is_x))); } - void auto_1() { connect_1(module->Not(NEW_ID, module->Or(NEW_ID, is_0, is_x))); } - void auto_x() { connect_x(module->Not(NEW_ID, module->Or(NEW_ID, is_0, is_1))); } + void auto_0() { connect_0(module->Not(NEWER_ID, module->Or(NEWER_ID, is_1, is_x))); } + void auto_1() { connect_1(module->Not(NEWER_ID, module->Or(NEWER_ID, is_0, is_x))); } + void auto_x() { connect_x(module->Not(NEWER_ID, module->Or(NEWER_ID, is_0, is_1))); } void connect_0(SigSpec sig) { module->connect(is_0, sig); } void connect_1(SigSpec sig) { module->connect(is_1, sig); } void connect_x(SigSpec sig) { module->connect(is_x, sig); } - void connect_1_under_x(SigSpec sig) { connect_1(module->And(NEW_ID, sig, module->Not(NEW_ID, is_x))); } - void connect_0_under_x(SigSpec sig) { connect_0(module->And(NEW_ID, sig, module->Not(NEW_ID, is_x))); } + void connect_1_under_x(SigSpec sig) { connect_1(module->And(NEWER_ID, sig, module->Not(NEWER_ID, is_x))); } + void connect_0_under_x(SigSpec sig) { connect_0(module->And(NEWER_ID, sig, module->Not(NEWER_ID, is_x))); } - void connect_x_under_0(SigSpec sig) { connect_x(module->And(NEW_ID, sig, module->Not(NEW_ID, is_0))); } + void connect_x_under_0(SigSpec sig) { connect_x(module->And(NEWER_ID, sig, module->Not(NEWER_ID, is_0))); } void connect_as_bool() { int width = GetSize(is_0); @@ -198,13 +198,13 @@ struct XpropWorker } if (!invert.empty() && !driving) - invert = module->Not(NEW_ID, invert); + invert = module->Not(NEWER_ID, invert); EncodedSig new_sigs; if (new_bits > 0) { - new_sigs.is_0 = module->addWire(NEW_ID, new_bits); - new_sigs.is_1 = module->addWire(NEW_ID, new_bits); - new_sigs.is_x = module->addWire(NEW_ID, new_bits); + new_sigs.is_0 = module->addWire(NEWER_ID, new_bits); + new_sigs.is_1 = module->addWire(NEWER_ID, new_bits); + new_sigs.is_x = module->addWire(NEWER_ID, new_bits); } int invert_pos = 0; @@ -253,7 +253,7 @@ struct XpropWorker } if (!driven_orig.empty()) { - auto decoder = module->addBwmux(NEW_ID, driven_enc.is_1, Const(State::Sx, GetSize(driven_orig)), driven_enc.is_x, driven_orig); + auto decoder = module->addBwmux(NEWER_ID, driven_enc.is_1, Const(State::Sx, GetSize(driven_orig)), driven_enc.is_x, driven_orig); decoder->set_bool_attribute(ID::xprop_decoder); } if (!driven_never_x.first.empty()) { @@ -261,21 +261,21 @@ struct XpropWorker } if (driving && (options.assert_encoding || options.assume_encoding)) { - auto not_0 = module->Not(NEW_ID, result.is_0); - auto not_1 = module->Not(NEW_ID, result.is_1); - auto not_x = module->Not(NEW_ID, result.is_x); - auto valid = module->ReduceAnd(NEW_ID, { - module->Eq(NEW_ID, result.is_0, module->And(NEW_ID, not_1, not_x)), - module->Eq(NEW_ID, result.is_1, module->And(NEW_ID, not_0, not_x)), - module->Eq(NEW_ID, result.is_x, module->And(NEW_ID, not_0, not_1)), + auto not_0 = module->Not(NEWER_ID, result.is_0); + auto not_1 = module->Not(NEWER_ID, result.is_1); + auto not_x = module->Not(NEWER_ID, result.is_x); + auto valid = module->ReduceAnd(NEWER_ID, { + module->Eq(NEWER_ID, result.is_0, module->And(NEWER_ID, not_1, not_x)), + module->Eq(NEWER_ID, result.is_1, module->And(NEWER_ID, not_0, not_x)), + module->Eq(NEWER_ID, result.is_x, module->And(NEWER_ID, not_0, not_1)), }); if (options.assert_encoding) - module->addAssert(NEW_ID_SUFFIX("xprop_enc"), valid, State::S1); + module->addAssert(NEWER_ID_SUFFIX("xprop_enc"), valid, State::S1); else - module->addAssume(NEW_ID_SUFFIX("xprop_enc"), valid, State::S1); + module->addAssume(NEWER_ID_SUFFIX("xprop_enc"), valid, State::S1); if (options.debug_asserts) { - auto bad_bits = module->Bweqx(NEW_ID, {result.is_0, result.is_1, result.is_x}, Const(State::Sx, GetSize(result) * 3)); - module->addAssert(NEW_ID_SUFFIX("xprop_debug"), module->LogicNot(NEW_ID, bad_bits), State::S1); + auto bad_bits = module->Bweqx(NEWER_ID, {result.is_0, result.is_1, result.is_x}, Const(State::Sx, GetSize(result) * 3)); + module->addAssert(NEWER_ID_SUFFIX("xprop_debug"), module->LogicNot(NEWER_ID, bad_bits), State::S1); } } @@ -543,8 +543,8 @@ struct XpropWorker if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_))) enc_b.invert(); - enc_y.connect_0(module->Or(NEW_ID, enc_a.is_0, enc_b.is_0)); - enc_y.connect_1(module->And(NEW_ID, enc_a.is_1, enc_b.is_1)); + enc_y.connect_0(module->Or(NEWER_ID, enc_a.is_0, enc_b.is_0)); + enc_y.connect_1(module->And(NEWER_ID, enc_a.is_1, enc_b.is_1)); enc_y.auto_x(); module->remove(cell); return; @@ -564,8 +564,8 @@ struct XpropWorker if (cell->type == ID($logic_not)) enc_a.invert(); - enc_y.connect_0(module->ReduceOr(NEW_ID, enc_a.is_0)); - enc_y.connect_1(module->ReduceAnd(NEW_ID, enc_a.is_1)); + enc_y.connect_0(module->ReduceOr(NEWER_ID, enc_a.is_0)); + enc_y.connect_1(module->ReduceAnd(NEWER_ID, enc_a.is_1)); enc_y.auto_x(); module->remove(cell); @@ -584,8 +584,8 @@ struct XpropWorker enc_y.invert(); - enc_y.connect_x(module->ReduceOr(NEW_ID, enc_a.is_x)); - enc_y.connect_1_under_x(module->ReduceXor(NEW_ID, enc_a.is_1)); + enc_y.connect_x(module->ReduceOr(NEWER_ID, enc_a.is_x)); + enc_y.connect_1_under_x(module->ReduceXor(NEWER_ID, enc_a.is_1)); enc_y.auto_0(); module->remove(cell); @@ -603,16 +603,16 @@ struct XpropWorker enc_y.connect_as_bool(); - auto a_is_1 = module->ReduceOr(NEW_ID, enc_a.is_1); - auto a_is_0 = module->ReduceAnd(NEW_ID, enc_a.is_0); - auto b_is_1 = module->ReduceOr(NEW_ID, enc_b.is_1); - auto b_is_0 = module->ReduceAnd(NEW_ID, enc_b.is_0); + auto a_is_1 = module->ReduceOr(NEWER_ID, enc_a.is_1); + auto a_is_0 = module->ReduceAnd(NEWER_ID, enc_a.is_0); + auto b_is_1 = module->ReduceOr(NEWER_ID, enc_b.is_1); + auto b_is_0 = module->ReduceAnd(NEWER_ID, enc_b.is_0); if (cell->type == ID($logic_or)) enc_y.invert(), std::swap(a_is_0, a_is_1), std::swap(b_is_0, b_is_1); - enc_y.connect_0(module->Or(NEW_ID, a_is_0, b_is_0)); - enc_y.connect_1(module->And(NEW_ID, a_is_1, b_is_1)); + enc_y.connect_0(module->Or(NEWER_ID, a_is_0, b_is_0)); + enc_y.connect_1(module->And(NEWER_ID, a_is_1, b_is_1)); enc_y.auto_x(); module->remove(cell); return; @@ -634,8 +634,8 @@ struct XpropWorker if (cell->type.in(ID($xnor), ID($_XNOR_))) enc_y.invert(); - enc_y.connect_x(module->Or(NEW_ID, enc_a.is_x, enc_b.is_x)); - enc_y.connect_1_under_x(module->Xor(NEW_ID, enc_a.is_1, enc_b.is_1)); + enc_y.connect_x(module->Or(NEWER_ID, enc_a.is_x, enc_b.is_x)); + enc_y.connect_1_under_x(module->Xor(NEWER_ID, enc_a.is_1, enc_b.is_1)); enc_y.auto_0(); module->remove(cell); return; @@ -657,11 +657,11 @@ struct XpropWorker if (cell->type == ID($ne)) enc_y.invert(); - auto delta = module->Xor(NEW_ID, enc_a.is_1, enc_b.is_1); - auto xpos = module->Or(NEW_ID, enc_a.is_x, enc_b.is_x); + auto delta = module->Xor(NEWER_ID, enc_a.is_1, enc_b.is_1); + auto xpos = module->Or(NEWER_ID, enc_a.is_x, enc_b.is_x); - enc_y.connect_0(module->ReduceOr(NEW_ID, module->And(NEW_ID, delta, module->Not(NEW_ID, xpos)))); - enc_y.connect_x_under_0(module->ReduceOr(NEW_ID, xpos)); + enc_y.connect_0(module->ReduceOr(NEWER_ID, module->And(NEWER_ID, delta, module->Not(NEWER_ID, xpos)))); + enc_y.connect_x_under_0(module->ReduceOr(NEWER_ID, xpos)); enc_y.auto_1(); module->remove(cell); return; @@ -678,12 +678,12 @@ struct XpropWorker auto enc_a = encoded(sig_a); auto enc_b = encoded(sig_b); - auto delta_0 = module->Xnor(NEW_ID, enc_a.is_0, enc_b.is_0); - auto delta_1 = module->Xnor(NEW_ID, enc_a.is_1, enc_b.is_1); + auto delta_0 = module->Xnor(NEWER_ID, enc_a.is_0, enc_b.is_0); + auto delta_1 = module->Xnor(NEWER_ID, enc_a.is_1, enc_b.is_1); - auto eq = module->ReduceAnd(NEW_ID, {delta_0, delta_1}); + auto eq = module->ReduceAnd(NEWER_ID, {delta_0, delta_1}); - auto res = cell->type == ID($nex) ? module->Not(NEW_ID, eq) : eq; + auto res = cell->type == ID($nex) ? module->Not(NEWER_ID, eq) : eq; module->connect(sig_y[0], res); if (GetSize(sig_y) > 1) @@ -700,9 +700,9 @@ struct XpropWorker auto enc_a = encoded(sig_a); auto enc_b = encoded(sig_b); - auto delta_0 = module->Xnor(NEW_ID, enc_a.is_0, enc_b.is_0); - auto delta_1 = module->Xnor(NEW_ID, enc_a.is_1, enc_b.is_1); - module->addAnd(NEW_ID, delta_0, delta_1, sig_y); + auto delta_0 = module->Xnor(NEWER_ID, enc_a.is_0, enc_b.is_0); + auto delta_1 = module->Xnor(NEWER_ID, enc_a.is_1, enc_b.is_1); + module->addAnd(NEWER_ID, delta_0, delta_1, sig_y); module->remove(cell); return; } @@ -721,12 +721,12 @@ struct XpropWorker auto enc_s = encoded(sig_s); auto enc_y = encoded(sig_y, true); - enc_y.connect_1(module->And(NEW_ID, - module->Or(NEW_ID, enc_a.is_1, enc_s.is_1), - module->Or(NEW_ID, enc_b.is_1, enc_s.is_0))); - enc_y.connect_0(module->And(NEW_ID, - module->Or(NEW_ID, enc_a.is_0, enc_s.is_1), - module->Or(NEW_ID, enc_b.is_0, enc_s.is_0))); + enc_y.connect_1(module->And(NEWER_ID, + module->Or(NEWER_ID, enc_a.is_1, enc_s.is_1), + module->Or(NEWER_ID, enc_b.is_1, enc_s.is_0))); + enc_y.connect_0(module->And(NEWER_ID, + module->Or(NEWER_ID, enc_a.is_0, enc_s.is_1), + module->Or(NEWER_ID, enc_b.is_0, enc_s.is_0))); enc_y.auto_x(); module->remove(cell); return; @@ -745,23 +745,23 @@ struct XpropWorker int width = GetSize(enc_y); - auto all_x = module->ReduceOr(NEW_ID, { + auto all_x = module->ReduceOr(NEWER_ID, { enc_s.is_x, - module->And(NEW_ID, enc_s.is_1, module->Sub(NEW_ID, enc_s.is_1, Const(1, width))) + module->And(NEWER_ID, enc_s.is_1, module->Sub(NEWER_ID, enc_s.is_1, Const(1, width))) }); auto selected = enc_a; for (int i = 0; i < GetSize(enc_s); i++) { auto sel_bit = enc_s.is_1[i]; - selected.is_0 = module->Mux(NEW_ID, selected.is_0, enc_b.is_0.extract(i * width, width), sel_bit); - selected.is_1 = module->Mux(NEW_ID, selected.is_1, enc_b.is_1.extract(i * width, width), sel_bit); - selected.is_x = module->Mux(NEW_ID, selected.is_x, enc_b.is_x.extract(i * width, width), sel_bit); + selected.is_0 = module->Mux(NEWER_ID, selected.is_0, enc_b.is_0.extract(i * width, width), sel_bit); + selected.is_1 = module->Mux(NEWER_ID, selected.is_1, enc_b.is_1.extract(i * width, width), sel_bit); + selected.is_x = module->Mux(NEWER_ID, selected.is_x, enc_b.is_x.extract(i * width, width), sel_bit); } - enc_y.connect_0(module->Mux(NEW_ID, selected.is_0, Const(State::S0, width), all_x)); - enc_y.connect_1(module->Mux(NEW_ID, selected.is_1, Const(State::S0, width), all_x)); - enc_y.connect_x(module->Mux(NEW_ID, selected.is_x, Const(State::S1, width), all_x)); + enc_y.connect_0(module->Mux(NEWER_ID, selected.is_0, Const(State::S0, width), all_x)); + enc_y.connect_1(module->Mux(NEWER_ID, selected.is_1, Const(State::S0, width), all_x)); + enc_y.connect_x(module->Mux(NEWER_ID, selected.is_x, Const(State::S1, width), all_x)); module->remove(cell); return; @@ -776,12 +776,12 @@ struct XpropWorker auto enc_b = encoded(sig_b); auto enc_y = encoded(sig_y, true); - auto all_x = module->ReduceOr(NEW_ID, enc_b.is_x)[0]; - auto not_all_x = module->Not(NEW_ID, all_x)[0]; + auto all_x = module->ReduceOr(NEWER_ID, enc_b.is_x)[0]; + auto not_all_x = module->Not(NEWER_ID, all_x)[0]; - SigSpec y_not_0 = module->addWire(NEW_ID, GetSize(sig_y)); - SigSpec y_1 = module->addWire(NEW_ID, GetSize(sig_y)); - SigSpec y_x = module->addWire(NEW_ID, GetSize(sig_y)); + SigSpec y_not_0 = module->addWire(NEWER_ID, GetSize(sig_y)); + SigSpec y_1 = module->addWire(NEWER_ID, GetSize(sig_y)); + SigSpec y_x = module->addWire(NEWER_ID, GetSize(sig_y)); auto encoded_type = cell->type == ID($shiftx) ? ID($shift) : cell->type; @@ -789,32 +789,32 @@ struct XpropWorker std::swap(enc_a.is_0, enc_a.is_x); } - auto shift_0 = module->addCell(NEW_ID, encoded_type); + auto shift_0 = module->addCell(NEWER_ID, encoded_type); shift_0->parameters = cell->parameters; - shift_0->setPort(ID::A, module->Not(NEW_ID, enc_a.is_0)); + shift_0->setPort(ID::A, module->Not(NEWER_ID, enc_a.is_0)); shift_0->setPort(ID::B, enc_b.is_1); shift_0->setPort(ID::Y, y_not_0); - auto shift_1 = module->addCell(NEW_ID, encoded_type); + auto shift_1 = module->addCell(NEWER_ID, encoded_type); shift_1->parameters = cell->parameters; shift_1->setPort(ID::A, enc_a.is_1); shift_1->setPort(ID::B, enc_b.is_1); shift_1->setPort(ID::Y, y_1); - auto shift_x = module->addCell(NEW_ID, encoded_type); + auto shift_x = module->addCell(NEWER_ID, encoded_type); shift_x->parameters = cell->parameters; shift_x->setPort(ID::A, enc_a.is_x); shift_x->setPort(ID::B, enc_b.is_1); shift_x->setPort(ID::Y, y_x); - SigSpec y_0 = module->Not(NEW_ID, y_not_0); + SigSpec y_0 = module->Not(NEWER_ID, y_not_0); if (cell->type == ID($shiftx)) std::swap(y_0, y_x); - enc_y.connect_0(module->And(NEW_ID, y_0, SigSpec(not_all_x, GetSize(sig_y)))); - enc_y.connect_1(module->And(NEW_ID, y_1, SigSpec(not_all_x, GetSize(sig_y)))); - enc_y.connect_x(module->Or(NEW_ID, y_x, SigSpec(all_x, GetSize(sig_y)))); + enc_y.connect_0(module->And(NEWER_ID, y_0, SigSpec(not_all_x, GetSize(sig_y)))); + enc_y.connect_1(module->And(NEWER_ID, y_1, SigSpec(not_all_x, GetSize(sig_y)))); + enc_y.connect_x(module->Or(NEWER_ID, y_x, SigSpec(all_x, GetSize(sig_y)))); module->remove(cell); return; @@ -838,10 +838,10 @@ struct XpropWorker auto enc_d = encoded(sig_d); auto enc_q = encoded(sig_q, true); - auto data_q = module->addWire(NEW_ID, GetSize(sig_q)); + auto data_q = module->addWire(NEWER_ID, GetSize(sig_q)); - module->addFf(NEW_ID, enc_d.is_1, data_q); - module->addFf(NEW_ID, enc_d.is_x, enc_q.is_x); + module->addFf(NEWER_ID, enc_d.is_1, data_q); + module->addFf(NEWER_ID, enc_d.is_x, enc_q.is_x); initvals.set_init(data_q, init_q_is_1); initvals.set_init(enc_q.is_x, init_q_is_x); @@ -881,14 +881,14 @@ struct XpropWorker auto enc_d = encoded(ff.sig_d); auto enc_q = encoded(ff.sig_q, true); - auto data_q = module->addWire(NEW_ID, GetSize(ff.sig_q)); + auto data_q = module->addWire(NEWER_ID, GetSize(ff.sig_q)); ff.sig_d = enc_d.is_1; ff.sig_q = data_q; ff.val_init = init_q_is_1; ff.emit(); - ff.name = NEW_ID; + ff.name = NEWER_ID; ff.cell = nullptr; ff.sig_d = enc_d.is_x; ff.sig_q = enc_q.is_x; @@ -925,13 +925,13 @@ struct XpropWorker if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) { auto sig_b = cell->getPort(ID::B); - auto invalid = module->LogicNot(NEW_ID, sig_b); + auto invalid = module->LogicNot(NEWER_ID, sig_b); inbits_x.append(invalid); - sig_b[0] = module->Or(NEW_ID, sig_b[0], invalid); + sig_b[0] = module->Or(NEWER_ID, sig_b[0], invalid); cell->setPort(ID::B, sig_b); } - SigBit outbits_x = (GetSize(inbits_x) == 1 ? inbits_x : module->ReduceOr(NEW_ID, inbits_x)); + SigBit outbits_x = (GetSize(inbits_x) == 1 ? inbits_x : module->ReduceOr(NEWER_ID, inbits_x)); bool bool_out = cell->type.in(ID($le), ID($lt), ID($ge), ID($gt)); @@ -941,7 +941,7 @@ struct XpropWorker if (bool_out) enc_port.connect_as_bool(); - SigSpec new_output = module->addWire(NEW_ID, GetSize(conn.second)); + SigSpec new_output = module->addWire(NEWER_ID, GetSize(conn.second)); enc_port.connect_1_under_x(bool_out ? new_output.extract(0) : new_output); enc_port.connect_x(SigSpec(outbits_x, GetSize(enc_port))); @@ -999,7 +999,7 @@ struct XpropWorker if (options.split_public) { // Need to hide the original wire so split_public doesn't try to split it again - module->rename(wire, NEW_ID_SUFFIX(wire->name.c_str())); + module->rename(wire, NEWER_ID_SUFFIX(wire->name.c_str())); } } else { auto enc = encoded(wire, true); @@ -1052,7 +1052,7 @@ struct XpropWorker module->connect(wire_d, enc.is_1); module->connect(wire_x, enc.is_x); - module->rename(wire, NEW_ID_SUFFIX(wire->name.c_str())); + module->rename(wire, NEWER_ID_SUFFIX(wire->name.c_str())); } } @@ -1092,9 +1092,9 @@ struct XpropWorker it->second.driven = true; } - module->addBweqx(NEW_ID, orig, Const(State::S0, GetSize(orig)), enc.is_0); - module->addBweqx(NEW_ID, orig, Const(State::S1, GetSize(orig)), enc.is_1); - module->addBweqx(NEW_ID, orig, Const(State::Sx, GetSize(orig)), enc.is_x); + module->addBweqx(NEWER_ID, orig, Const(State::S0, GetSize(orig)), enc.is_0); + module->addBweqx(NEWER_ID, orig, Const(State::S1, GetSize(orig)), enc.is_1); + module->addBweqx(NEWER_ID, orig, Const(State::Sx, GetSize(orig)), enc.is_x); } } }; @@ -1230,7 +1230,7 @@ struct XpropPass : public Pass { continue; if (wire->port_input) { - module->addAssume(NEW_ID, module->Not(NEW_ID, module->ReduceOr(NEW_ID, module->Bweqx(NEW_ID, wire, Const(State::Sx, GetSize(wire))))), State::S1); + module->addAssume(NEWER_ID, module->Not(NEWER_ID, module->ReduceOr(NEWER_ID, module->Bweqx(NEWER_ID, wire, Const(State::Sx, GetSize(wire))))), State::S1); } } } diff --git a/passes/equiv/equiv_add.cc b/passes/equiv/equiv_add.cc index 1bcd4a88710..51dbf4985ab 100644 --- a/passes/equiv/equiv_add.cc +++ b/passes/equiv/equiv_add.cc @@ -84,10 +84,10 @@ struct EquivAddPass : public Pass { if (gold_cell->input(port) && gate_cell->input(port)) { - SigSpec combined_sig = module->addWire(NEW_ID, width); + SigSpec combined_sig = module->addWire(NEWER_ID, width); for (int i = 0; i < width; i++) { - module->addEquiv(NEW_ID, gold_sig[i], gate_sig[i], combined_sig[i]); + module->addEquiv(NEWER_ID, gold_sig[i], gate_sig[i], combined_sig[i]); gold_sig[i] = gate_sig[i] = combined_sig[i]; } @@ -98,12 +98,12 @@ struct EquivAddPass : public Pass { if (gold_cell->output(port) && gate_cell->output(port)) { - SigSpec new_gold_wire = module->addWire(NEW_ID, width); - SigSpec new_gate_wire = module->addWire(NEW_ID, width); + SigSpec new_gold_wire = module->addWire(NEWER_ID, width); + SigSpec new_gate_wire = module->addWire(NEWER_ID, width); SigSig gg_conn; for (int i = 0; i < width; i++) { - module->addEquiv(NEW_ID, new_gold_wire[i], new_gold_wire[i], gold_sig[i]); + module->addEquiv(NEWER_ID, new_gold_wire[i], new_gold_wire[i], gold_sig[i]); gg_conn.first.append(gate_sig[i]); gg_conn.second.append(gold_sig[i]); gold_sig[i] = new_gold_wire[i]; @@ -141,7 +141,7 @@ struct EquivAddPass : public Pass { } log_assert(GetSize(gold_signal) == GetSize(gate_signal)); - SigSpec equiv_signal = module->addWire(NEW_ID, GetSize(gold_signal)); + SigSpec equiv_signal = module->addWire(NEWER_ID, GetSize(gold_signal)); SigMap sigmap(module); sigmap.apply(gold_signal); @@ -151,7 +151,7 @@ struct EquivAddPass : public Pass { pool added_equiv_cells; for (int i = 0; i < GetSize(gold_signal); i++) { - Cell *equiv_cell = module->addEquiv(NEW_ID, gold_signal[i], gate_signal[i], equiv_signal[i]); + Cell *equiv_cell = module->addEquiv(NEWER_ID, gold_signal[i], gate_signal[i], equiv_signal[i]); equiv_cell->set_bool_attribute(ID::keep); to_equiv_bits[gold_signal[i]] = equiv_signal[i]; to_equiv_bits[gate_signal[i]] = equiv_signal[i]; diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc index e15e510be90..42667830e87 100644 --- a/passes/equiv/equiv_make.cc +++ b/passes/equiv/equiv_make.cc @@ -136,8 +136,8 @@ struct EquivMakeWorker void add_eq_assertion(const SigSpec &gold_sig, const SigSpec &gate_sig) { - auto eq_wire = equiv_mod->Eqx(NEW_ID, gold_sig, gate_sig); - equiv_mod->addAssert(NEW_ID_SUFFIX("assert"), eq_wire, State::S1); + auto eq_wire = equiv_mod->Eqx(NEWER_ID, gold_sig, gate_sig); + equiv_mod->addAssert(NEWER_ID_SUFFIX("assert"), eq_wire, State::S1); } void find_same_wires() @@ -205,11 +205,11 @@ struct EquivMakeWorker for (auto &bit : enc_result) if (bit != State::S1) bit = State::S0; - SigSpec dec_eq = equiv_mod->addWire(NEW_ID); - SigSpec enc_eq = equiv_mod->addWire(NEW_ID); + SigSpec dec_eq = equiv_mod->addWire(NEWER_ID); + SigSpec enc_eq = equiv_mod->addWire(NEWER_ID); - equiv_mod->addEq(NEW_ID, reduced_dec_sig, reduced_dec_pat, dec_eq); - cells_list.push_back(equiv_mod->addEq(NEW_ID, reduced_enc_sig, reduced_enc_pat, enc_eq)); + equiv_mod->addEq(NEWER_ID, reduced_dec_sig, reduced_dec_pat, dec_eq); + cells_list.push_back(equiv_mod->addEq(NEWER_ID, reduced_enc_sig, reduced_enc_pat, enc_eq)); dec_s.append(dec_eq); enc_s.append(enc_eq); @@ -217,8 +217,8 @@ struct EquivMakeWorker enc_b.append(enc_result); } - equiv_mod->addPmux(NEW_ID, dec_a, dec_b, dec_s, dec_wire); - equiv_mod->addPmux(NEW_ID, enc_a, enc_b, enc_s, enc_wire); + equiv_mod->addPmux(NEWER_ID, dec_a, dec_b, dec_s, dec_wire); + equiv_mod->addPmux(NEWER_ID, enc_a, enc_b, enc_s, enc_wire); rd_signal_map.add(assign_map(gate_wire), enc_wire); gate_wire = dec_wire; @@ -254,7 +254,7 @@ struct EquivMakeWorker else { for (int i = 0; i < wire->width; i++) - equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i)); + equiv_mod->addEquiv(NEWER_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i)); } rd_signal_map.add(assign_map(gold_wire), wire); @@ -291,7 +291,7 @@ struct EquivMakeWorker log(" Skipping signal bit %s [%d]: undriven on gate side.\n", id2cstr(gate_wire->name), i); continue; } - equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i)); + equiv_mod->addEquiv(NEWER_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i)); rdmap_gold.append(SigBit(gold_wire, i)); rdmap_gate.append(SigBit(gate_wire, i)); rdmap_equiv.append(SigBit(wire, i)); @@ -365,8 +365,8 @@ struct EquivMakeWorker { for (int i = 0; i < GetSize(gold_sig); i++) if (gold_sig[i] != gate_sig[i]) { - Wire *w = equiv_mod->addWire(NEW_ID); - equiv_mod->addEquiv(NEW_ID, gold_sig[i], gate_sig[i], w); + Wire *w = equiv_mod->addWire(NEWER_ID); + equiv_mod->addEquiv(NEWER_ID, gold_sig[i], gate_sig[i], w); gold_sig[i] = w; } } diff --git a/passes/equiv/equiv_miter.cc b/passes/equiv/equiv_miter.cc index 6acfe85a972..e20f3c88494 100644 --- a/passes/equiv/equiv_miter.cc +++ b/passes/equiv/equiv_miter.cc @@ -219,9 +219,9 @@ struct EquivMiterWorker for (auto c : equiv_cells) { SigSpec cmp = mode_undef ? - miter_module->LogicOr(NEW_ID, miter_module->Eqx(NEW_ID, c->getPort(ID::A), State::Sx), - miter_module->Eqx(NEW_ID, c->getPort(ID::A), c->getPort(ID::B))) : - miter_module->Eq(NEW_ID, c->getPort(ID::A), c->getPort(ID::B)); + miter_module->LogicOr(NEWER_ID, miter_module->Eqx(NEWER_ID, c->getPort(ID::A), State::Sx), + miter_module->Eqx(NEWER_ID, c->getPort(ID::A), c->getPort(ID::B))) : + miter_module->Eq(NEWER_ID, c->getPort(ID::A), c->getPort(ID::B)); if (mode_cmp) { string cmp_name = stringf("\\cmp%s", log_signal(c->getPort(ID::Y))); @@ -236,15 +236,15 @@ struct EquivMiterWorker } if (mode_assert) - miter_module->addAssert(NEW_ID, cmp, State::S1); + miter_module->addAssert(NEWER_ID, cmp, State::S1); - trigger_signals.append(miter_module->Not(NEW_ID, cmp)); + trigger_signals.append(miter_module->Not(NEWER_ID, cmp)); } if (mode_trigger) { auto w = miter_module->addWire(ID(trigger)); w->port_output = true; - miter_module->addReduceOr(NEW_ID, trigger_signals, w); + miter_module->addReduceOr(NEWER_ID, trigger_signals, w); } miter_module->fixup_ports(); diff --git a/passes/equiv/equiv_purge.cc b/passes/equiv/equiv_purge.cc index 5b0696d9ba4..f62bafd3f9b 100644 --- a/passes/equiv/equiv_purge.cc +++ b/passes/equiv/equiv_purge.cc @@ -67,7 +67,7 @@ struct EquivPurgeWorker log(" Module input: %s\n", log_signal(wire)); wire->port_input = true; } - return module->addWire(NEW_ID, GetSize(sig)); + return module->addWire(NEWER_ID, GetSize(sig)); } } @@ -81,7 +81,7 @@ struct EquivPurgeWorker wire->port_input = true; module->connect(sig, wire); log(" Module input: %s (%s)\n", log_signal(wire), log_signal(sig)); - return module->addWire(NEW_ID, GetSize(sig)); + return module->addWire(NEWER_ID, GetSize(sig)); } } diff --git a/passes/equiv/equiv_struct.cc b/passes/equiv/equiv_struct.cc index 411f0dd5c6e..d7b075448e5 100644 --- a/passes/equiv/equiv_struct.cc +++ b/passes/equiv/equiv_struct.cc @@ -85,10 +85,10 @@ struct EquivStructWorker for (int i = 0; i < GetSize(inputs_a); i++) { SigBit bit_a = inputs_a[i], bit_b = inputs_b[i]; - SigBit bit_y = module->addWire(NEW_ID); + SigBit bit_y = module->addWire(NEWER_ID); log(" New $equiv for input %s: A: %s, B: %s, Y: %s\n", input_names[i].c_str(), log_signal(bit_a), log_signal(bit_b), log_signal(bit_y)); - module->addEquiv(NEW_ID, bit_a, bit_b, bit_y); + module->addEquiv(NEWER_ID, bit_a, bit_b, bit_y); merged_map.add(bit_a, bit_y); merged_map.add(bit_b, bit_y); } diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index c19edcc889e..ae3aaba6501 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -71,10 +71,10 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map 0) { - RTLIL::Wire *eq_wire = module->addWire(NEW_ID); + RTLIL::Wire *eq_wire = module->addWire(NEWER_ID); and_sig.append(RTLIL::SigSpec(eq_wire)); - RTLIL::Cell *eq_cell = module->addCell(NEW_ID, ID($eq)); + RTLIL::Cell *eq_cell = module->addCell(NEWER_ID, ID($eq)); eq_cell->setPort(ID::A, eq_sig_a); eq_cell->setPort(ID::B, eq_sig_b); eq_cell->setPort(ID::Y, RTLIL::SigSpec(eq_wire)); @@ -99,10 +99,10 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapaddWire(NEW_ID); + RTLIL::Wire *or_wire = module->addWire(NEWER_ID); and_sig.append(RTLIL::SigSpec(or_wire)); - RTLIL::Cell *or_cell = module->addCell(NEW_ID, ID($reduce_or)); + RTLIL::Cell *or_cell = module->addCell(NEWER_ID, ID($reduce_or)); or_cell->setPort(ID::A, or_sig); or_cell->setPort(ID::Y, RTLIL::SigSpec(or_wire)); or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false); @@ -115,10 +115,10 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapaddWire(NEW_ID); + RTLIL::Wire *and_wire = module->addWire(NEWER_ID); cases_vector.append(RTLIL::SigSpec(and_wire)); - RTLIL::Cell *and_cell = module->addCell(NEW_ID, ID($and)); + RTLIL::Cell *and_cell = module->addCell(NEWER_ID, ID($and)); and_cell->setPort(ID::A, and_sig.extract(0, 1)); and_cell->setPort(ID::B, and_sig.extract(1, 1)); and_cell->setPort(ID::Y, RTLIL::SigSpec(and_wire)); @@ -141,7 +141,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map 1) { - RTLIL::Cell *or_cell = module->addCell(NEW_ID, ID($reduce_or)); + RTLIL::Cell *or_cell = module->addCell(NEWER_ID, ID($reduce_or)); or_cell->setPort(ID::A, cases_vector); or_cell->setPort(ID::Y, output); or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false); @@ -167,9 +167,9 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) // create state register RTLIL::Wire *state_wire = module->addWire(module->uniquify(fsm_cell->parameters[ID::NAME].decode_string()), fsm_data.state_bits); - RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits); + RTLIL::Wire *next_state_wire = module->addWire(NEWER_ID, fsm_data.state_bits); - RTLIL::Cell *state_dff = module->addCell(NEW_ID, ""); + RTLIL::Cell *state_dff = module->addCell(NEWER_ID, ""); if (fsm_cell->getPort(ID::ARST).is_fully_const()) { state_dff->type = ID($dff); } else { @@ -191,7 +191,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) bool encoding_is_onehot = true; - RTLIL::Wire *state_onehot = module->addWire(NEW_ID, fsm_data.state_table.size()); + RTLIL::Wire *state_onehot = module->addWire(NEWER_ID, fsm_data.state_table.size()); for (size_t i = 0; i < fsm_data.state_table.size(); i++) { @@ -212,7 +212,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) { encoding_is_onehot = false; - RTLIL::Cell *eq_cell = module->addCell(NEW_ID, ID($eq)); + RTLIL::Cell *eq_cell = module->addCell(NEWER_ID, ID($eq)); eq_cell->setPort(ID::A, sig_a); eq_cell->setPort(ID::B, sig_b); eq_cell->setPort(ID::Y, RTLIL::SigSpec(state_onehot, i)); @@ -235,7 +235,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) } else { - RTLIL::Wire *next_state_onehot = module->addWire(NEW_ID, fsm_data.state_table.size()); + RTLIL::Wire *next_state_onehot = module->addWire(NEWER_ID, fsm_data.state_table.size()); for (size_t i = 0; i < fsm_data.state_table.size(); i++) { @@ -285,7 +285,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) } } - RTLIL::Cell *mux_cell = module->addCell(NEW_ID, ID($pmux)); + RTLIL::Cell *mux_cell = module->addCell(NEWER_ID, ID($pmux)); mux_cell->setPort(ID::A, sig_a); mux_cell->setPort(ID::B, sig_b); mux_cell->setPort(ID::S, sig_s); diff --git a/passes/hierarchy/flatten.cc b/passes/hierarchy/flatten.cc index 17bd6e3404f..6e291327a6f 100644 --- a/passes/hierarchy/flatten.cc +++ b/passes/hierarchy/flatten.cc @@ -273,7 +273,7 @@ struct FlattenWorker if (create_scopeinfo && cell_name.isPublic()) { // The $scopeinfo's name will be changed below after removing the flattened cell - scopeinfo = module->addCell(NEW_ID, ID($scopeinfo)); + scopeinfo = module->addCell(NEWER_ID, ID($scopeinfo)); scopeinfo->setParam(ID::TYPE, RTLIL::Const("module")); for (auto const &attr : cell->attributes) diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 6fec628c237..bab34050bb0 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -1370,7 +1370,7 @@ struct HierarchyPass : public Pass { continue; } - Wire *t = module->addWire(NEW_ID, GetSize(c)); + Wire *t = module->addWire(NEWER_ID, GetSize(c)); new_sig.append(t); update_port = true; @@ -1400,18 +1400,18 @@ struct HierarchyPass : public Pass { if (GetSize(w) == 1) { if (wand) - module->addReduceAnd(NEW_ID, sigs, w); + module->addReduceAnd(NEWER_ID, sigs, w); else - module->addReduceOr(NEW_ID, sigs, w); + module->addReduceOr(NEWER_ID, sigs, w); continue; } SigSpec s = sigs.extract(0, GetSize(w)); for (int i = GetSize(w); i < GetSize(sigs); i += GetSize(w)) { if (wand) - s = module->And(NEW_ID, s, sigs.extract(i, GetSize(w))); + s = module->And(NEWER_ID, s, sigs.extract(i, GetSize(w))); else - s = module->Or(NEW_ID, s, sigs.extract(i, GetSize(w))); + s = module->Or(NEWER_ID, s, sigs.extract(i, GetSize(w))); } module->connect(w, s); } @@ -1473,7 +1473,7 @@ struct HierarchyPass : public Pass { if (w->port_input && !w->port_output) sig.extend_u0(GetSize(w), sig.is_wire() && sig.as_wire()->is_signed); else - sig.append(module->addWire(NEW_ID, n)); + sig.append(module->addWire(NEWER_ID, n)); } if (!conn.second.is_fully_const() || !w->port_input || w->port_output) diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 486d21920d4..4f81ad0edb6 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -232,10 +232,10 @@ struct SubmodWorker auto &b = old_sig[i]; // Prevents "ERROR: Mismatch in directionality ..." when flattening if (!b.wire) - b = module->addWire(NEW_ID); + b = module->addWire(NEWER_ID); // Prevents "Warning: multiple conflicting drivers ..." else if (!it.second.is_int_driven[i]) - b = module->addWire(NEW_ID); + b = module->addWire(NEWER_ID); } new_cell->setPort(new_wire->name, old_sig); } diff --git a/passes/memory/memory_bmux2rom.cc b/passes/memory/memory_bmux2rom.cc index a3fc5a7fc59..8e63a5be9d9 100644 --- a/passes/memory/memory_bmux2rom.cc +++ b/passes/memory/memory_bmux2rom.cc @@ -60,7 +60,7 @@ struct MemoryBmux2RomPass : public Pass { continue; // Ok, let's do it. - Mem mem(module, NEW_ID, width, 0, 1 << abits); + Mem mem(module, NEWER_ID, width, 0, 1 << abits); mem.attributes = cell->attributes; MemInit init; diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 10301b44ab2..118de04a8c9 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -841,7 +841,7 @@ grow_read_ports:; // Swizzle read ports. for (auto &port : mem.rd_ports) { - SigSpec new_data = module->addWire(NEW_ID, mem.width); + SigSpec new_data = module->addWire(NEWER_ID, mem.width); Const new_init_value = Const(State::Sx, mem.width); Const new_arst_value = Const(State::Sx, mem.width); Const new_srst_value = Const(State::Sx, mem.width); @@ -920,7 +920,7 @@ grow_read_ports:; if (GetSize(sig_addr) > bram.abits) { SigSpec extra_addr = sig_addr.extract(bram.abits, GetSize(sig_addr) - bram.abits); SigSpec extra_addr_sel = SigSpec(grid_a, GetSize(extra_addr)); - addr_ok = module->Eq(NEW_ID, extra_addr, extra_addr_sel); + addr_ok = module->Eq(NEWER_ID, extra_addr, extra_addr_sel); } sig_addr.extend_u0(bram.abits); @@ -946,7 +946,7 @@ grow_read_ports:; sig_en.append(port.en[stride * i + grid_d * bram.dbits]); if (!addr_ok.empty()) - sig_en = module->Mux(NEW_ID, SigSpec(0, GetSize(sig_en)), sig_en, addr_ok); + sig_en = module->Mux(NEWER_ID, SigSpec(0, GetSize(sig_en)), sig_en, addr_ok); c->setPort(stringf("\\%sEN", pf), sig_en); @@ -961,13 +961,13 @@ grow_read_ports:; auto &port = mem.rd_ports[pi.mapped_port]; SigSpec sig_data = port.data.extract(grid_d * bram.dbits, bram.dbits); - SigSpec bram_dout = module->addWire(NEW_ID, bram.dbits); + SigSpec bram_dout = module->addWire(NEWER_ID, bram.dbits); c->setPort(stringf("\\%sDATA", pf), bram_dout); SigSpec addr_ok_q = addr_ok; if (port.clk_enable && !addr_ok.empty()) { - addr_ok_q = module->addWire(NEW_ID); - module->addDffe(NEW_ID, port.clk, port.en, addr_ok, addr_ok_q, port.clk_polarity); + addr_ok_q = module->addWire(NEWER_ID); + module->addDffe(NEWER_ID, port.clk, port.en, addr_ok, addr_ok_q, port.clk_polarity); } dout_cache[sig_data].first.append(addr_ok_q); @@ -976,7 +976,7 @@ grow_read_ports:; if (pi.enable) { SigSpec sig_en = port.en; if (!addr_ok.empty()) - sig_en = module->And(NEW_ID, sig_en, addr_ok); + sig_en = module->And(NEWER_ID, sig_en, addr_ok); c->setPort(stringf("\\%sEN", pf), sig_en); } } @@ -994,7 +994,7 @@ grow_read_ports:; else { log_assert(GetSize(it.first)*GetSize(it.second.first) == GetSize(it.second.second)); - module->addPmux(NEW_ID, SigSpec(State::Sx, GetSize(it.first)), it.second.second, it.second.first, it.first); + module->addPmux(NEWER_ID, SigSpec(State::Sx, GetSize(it.first)), it.second.second, it.second.first, it.first); } } diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 916b21233a6..6a9f3bac9b8 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -507,11 +507,11 @@ struct MemoryDffWorker merger.remove_output_ff(bits); if (ff.has_ce && !ff.pol_ce) - ff.sig_ce = module->LogicNot(NEW_ID, ff.sig_ce); + ff.sig_ce = module->LogicNot(NEWER_ID, ff.sig_ce); if (ff.has_arst && !ff.pol_arst) - ff.sig_arst = module->LogicNot(NEW_ID, ff.sig_arst); + ff.sig_arst = module->LogicNot(NEWER_ID, ff.sig_arst); if (ff.has_srst && !ff.pol_srst) - ff.sig_srst = module->LogicNot(NEW_ID, ff.sig_srst); + ff.sig_srst = module->LogicNot(NEWER_ID, ff.sig_srst); port.clk = ff.sig_clk; port.clk_enable = true; port.clk_polarity = ff.pol_clk; diff --git a/passes/memory/memory_libmap.cc b/passes/memory/memory_libmap.cc index 0fb4608b17f..8b48491c403 100644 --- a/passes/memory/memory_libmap.cc +++ b/passes/memory/memory_libmap.cc @@ -1625,8 +1625,8 @@ std::vector generate_demux(Mem &mem, int wpidx, const Swizzle &swz) { lo = new_lo; hi = new_hi; } - SigSpec in_range = mem.module->And(NEW_ID, mem.module->Ge(NEW_ID, addr, lo), mem.module->Lt(NEW_ID, addr, hi)); - sig_a = mem.module->Mux(NEW_ID, Const(State::S0, GetSize(sig_a)), sig_a, in_range); + SigSpec in_range = mem.module->And(NEWER_ID, mem.module->Ge(NEWER_ID, addr, lo), mem.module->Lt(NEWER_ID, addr, hi)); + sig_a = mem.module->Mux(NEWER_ID, Const(State::S0, GetSize(sig_a)), sig_a, in_range); } addr.extend_u0(swz.addr_shift + hi_bits, false); SigSpec sig_s; @@ -1638,7 +1638,7 @@ std::vector generate_demux(Mem &mem, int wpidx, const Swizzle &swz) { if (GetSize(sig_s) == 0) sig_y = sig_a; else - sig_y = mem.module->Demux(NEW_ID, sig_a, sig_s); + sig_y = mem.module->Demux(NEWER_ID, sig_a, sig_s); for (int i = 0; i < ((swz.addr_end - swz.addr_start) >> swz.addr_shift); i++) { for (int j = 0; j < (1 << GetSize(swz.addr_mux_bits)); j++) { int hi = ((swz.addr_start >> swz.addr_shift) + i) & ((1 << hi_bits) - 1); @@ -1664,14 +1664,14 @@ std::vector generate_mux(Mem &mem, int rpidx, const Swizzle &swz) { return {port.data}; } if (port.clk_enable) { - SigSpec new_sig_s = mem.module->addWire(NEW_ID, GetSize(sig_s)); - mem.module->addDffe(NEW_ID, port.clk, port.en, sig_s, new_sig_s, port.clk_polarity); + SigSpec new_sig_s = mem.module->addWire(NEWER_ID, GetSize(sig_s)); + mem.module->addDffe(NEWER_ID, port.clk, port.en, sig_s, new_sig_s, port.clk_polarity); sig_s = new_sig_s; } SigSpec sig_a = Const(State::Sx, GetSize(port.data) << hi_bits << GetSize(swz.addr_mux_bits)); for (int i = 0; i < ((swz.addr_end - swz.addr_start) >> swz.addr_shift); i++) { for (int j = 0; j < (1 << GetSize(swz.addr_mux_bits)); j++) { - SigSpec sig = mem.module->addWire(NEW_ID, GetSize(port.data)); + SigSpec sig = mem.module->addWire(NEWER_ID, GetSize(port.data)); int hi = ((swz.addr_start >> swz.addr_shift) + i) & ((1 << hi_bits) - 1); int pos = (hi << GetSize(swz.addr_mux_bits) | j) * GetSize(port.data); for (int k = 0; k < GetSize(port.data); k++) @@ -1679,7 +1679,7 @@ std::vector generate_mux(Mem &mem, int rpidx, const Swizzle &swz) { res.push_back(sig); } } - mem.module->addBmux(NEW_ID, sig_a, sig_s, port.data); + mem.module->addBmux(NEWER_ID, sig_a, sig_s, port.data); return res; } @@ -1709,7 +1709,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector &cells, cons if (pdef.clk_en) { if (rpcfg.rd_en_to_clk_en) { if (pdef.rdwr == RdWrKind::NoChange) { - clk_en = mem.module->Or(NEW_ID, rport.en, mem.module->ReduceOr(NEW_ID, wport.en)); + clk_en = mem.module->Or(NEWER_ID, rport.en, mem.module->ReduceOr(NEWER_ID, wport.en)); } else { clk_en = rport.en; } @@ -1743,11 +1743,11 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector &cells, cons switch (pdef.clk_pol) { case ClkPolKind::Posedge: if (!clk_pol) - clk = mem.module->Not(NEW_ID, clk); + clk = mem.module->Not(NEWER_ID, clk); break; case ClkPolKind::Negedge: if (clk_pol) - clk = mem.module->Not(NEW_ID, clk); + clk = mem.module->Not(NEWER_ID, clk); break; case ClkPolKind::Anyedge: for (auto cell: cells) @@ -1852,7 +1852,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector &cells, cons cell->setPort(stringf("\\PORT_%s_WR_DATA", name), hw_wdata); if (pdef.wrbe_separate) { // TODO make some use of it - SigSpec en = mem.module->ReduceOr(NEW_ID, hw_wren); + SigSpec en = mem.module->ReduceOr(NEWER_ID, hw_wren); cell->setPort(stringf("\\PORT_%s_WR_EN", name), en); cell->setPort(stringf("\\PORT_%s_WR_BE", name), hw_wren); if (cfg.def->width_mode != WidthMode::Single) @@ -1947,7 +1947,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector &cells, cons cell->setParam(stringf("\\PORT_%s_RD_SRST_VALUE", name), hw_val); } } - SigSpec hw_rdata = mem.module->addWire(NEW_ID, width); + SigSpec hw_rdata = mem.module->addWire(NEWER_ID, width); cell->setPort(stringf("\\PORT_%s_RD_DATA", name), hw_rdata); SigSpec lhs; SigSpec rhs; @@ -1982,7 +1982,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector &cells, cons else if (pdef.rdsrstval == ResetValKind::NoUndef) cell->setParam(stringf("\\PORT_%s_RD_SRST_VALUE", name), Const(State::S0, width)); } - SigSpec hw_rdata = mem.module->addWire(NEW_ID, width); + SigSpec hw_rdata = mem.module->addWire(NEWER_ID, width); cell->setPort(stringf("\\PORT_%s_RD_DATA", name), hw_rdata); } } @@ -2087,7 +2087,7 @@ void MemMapping::emit(const MemConfig &cfg) { } else { SigSpec sig = ccfg.used ? ccfg.clk : State::S0; if (ccfg.used && ccfg.invert) - sig = mem.module->Not(NEW_ID, sig); + sig = mem.module->Not(NEWER_ID, sig); cell->setPort(stringf("\\CLK_%s", cdef.name), sig); } } diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index cc8dce13e88..76f94651265 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -89,12 +89,12 @@ struct MemoryMapWorker if (decoder_cache.count(key) == 0) { if (GetSize(addr_sig) < 2) { - decoder_cache[key] = module->Eq(NEW_ID, addr_sig, addr_val); + decoder_cache[key] = module->Eq(NEWER_ID, addr_sig, addr_val); } else { int split_at = GetSize(addr_sig) / 2; RTLIL::SigBit left_eq = addr_decode(addr_sig.extract(0, split_at), addr_val.extract(0, split_at)); RTLIL::SigBit right_eq = addr_decode(addr_sig.extract(split_at, GetSize(addr_sig) - split_at), addr_val.extract(split_at, GetSize(addr_val) - split_at)); - decoder_cache[key] = module->And(NEW_ID, left_eq, right_eq); + decoder_cache[key] = module->And(NEWER_ID, left_eq, right_eq); } } diff --git a/passes/memory/memory_memx.cc b/passes/memory/memory_memx.cc index 22aebb43f1b..5b98ec017ae 100644 --- a/passes/memory/memory_memx.cc +++ b/passes/memory/memory_memx.cc @@ -42,10 +42,10 @@ struct MemoryMemxPass : public Pass { addr.extend_u0(32); - SigSpec res = mem.module->Nex(NEW_ID, mem.module->ReduceXor(NEW_ID, addr), mem.module->ReduceXor(NEW_ID, {addr, State::S1})); + SigSpec res = mem.module->Nex(NEWER_ID, mem.module->ReduceXor(NEWER_ID, addr), mem.module->ReduceXor(NEWER_ID, {addr, State::S1})); if (start_addr != 0) - res = mem.module->LogicAnd(NEW_ID, res, mem.module->Ge(NEW_ID, addr, start_addr)); - res = mem.module->LogicAnd(NEW_ID, res, mem.module->Lt(NEW_ID, addr, end_addr)); + res = mem.module->LogicAnd(NEWER_ID, res, mem.module->Ge(NEWER_ID, addr, start_addr)); + res = mem.module->LogicAnd(NEWER_ID, res, mem.module->Lt(NEWER_ID, addr, end_addr)); return res; } @@ -63,14 +63,14 @@ struct MemoryMemxPass : public Pass { log_id(module), log_id(mem.memid)); SigSpec addr_ok = make_addr_check(mem, port.addr); - Wire *raw_rdata = module->addWire(NEW_ID, GetSize(port.data)); - module->addMux(NEW_ID, SigSpec(State::Sx, GetSize(port.data)), raw_rdata, addr_ok, port.data); + Wire *raw_rdata = module->addWire(NEWER_ID, GetSize(port.data)); + module->addMux(NEWER_ID, SigSpec(State::Sx, GetSize(port.data)), raw_rdata, addr_ok, port.data); port.data = raw_rdata; } for (auto &port : mem.wr_ports) { SigSpec addr_ok = make_addr_check(mem, port.addr); - port.en = module->And(NEW_ID, port.en, addr_ok.repeat(GetSize(port.en))); + port.en = module->And(NEWER_ID, port.en, addr_ok.repeat(GetSize(port.en))); } mem.emit(); diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index fe884772a80..66d36a4d23b 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -164,7 +164,7 @@ struct MemoryShareWorker port2.addr = addr2; mem.prepare_rd_merge(i, j, &initvals); mem.widen_prep(wide_log2); - SigSpec new_data = module->addWire(NEW_ID, mem.width << wide_log2); + SigSpec new_data = module->addWire(NEWER_ID, mem.width << wide_log2); module->connect(port1.data, new_data.extract(sub1 * mem.width, mem.width << port1.wide_log2)); module->connect(port2.data, new_data.extract(sub2 * mem.width, mem.width << port2.wide_log2)); for (int k = 0; k < wide_log2; k++) @@ -271,8 +271,8 @@ struct MemoryShareWorker port1.data.replace(pos, port2.data.extract(pos, width)); new_en = port2.en[pos]; } else { - port1.data.replace(pos, module->Mux(NEW_ID, port1.data.extract(pos, width), port2.data.extract(pos, width), port2.en[pos])); - new_en = module->Or(NEW_ID, port1.en[pos], port2.en[pos]); + port1.data.replace(pos, module->Mux(NEWER_ID, port1.data.extract(pos, width), port2.data.extract(pos, width), port2.en[pos])); + new_en = module->Or(NEWER_ID, port1.en[pos], port2.en[pos]); } for (int k = pos; k < epos; k++) port1.en[k] = new_en; @@ -424,21 +424,21 @@ struct MemoryShareWorker RTLIL::SigSpec this_data = port2.data; std::vector this_en = modwalker.sigmap(port2.en); - RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en); + RTLIL::SigBit this_en_active = module->ReduceOr(NEWER_ID, this_en); if (GetSize(last_addr) < GetSize(this_addr)) last_addr.extend_u0(GetSize(this_addr)); else this_addr.extend_u0(GetSize(last_addr)); - SigSpec new_addr = module->Mux(NEW_ID, last_addr.extract_end(port1.wide_log2), this_addr.extract_end(port1.wide_log2), this_en_active); + SigSpec new_addr = module->Mux(NEWER_ID, last_addr.extract_end(port1.wide_log2), this_addr.extract_end(port1.wide_log2), this_en_active); port1.addr = SigSpec({new_addr, port1.addr.extract(0, port1.wide_log2)}); - port1.data = module->Mux(NEW_ID, last_data, this_data, this_en_active); + port1.data = module->Mux(NEWER_ID, last_data, this_data, this_en_active); std::map, int> groups_en; RTLIL::SigSpec grouped_last_en, grouped_this_en, en; - RTLIL::Wire *grouped_en = module->addWire(NEW_ID, 0); + RTLIL::Wire *grouped_en = module->addWire(NEWER_ID, 0); for (int j = 0; j < int(this_en.size()); j++) { std::pair key(last_en[j], this_en[j]); @@ -451,7 +451,7 @@ struct MemoryShareWorker en.append(RTLIL::SigSpec(grouped_en, groups_en[key])); } - module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en); + module->addMux(NEWER_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en); port1.en = en; port2.removed = true; diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc index 6efeefb3c16..6570a82cf72 100644 --- a/passes/opt/muxpack.cc +++ b/passes/opt/muxpack.cc @@ -283,7 +283,7 @@ struct MuxpackWorker else { log_assert(cursor_cell->type == ID($mux)); b_sig.append(cursor_cell->getPort(ID::A)); - s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort(ID::S))); + s_sig.append(module->LogicNot(NEWER_ID, cursor_cell->getPort(ID::S))); } remove_cells.insert(cursor_cell); } diff --git a/passes/opt/opt_demorgan.cc b/passes/opt/opt_demorgan.cc index 1a2c1fe8265..0c09d4cb7d9 100644 --- a/passes/opt/opt_demorgan.cc +++ b/passes/opt/opt_demorgan.cc @@ -99,8 +99,8 @@ void demorgan_worker( //We are NOT inverted! Add an inverter if(!srcinv) { - auto inverted_b = m->addWire(NEW_ID); - m->addNot(NEW_ID, RTLIL::SigSpec(b), RTLIL::SigSpec(inverted_b)); + auto inverted_b = m->addWire(NEWER_ID); + m->addNot(NEWER_ID, RTLIL::SigSpec(b), RTLIL::SigSpec(inverted_b)); insig[i] = inverted_b; } @@ -166,8 +166,8 @@ void demorgan_worker( //Add an inverter to the output auto inverted_output = cell->getPort(ID::Y); - auto uninverted_output = m->addWire(NEW_ID); - m->addNot(NEW_ID, RTLIL::SigSpec(uninverted_output), inverted_output); + auto uninverted_output = m->addWire(NEWER_ID); + m->addNot(NEWER_ID, RTLIL::SigSpec(uninverted_output), inverted_output); cell->setPort(ID::Y, uninverted_output); } diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index a364539e492..9bf550a1cf5 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -244,8 +244,8 @@ struct OptDffWorker s2.append(it.second); } - RTLIL::SigSpec y = module->addWire(NEW_ID); - RTLIL::Cell *c = module->addNe(NEW_ID, s1, s2, y); + RTLIL::SigSpec y = module->addWire(NEWER_ID); + RTLIL::Cell *c = module->addNe(NEWER_ID, s1, s2, y); if (make_gates) { simplemap(module, c); @@ -258,9 +258,9 @@ struct OptDffWorker if (item.second) or_input.append(item.first); else if (make_gates) - or_input.append(module->NotGate(NEW_ID, item.first)); + or_input.append(module->NotGate(NEWER_ID, item.first)); else - or_input.append(module->Not(NEW_ID, item.first)); + or_input.append(module->Not(NEWER_ID, item.first)); } if (GetSize(or_input) == 0) @@ -269,8 +269,8 @@ struct OptDffWorker if (GetSize(or_input) == 1) return ctrl_t(or_input, true); - RTLIL::SigSpec y = module->addWire(NEW_ID); - RTLIL::Cell *c = module->addReduceAnd(NEW_ID, or_input, y); + RTLIL::SigSpec y = module->addWire(NEWER_ID); + RTLIL::Cell *c = module->addReduceAnd(NEWER_ID, or_input, y); if (make_gates) { simplemap(module, c); @@ -298,13 +298,13 @@ struct OptDffWorker if (item.second == final_pol) or_input.append(item.first); else if (make_gates) - or_input.append(module->NotGate(NEW_ID, item.first)); + or_input.append(module->NotGate(NEWER_ID, item.first)); else - or_input.append(module->Not(NEW_ID, item.first)); + or_input.append(module->Not(NEWER_ID, item.first)); } - RTLIL::SigSpec y = module->addWire(NEW_ID); - RTLIL::Cell *c = final_pol ? module->addReduceOr(NEW_ID, or_input, y) : module->addReduceAnd(NEW_ID, or_input, y); + RTLIL::SigSpec y = module->addWire(NEWER_ID); + RTLIL::Cell *c = final_pol ? module->addReduceOr(NEWER_ID, or_input, y) : module->addReduceAnd(NEWER_ID, or_input, y); if (make_gates) { simplemap(module, c); @@ -348,9 +348,9 @@ struct OptDffWorker if (!ff.pol_clr) { module->connect(ff.sig_q[i], ff.sig_clr[i]); } else if (ff.is_fine) { - module->addNotGate(NEW_ID, ff.sig_clr[i], ff.sig_q[i]); + module->addNotGate(NEWER_ID, ff.sig_clr[i], ff.sig_q[i]); } else { - module->addNot(NEW_ID, ff.sig_clr[i], ff.sig_q[i]); + module->addNot(NEWER_ID, ff.sig_clr[i], ff.sig_q[i]); } log("Handling always-active SET at position %d on %s (%s) from module %s (changing to combinatorial circuit).\n", i, log_id(cell), log_id(cell->type), log_id(module)); @@ -451,34 +451,34 @@ struct OptDffWorker SigSpec tmp; if (ff.is_fine) { if (ff.pol_set) - tmp = module->MuxGate(NEW_ID, ff.sig_ad, State::S1, ff.sig_set); + tmp = module->MuxGate(NEWER_ID, ff.sig_ad, State::S1, ff.sig_set); else - tmp = module->MuxGate(NEW_ID, State::S1, ff.sig_ad, ff.sig_set); + tmp = module->MuxGate(NEWER_ID, State::S1, ff.sig_ad, ff.sig_set); if (ff.pol_clr) - module->addMuxGate(NEW_ID, tmp, State::S0, ff.sig_clr, ff.sig_q); + module->addMuxGate(NEWER_ID, tmp, State::S0, ff.sig_clr, ff.sig_q); else - module->addMuxGate(NEW_ID, State::S0, tmp, ff.sig_clr, ff.sig_q); + module->addMuxGate(NEWER_ID, State::S0, tmp, ff.sig_clr, ff.sig_q); } else { if (ff.pol_set) - tmp = module->Or(NEW_ID, ff.sig_ad, ff.sig_set); + tmp = module->Or(NEWER_ID, ff.sig_ad, ff.sig_set); else - tmp = module->Or(NEW_ID, ff.sig_ad, module->Not(NEW_ID, ff.sig_set)); + tmp = module->Or(NEWER_ID, ff.sig_ad, module->Not(NEWER_ID, ff.sig_set)); if (ff.pol_clr) - module->addAnd(NEW_ID, tmp, module->Not(NEW_ID, ff.sig_clr), ff.sig_q); + module->addAnd(NEWER_ID, tmp, module->Not(NEWER_ID, ff.sig_clr), ff.sig_q); else - module->addAnd(NEW_ID, tmp, ff.sig_clr, ff.sig_q); + module->addAnd(NEWER_ID, tmp, ff.sig_clr, ff.sig_q); } } else if (ff.has_arst) { if (ff.is_fine) { if (ff.pol_arst) - module->addMuxGate(NEW_ID, ff.sig_ad, ff.val_arst[0], ff.sig_arst, ff.sig_q); + module->addMuxGate(NEWER_ID, ff.sig_ad, ff.val_arst[0], ff.sig_arst, ff.sig_q); else - module->addMuxGate(NEW_ID, ff.val_arst[0], ff.sig_ad, ff.sig_arst, ff.sig_q); + module->addMuxGate(NEWER_ID, ff.val_arst[0], ff.sig_ad, ff.sig_arst, ff.sig_q); } else { if (ff.pol_arst) - module->addMux(NEW_ID, ff.sig_ad, ff.val_arst, ff.sig_arst, ff.sig_q); + module->addMux(NEWER_ID, ff.sig_ad, ff.val_arst, ff.sig_arst, ff.sig_q); else - module->addMux(NEW_ID, ff.val_arst, ff.sig_ad, ff.sig_arst, ff.sig_q); + module->addMux(NEWER_ID, ff.val_arst, ff.sig_ad, ff.sig_arst, ff.sig_q); } } else { module->connect(ff.sig_q, ff.sig_ad); @@ -594,20 +594,20 @@ struct OptDffWorker if (ff.has_ce && ff.ce_over_srst) { if (!ff.pol_ce) { if (ff.is_fine) - ff.sig_ce = module->NotGate(NEW_ID, ff.sig_ce); + ff.sig_ce = module->NotGate(NEWER_ID, ff.sig_ce); else - ff.sig_ce = module->Not(NEW_ID, ff.sig_ce); + ff.sig_ce = module->Not(NEWER_ID, ff.sig_ce); } if (!ff.pol_srst) { if (ff.is_fine) - ff.sig_srst = module->NotGate(NEW_ID, ff.sig_srst); + ff.sig_srst = module->NotGate(NEWER_ID, ff.sig_srst); else - ff.sig_srst = module->Not(NEW_ID, ff.sig_srst); + ff.sig_srst = module->Not(NEWER_ID, ff.sig_srst); } if (ff.is_fine) - ff.sig_ce = module->AndGate(NEW_ID, ff.sig_ce, ff.sig_srst); + ff.sig_ce = module->AndGate(NEWER_ID, ff.sig_ce, ff.sig_srst); else - ff.sig_ce = module->And(NEW_ID, ff.sig_ce, ff.sig_srst); + ff.sig_ce = module->And(NEWER_ID, ff.sig_ce, ff.sig_srst); ff.pol_ce = true; } else { ff.pol_ce = ff.pol_srst; diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 86d96ea7a70..c0d8a7e73bc 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -202,7 +202,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ if (grouped_bits[i].empty()) continue; - RTLIL::SigSpec new_y = module->addWire(NEW_ID, GetSize(grouped_bits[i])); + RTLIL::SigSpec new_y = module->addWire(NEWER_ID, GetSize(grouped_bits[i])); RTLIL::SigSpec new_a, new_b; RTLIL::SigSig new_conn; @@ -247,9 +247,9 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ else if (new_a[i] == State::S0 || new_a[i] == State::S1) { undef_a.append(new_a[i]); if (cell->type == ID($xor)) - undef_b.append(new_a[i] == State::S1 ? module->Not(NEW_ID, new_b[i]).as_bit() : new_b[i]); + undef_b.append(new_a[i] == State::S1 ? module->Not(NEWER_ID, new_b[i]).as_bit() : new_b[i]); else if (cell->type == ID($xnor)) - undef_b.append(new_a[i] == State::S1 ? new_b[i] : module->Not(NEW_ID, new_b[i]).as_bit()); + undef_b.append(new_a[i] == State::S1 ? new_b[i] : module->Not(NEWER_ID, new_b[i]).as_bit()); else log_abort(); undef_y.append(new_y[i]); } @@ -273,7 +273,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ } - RTLIL::Cell *c = module->addCell(NEW_ID, cell->type); + RTLIL::Cell *c = module->addCell(NEWER_ID, cell->type); c->setPort(ID::A, new_a); c->parameters[ID::A_WIDTH] = new_a.size(); @@ -612,9 +612,9 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons cover("opt.opt_expr.xor_buffer"); SigSpec sig_y; if (cell->type == ID($xor)) - sig_y = (sig_b == State::S1 ? module->Not(NEW_ID, sig_a).as_bit() : sig_a); + sig_y = (sig_b == State::S1 ? module->Not(NEWER_ID, sig_a).as_bit() : sig_a); else if (cell->type == ID($_XOR_)) - sig_y = (sig_b == State::S1 ? module->NotGate(NEW_ID, sig_a) : sig_a); + sig_y = (sig_b == State::S1 ? module->NotGate(NEWER_ID, sig_a) : sig_a); else log_abort(); replace_cell(assign_map, module, cell, "xor_buffer", ID::Y, sig_y); goto next_cell; @@ -623,12 +623,12 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons cover("opt.opt_expr.xnor_buffer"); SigSpec sig_y; if (cell->type == ID($xnor)) { - sig_y = (sig_b == State::S1 ? sig_a : module->Not(NEW_ID, sig_a).as_bit()); + sig_y = (sig_b == State::S1 ? sig_a : module->Not(NEWER_ID, sig_a).as_bit()); int width = cell->getParam(ID::Y_WIDTH).as_int(); sig_y.append(RTLIL::Const(State::S1, width-1)); } else if (cell->type == ID($_XNOR_)) - sig_y = (sig_b == State::S1 ? sig_a : module->NotGate(NEW_ID, sig_a)); + sig_y = (sig_b == State::S1 ? sig_a : module->NotGate(NEWER_ID, sig_a)); else log_abort(); replace_cell(assign_map, module, cell, "xnor_buffer", ID::Y, sig_y); goto next_cell; @@ -698,7 +698,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (!y_group_1.empty()) y_new_1 = b_group_1; if (!y_group_x.empty()) { if (keepdc) - y_new_x = module->And(NEW_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x); + y_new_x = module->And(NEWER_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x); else y_new_x = Const(State::S0, GetSize(y_group_x)); } @@ -707,16 +707,16 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (!y_group_1.empty()) y_new_1 = Const(State::S1, GetSize(y_group_1)); if (!y_group_x.empty()) { if (keepdc) - y_new_x = module->Or(NEW_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x); + y_new_x = module->Or(NEWER_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x); else y_new_x = Const(State::S1, GetSize(y_group_x)); } } else if (cell->type.in(ID($xor), ID($xnor))) { if (!y_group_0.empty()) y_new_0 = b_group_0; - if (!y_group_1.empty()) y_new_1 = module->Not(NEW_ID, b_group_1); + if (!y_group_1.empty()) y_new_1 = module->Not(NEWER_ID, b_group_1); if (!y_group_x.empty()) { if (keepdc) - y_new_x = module->Xor(NEW_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x); + y_new_x = module->Xor(NEWER_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x); else // This should be fine even with keepdc, but opt_expr_xor.ys wants to keep the xor y_new_x = Const(State::Sx, GetSize(y_group_x)); } @@ -779,11 +779,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons RTLIL::SigSpec y_new_0, y_new_1; if (flip) { - if (!y_group_0.empty()) y_new_0 = module->And(NEW_ID, b_group_0, module->Not(NEW_ID, s_group_0)); - if (!y_group_1.empty()) y_new_1 = module->Or(NEW_ID, b_group_1, s_group_1); + if (!y_group_0.empty()) y_new_0 = module->And(NEWER_ID, b_group_0, module->Not(NEWER_ID, s_group_0)); + if (!y_group_1.empty()) y_new_1 = module->Or(NEWER_ID, b_group_1, s_group_1); } else { - if (!y_group_0.empty()) y_new_0 = module->And(NEW_ID, b_group_0, s_group_0); - if (!y_group_1.empty()) y_new_1 = module->Or(NEW_ID, b_group_1, module->Not(NEW_ID, s_group_1)); + if (!y_group_0.empty()) y_new_0 = module->And(NEWER_ID, b_group_0, s_group_0); + if (!y_group_1.empty()) y_new_1 = module->Or(NEWER_ID, b_group_1, module->Not(NEWER_ID, s_group_1)); } module->connect(y_group_0, y_new_0); @@ -996,12 +996,12 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons RTLIL::SigBit a = sig_a[i]; if (b == ((bi ^ ci) ? State::S1 : State::S0)) { module->connect(sig_y[i], a); - module->connect(sig_x[i], ci ? module->Not(NEW_ID, a).as_bit() : a); + module->connect(sig_x[i], ci ? module->Not(NEWER_ID, a).as_bit() : a); module->connect(sig_co[i], ci ? State::S1 : State::S0); } else if (a == (ci ? State::S1 : State::S0)) { - module->connect(sig_y[i], bi ? module->Not(NEW_ID, b).as_bit() : b); - module->connect(sig_x[i], (bi ^ ci) ? module->Not(NEW_ID, b).as_bit() : b); + module->connect(sig_y[i], bi ? module->Not(NEWER_ID, b).as_bit() : b); + module->connect(sig_x[i], (bi ^ ci) ? module->Not(NEWER_ID, b).as_bit() : b); module->connect(sig_co[i], ci ? State::S1 : State::S0); } else @@ -1428,7 +1428,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons /* sub, b is 0 */ RTLIL::SigSpec a = cell->getPort(ID::A); a.extend_u0(y_width, is_signed); - module->connect(cell->getPort(ID::X), module->Not(NEW_ID, a)); + module->connect(cell->getPort(ID::X), module->Not(NEWER_ID, a)); module->connect(cell->getPort(ID::CO), RTLIL::Const(State::S1, y_width)); } else { /* add */ @@ -1733,10 +1733,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons cell->parameters[ID::A_SIGNED] = 0; cell->setPort(ID::A, Const(bit_idx, cell->parameters[ID::A_WIDTH].as_int())); - SigSpec y_wire = module->addWire(NEW_ID, y_size); + SigSpec y_wire = module->addWire(NEWER_ID, y_size); cell->setPort(ID::Y, y_wire); - module->addShl(NEW_ID, Const(State::S1, 1), y_wire, sig_y); + module->addShl(NEWER_ID, Const(State::S1, 1), y_wire, sig_y); } did_something = true; goto next_cell; @@ -1889,13 +1889,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons // Truncating division is the same as flooring division, except when // the result is negative and there is a remainder - then trunc = floor + 1 if (is_truncating && a_signed && GetSize(sig_a) != 0 && exp != 0) { - Wire *flooring = module->addWire(NEW_ID, sig_y.size()); + Wire *flooring = module->addWire(NEWER_ID, sig_y.size()); cell->setPort(ID::Y, flooring); SigSpec a_sign = sig_a[sig_a.size()-1]; - SigSpec rem_nonzero = module->ReduceOr(NEW_ID, sig_a.extract(0, exp)); - SigSpec should_add = module->And(NEW_ID, a_sign, rem_nonzero); - module->addAdd(NEW_ID, flooring, should_add, sig_y); + SigSpec rem_nonzero = module->ReduceOr(NEWER_ID, sig_a.extract(0, exp)); + SigSpec should_add = module->And(NEWER_ID, a_sign, rem_nonzero); + module->addAdd(NEWER_ID, flooring, should_add, sig_y); } cell->check(); @@ -1917,11 +1917,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons SigSpec truncating = sig_a.extract(0, exp); SigSpec a_sign = sig_a[sig_a.size()-1]; - SigSpec rem_nonzero = module->ReduceOr(NEW_ID, sig_a.extract(0, exp)); - SigSpec extend_bit = module->And(NEW_ID, a_sign, rem_nonzero); + SigSpec rem_nonzero = module->ReduceOr(NEWER_ID, sig_a.extract(0, exp)); + SigSpec extend_bit = module->And(NEWER_ID, a_sign, rem_nonzero); truncating.append(extend_bit); - module->addPos(NEW_ID, truncating, sig_y, true); + module->addPos(NEWER_ID, truncating, sig_y, true); } else { @@ -2004,7 +2004,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons int sz = cur - prev; bool last = cur == GetSize(sig_y); - RTLIL::Cell *c = module->addCell(NEW_ID, cell->type); + RTLIL::Cell *c = module->addCell(NEWER_ID, cell->type); c->setPort(ID::A, sig_a.extract(prev, sz)); c->setPort(ID::B, sig_b.extract(prev, sz)); c->setPort(ID::BI, sig_bi); @@ -2014,7 +2014,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons RTLIL::SigSpec new_co = sig_co.extract(prev, sz); if (p.second != State::Sx) { module->connect(new_co[sz-1], p.second); - RTLIL::Wire *dummy = module->addWire(NEW_ID); + RTLIL::Wire *dummy = module->addWire(NEWER_ID); new_co[sz-1] = dummy; } c->setPort(ID::CO, new_co); @@ -2181,14 +2181,14 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons { condition = stringf("unsigned X<%s", log_signal(const_sig)); replacement = stringf("!X[%d:%d]", var_width - 1, const_bit_hot); - module->addLogicNot(NEW_ID, var_high_sig, cell->getPort(ID::Y)); + module->addLogicNot(NEWER_ID, var_high_sig, cell->getPort(ID::Y)); remove = true; } if (cmp_type == ID($ge)) { condition = stringf("unsigned X>=%s", log_signal(const_sig)); replacement = stringf("|X[%d:%d]", var_width - 1, const_bit_hot); - module->addReduceOr(NEW_ID, var_high_sig, cell->getPort(ID::Y)); + module->addReduceOr(NEWER_ID, var_high_sig, cell->getPort(ID::Y)); remove = true; } } @@ -2230,7 +2230,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons { condition = "signed X>=0"; replacement = stringf("X[%d]", var_width - 1); - module->addLogicNot(NEW_ID, var_sig[var_width - 1], cell->getPort(ID::Y)); + module->addLogicNot(NEWER_ID, var_sig[var_width - 1], cell->getPort(ID::Y)); remove = true; } } diff --git a/passes/opt/opt_hier.cc b/passes/opt/opt_hier.cc index a8df78dc1e1..ddead1ef032 100644 --- a/passes/opt/opt_hier.cc +++ b/passes/opt/opt_hier.cc @@ -137,7 +137,7 @@ struct ModuleIndex { rhs.replace(constant_outputs); log_assert(rhs.is_fully_const()); parent.module->connect(value.extract(chunk.offset, chunk.width), rhs); - SigSpec dummy = parent.module->addWire(NEW_ID_SUFFIX("const_output"), chunk.width); + SigSpec dummy = parent.module->addWire(NEWER_ID_SUFFIX("const_output"), chunk.width); for (int i = 0; i < chunk.width; i++) value[chunk.offset + i] = dummy[i]; } @@ -182,7 +182,7 @@ struct ModuleIndex { severed_port_bits.sort_and_unify(); for (auto chunk : severed_port_bits.chunks()) { SigSpec &value = instantiation->connections_.at(chunk.wire->name); - SigSpec dummy = parent.module->addWire(NEW_ID_SUFFIX("tie_together"), chunk.width); + SigSpec dummy = parent.module->addWire(NEWER_ID_SUFFIX("tie_together"), chunk.width); for (int i = 0; i < chunk.width; i++) value[chunk.offset + i] = dummy[i]; } diff --git a/passes/opt/opt_mem.cc b/passes/opt/opt_mem.cc index 9c5a6d83e71..cb919e0ab8c 100644 --- a/passes/opt/opt_mem.cc +++ b/passes/opt/opt_mem.cc @@ -125,7 +125,7 @@ struct OptMemPass : public Pass { module->connect(port.data[bidx], bit); } else { // The FF will most likely be redundant, but it's up to opt_dff to deal with this. - FfData ff(module, &initvals, NEW_ID); + FfData ff(module, &initvals, NEWER_ID); ff.width = 1; ff.has_clk = true; ff.sig_clk = port.clk; diff --git a/passes/opt/opt_mem_feedback.cc b/passes/opt/opt_mem_feedback.cc index 20a2a79ed84..20d35e1fd69 100644 --- a/passes/opt/opt_mem_feedback.cc +++ b/passes/opt/opt_mem_feedback.cc @@ -120,7 +120,7 @@ struct OptMemFeedbackWorker sig1.append(it.first); sig2.append(it.second ? RTLIL::State::S1 : RTLIL::State::S0); } - terms.append(module->Ne(NEW_ID, sig1, sig2)); + terms.append(module->Ne(NEWER_ID, sig1, sig2)); } if (olden != State::S1) @@ -130,7 +130,7 @@ struct OptMemFeedbackWorker terms = State::S1; if (GetSize(terms) > 1) - terms = module->ReduceAnd(NEW_ID, terms); + terms = module->ReduceAnd(NEWER_ID, terms); return conditions_logic_cache[key] = terms; } diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index 6d6cadfe78e..8cdacf67250 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -128,13 +128,13 @@ struct OptReduceWorker if (this_s.size() > 1) { - RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, ID($reduce_or)); + RTLIL::Cell *reduce_or_cell = module->addCell(NEWER_ID, ID($reduce_or)); reduce_or_cell->setPort(ID::A, this_s); reduce_or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0); reduce_or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(this_s.size()); reduce_or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1); - RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID); + RTLIL::Wire *reduce_or_wire = module->addWire(NEWER_ID); this_s = RTLIL::SigSpec(reduce_or_wire); reduce_or_cell->setPort(ID::Y, this_s); } diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index bf9569d9905..7bc8db40dbf 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -196,7 +196,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector< for (auto &operand : muxed_operands) { operand.sig.extend_u0(max_width, operand.is_signed); if (operand.sign != muxed_operands[0].sign) - operand = ExtSigSpec(module->Neg(NEW_ID, operand.sig, operand.is_signed)); + operand = ExtSigSpec(module->Neg(NEWER_ID, operand.sig, operand.is_signed)); } for (const auto& p : ports) { @@ -219,7 +219,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector< RTLIL::SigSpec shared_pmux_s; // Make a new wire to avoid false equivalence with whatever the former shared output was connected to. - Wire *new_out = module->addWire(NEW_ID, conn_op_offset + conn_width); + Wire *new_out = module->addWire(NEWER_ID, conn_op_offset + conn_width); SigSpec new_sig_out = SigSpec(new_out, conn_op_offset, conn_width); for (int i = 0; i < GetSize(ports); i++) { @@ -241,14 +241,14 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector< SigSpec mux_to_oper; if (GetSize(shared_pmux_s) == 1) { - mux_to_oper = module->Mux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s); + mux_to_oper = module->Mux(NEWER_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s); } else { - mux_to_oper = module->Pmux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s); + mux_to_oper = module->Pmux(NEWER_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s); } if (shared_op->type.in(ID($alu))) { - shared_op->setPort(ID::X, module->addWire(NEW_ID, GetSize(new_out))); - shared_op->setPort(ID::CO, module->addWire(NEW_ID, GetSize(new_out))); + shared_op->setPort(ID::X, module->addWire(NEWER_ID, GetSize(new_out))); + shared_op->setPort(ID::CO, module->addWire(NEWER_ID, GetSize(new_out))); } bool is_fine = shared_op->type.in(FINE_BITWISE_OPS); diff --git a/passes/opt/peepopt_formal_clockgateff.pmg b/passes/opt/peepopt_formal_clockgateff.pmg index 835f68bd86d..dfdff7c4ed2 100644 --- a/passes/opt/peepopt_formal_clockgateff.pmg +++ b/passes/opt/peepopt_formal_clockgateff.pmg @@ -50,8 +50,8 @@ code // instead of the latch. We don't delete the latch in case its output is // used to drive other nodes. If it isn't, it will be trivially removed by // clean - SigSpec flopped_en = module->addWire(NEW_ID); - module->addDff(NEW_ID, clk, en, flopped_en, true, latch->get_src_attribute()); + SigSpec flopped_en = module->addWire(NEWER_ID); + module->addDff(NEWER_ID, clk, en, flopped_en, true, latch->get_src_attribute()); and_gate->setPort(latched_en_port_name, flopped_en); did_something = true; diff --git a/passes/opt/peepopt_shiftmul_left.pmg b/passes/opt/peepopt_shiftmul_left.pmg index 607f8368c53..554d6fb980e 100644 --- a/passes/opt/peepopt_shiftmul_left.pmg +++ b/passes/opt/peepopt_shiftmul_left.pmg @@ -129,7 +129,7 @@ code if (bit == SigBit(State::Sm)) padbits++; - SigSpec padwire = module->addWire(NEW_ID, padbits); + SigSpec padwire = module->addWire(NEWER_ID, padbits); for (int i = new_y.size() - 1; i >= 0; i--) if (new_y[i] == SigBit(State::Sm)) { @@ -148,8 +148,8 @@ code shift->setPort(\B, new_b); shift->setParam(\B_WIDTH, GetSize(new_b)); } else { - SigSpec b_neg = module->addWire(NEW_ID, GetSize(new_b) + 1); - module->addNeg(NEW_ID, new_b, b_neg); + SigSpec b_neg = module->addWire(NEWER_ID, GetSize(new_b) + 1); + module->addNeg(NEWER_ID, new_b, b_neg); shift->setPort(\B, b_neg); shift->setParam(\B_WIDTH, GetSize(b_neg)); } diff --git a/passes/opt/pmux2shiftx.cc b/passes/opt/pmux2shiftx.cc index 4a0864df0d6..1739a8b479e 100644 --- a/passes/opt/pmux2shiftx.cc +++ b/passes/opt/pmux2shiftx.cc @@ -680,9 +680,9 @@ struct Pmux2ShiftxPass : public Pass { // creat cmp signal SigSpec cmp = perm_sig; if (perm_xormask.as_bool()) - cmp = module->Xor(NEW_ID, cmp, perm_xormask, false, src); + cmp = module->Xor(NEWER_ID, cmp, perm_xormask, false, src); if (offset.as_bool()) - cmp = module->Sub(NEW_ID, cmp, offset, false, src); + cmp = module->Sub(NEWER_ID, cmp, offset, false, src); // create enable signal SigBit en = State::S1; @@ -690,8 +690,8 @@ struct Pmux2ShiftxPass : public Pass { Const enable_mask(State::S0, max_choice+1); for (auto &it : perm_choices) enable_mask.set(it.first.as_int(), State::S1); - en = module->addWire(NEW_ID); - module->addShift(NEW_ID, enable_mask, cmp, en, false, src); + en = module->addWire(NEWER_ID); + module->addShift(NEWER_ID, enable_mask, cmp, en, false, src); } // create data signal @@ -710,8 +710,8 @@ struct Pmux2ShiftxPass : public Pass { // create shiftx cell SigSpec shifted_cmp = {cmp, SigSpec(State::S0, width_bits)}; - SigSpec outsig = module->addWire(NEW_ID, width); - Cell *c = module->addShiftx(NEW_ID, data, shifted_cmp, outsig, false, src); + SigSpec outsig = module->addWire(NEWER_ID, width); + Cell *c = module->addShiftx(NEWER_ID, data, shifted_cmp, outsig, false, src); updated_S.append(en); updated_B.append(outsig); log(" created $shiftx cell %s.\n", log_id(c)); diff --git a/passes/opt/share.cc b/passes/opt/share.cc index 307cd299bd5..16f308603ea 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -207,13 +207,13 @@ struct ShareWorker sig_b2.extend_u0(GetSize(sig_b), p2.is_signed); if (supercell_aux && GetSize(sig_a)) { - sig_a = module->addWire(NEW_ID, GetSize(sig_a)); - supercell_aux->insert(module->addMux(NEW_ID, sig_a2, sig_a1, act, sig_a)); + sig_a = module->addWire(NEWER_ID, GetSize(sig_a)); + supercell_aux->insert(module->addMux(NEWER_ID, sig_a2, sig_a1, act, sig_a)); } if (supercell_aux && GetSize(sig_b)) { - sig_b = module->addWire(NEW_ID, GetSize(sig_b)); - supercell_aux->insert(module->addMux(NEW_ID, sig_b2, sig_b1, act, sig_b)); + sig_b = module->addWire(NEWER_ID, GetSize(sig_b)); + supercell_aux->insert(module->addMux(NEWER_ID, sig_b2, sig_b1, act, sig_b)); } Macc::term_t p; @@ -284,13 +284,13 @@ struct ShareWorker RTLIL::SigSpec sig_b = m1.terms[i].in_b; if (supercell_aux && GetSize(sig_a)) { - sig_a = module->addWire(NEW_ID, GetSize(sig_a)); - supercell_aux->insert(module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(sig_a)), m1.terms[i].in_a, act, sig_a)); + sig_a = module->addWire(NEWER_ID, GetSize(sig_a)); + supercell_aux->insert(module->addMux(NEWER_ID, RTLIL::SigSpec(0, GetSize(sig_a)), m1.terms[i].in_a, act, sig_a)); } if (supercell_aux && GetSize(sig_b)) { - sig_b = module->addWire(NEW_ID, GetSize(sig_b)); - supercell_aux->insert(module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(sig_b)), m1.terms[i].in_b, act, sig_b)); + sig_b = module->addWire(NEWER_ID, GetSize(sig_b)); + supercell_aux->insert(module->addMux(NEWER_ID, RTLIL::SigSpec(0, GetSize(sig_b)), m1.terms[i].in_b, act, sig_b)); } Macc::term_t p; @@ -307,13 +307,13 @@ struct ShareWorker RTLIL::SigSpec sig_b = m2.terms[i].in_b; if (supercell_aux && GetSize(sig_a)) { - sig_a = module->addWire(NEW_ID, GetSize(sig_a)); - supercell_aux->insert(module->addMux(NEW_ID, m2.terms[i].in_a, RTLIL::SigSpec(0, GetSize(sig_a)), act, sig_a)); + sig_a = module->addWire(NEWER_ID, GetSize(sig_a)); + supercell_aux->insert(module->addMux(NEWER_ID, m2.terms[i].in_a, RTLIL::SigSpec(0, GetSize(sig_a)), act, sig_a)); } if (supercell_aux && GetSize(sig_b)) { - sig_b = module->addWire(NEW_ID, GetSize(sig_b)); - supercell_aux->insert(module->addMux(NEW_ID, m2.terms[i].in_b, RTLIL::SigSpec(0, GetSize(sig_b)), act, sig_b)); + sig_b = module->addWire(NEWER_ID, GetSize(sig_b)); + supercell_aux->insert(module->addMux(NEWER_ID, m2.terms[i].in_b, RTLIL::SigSpec(0, GetSize(sig_b)), act, sig_b)); } Macc::term_t p; @@ -326,10 +326,10 @@ struct ShareWorker if (supercell) { - RTLIL::SigSpec sig_y = module->addWire(NEW_ID, width); + RTLIL::SigSpec sig_y = module->addWire(NEWER_ID, width); - supercell_aux->insert(module->addPos(NEW_ID, sig_y, c1->getPort(ID::Y))); - supercell_aux->insert(module->addPos(NEW_ID, sig_y, c2->getPort(ID::Y))); + supercell_aux->insert(module->addPos(NEWER_ID, sig_y, c1->getPort(ID::Y))); + supercell_aux->insert(module->addPos(NEWER_ID, sig_y, c2->getPort(ID::Y))); supercell->setParam(ID::Y_WIDTH, width); supercell->setPort(ID::Y, sig_y); @@ -541,20 +541,20 @@ struct ShareWorker a1.extend_u0(a_width, a_signed); a2.extend_u0(a_width, a_signed); - RTLIL::SigSpec a = module->addWire(NEW_ID, a_width); - supercell_aux.insert(module->addMux(NEW_ID, a2, a1, act, a)); + RTLIL::SigSpec a = module->addWire(NEWER_ID, a_width); + supercell_aux.insert(module->addMux(NEWER_ID, a2, a1, act, a)); - RTLIL::Wire *y = module->addWire(NEW_ID, y_width); + RTLIL::Wire *y = module->addWire(NEWER_ID, y_width); - RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type); + RTLIL::Cell *supercell = module->addCell(NEWER_ID, c1->type); supercell->parameters[ID::A_SIGNED] = a_signed; supercell->parameters[ID::A_WIDTH] = a_width; supercell->parameters[ID::Y_WIDTH] = y_width; supercell->setPort(ID::A, a); supercell->setPort(ID::Y, y); - supercell_aux.insert(module->addPos(NEW_ID, y, y1)); - supercell_aux.insert(module->addPos(NEW_ID, y, y2)); + supercell_aux.insert(module->addPos(NEWER_ID, y, y1)); + supercell_aux.insert(module->addPos(NEWER_ID, y, y2)); supercell_aux.insert(supercell); return supercell; @@ -656,17 +656,17 @@ struct ShareWorker b1.extend_u0(b_width, b_signed); b2.extend_u0(b_width, b_signed); - RTLIL::SigSpec a = module->addWire(NEW_ID, a_width); - RTLIL::SigSpec b = module->addWire(NEW_ID, b_width); + RTLIL::SigSpec a = module->addWire(NEWER_ID, a_width); + RTLIL::SigSpec b = module->addWire(NEWER_ID, b_width); - supercell_aux.insert(module->addMux(NEW_ID, a2, a1, act, a)); - supercell_aux.insert(module->addMux(NEW_ID, b2, b1, act, b)); + supercell_aux.insert(module->addMux(NEWER_ID, a2, a1, act, a)); + supercell_aux.insert(module->addMux(NEWER_ID, b2, b1, act, b)); - RTLIL::Wire *y = module->addWire(NEW_ID, y_width); - RTLIL::Wire *x = c1->type == ID($alu) ? module->addWire(NEW_ID, y_width) : nullptr; - RTLIL::Wire *co = c1->type == ID($alu) ? module->addWire(NEW_ID, y_width) : nullptr; + RTLIL::Wire *y = module->addWire(NEWER_ID, y_width); + RTLIL::Wire *x = c1->type == ID($alu) ? module->addWire(NEWER_ID, y_width) : nullptr; + RTLIL::Wire *co = c1->type == ID($alu) ? module->addWire(NEWER_ID, y_width) : nullptr; - RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type); + RTLIL::Cell *supercell = module->addCell(NEWER_ID, c1->type); supercell->parameters[ID::A_SIGNED] = a_signed; supercell->parameters[ID::B_SIGNED] = b_signed; supercell->parameters[ID::A_WIDTH] = a_width; @@ -676,9 +676,9 @@ struct ShareWorker supercell->setPort(ID::B, b); supercell->setPort(ID::Y, y); if (c1->type == ID($alu)) { - RTLIL::Wire *ci = module->addWire(NEW_ID), *bi = module->addWire(NEW_ID); - supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID::CI), c1->getPort(ID::CI), act, ci)); - supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID::BI), c1->getPort(ID::BI), act, bi)); + RTLIL::Wire *ci = module->addWire(NEWER_ID), *bi = module->addWire(NEWER_ID); + supercell_aux.insert(module->addMux(NEWER_ID, c2->getPort(ID::CI), c1->getPort(ID::CI), act, ci)); + supercell_aux.insert(module->addMux(NEWER_ID, c2->getPort(ID::BI), c1->getPort(ID::BI), act, bi)); supercell->setPort(ID::CI, ci); supercell->setPort(ID::BI, bi); supercell->setPort(ID::CO, co); @@ -686,13 +686,13 @@ struct ShareWorker } supercell->check(); - supercell_aux.insert(module->addPos(NEW_ID, y, y1)); - supercell_aux.insert(module->addPos(NEW_ID, y, y2)); + supercell_aux.insert(module->addPos(NEWER_ID, y, y1)); + supercell_aux.insert(module->addPos(NEWER_ID, y, y2)); if (c1->type == ID($alu)) { - supercell_aux.insert(module->addPos(NEW_ID, co, c1->getPort(ID::CO))); - supercell_aux.insert(module->addPos(NEW_ID, co, c2->getPort(ID::CO))); - supercell_aux.insert(module->addPos(NEW_ID, x, c1->getPort(ID::X))); - supercell_aux.insert(module->addPos(NEW_ID, x, c2->getPort(ID::X))); + supercell_aux.insert(module->addPos(NEWER_ID, co, c1->getPort(ID::CO))); + supercell_aux.insert(module->addPos(NEWER_ID, co, c2->getPort(ID::CO))); + supercell_aux.insert(module->addPos(NEWER_ID, x, c1->getPort(ID::X))); + supercell_aux.insert(module->addPos(NEWER_ID, x, c2->getPort(ID::X))); } supercell_aux.insert(supercell); @@ -701,7 +701,7 @@ struct ShareWorker if (c1->type == ID($macc)) { - RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type); + RTLIL::Cell *supercell = module->addCell(NEWER_ID, c1->type); supercell_aux.insert(supercell); share_macc(c1, c2, act, supercell, &supercell_aux); supercell->check(); @@ -710,16 +710,16 @@ struct ShareWorker if (c1->type.in(ID($memrd), ID($memrd_v2))) { - RTLIL::Cell *supercell = module->addCell(NEW_ID, c1); + RTLIL::Cell *supercell = module->addCell(NEWER_ID, c1); RTLIL::SigSpec addr1 = c1->getPort(ID::ADDR); RTLIL::SigSpec addr2 = c2->getPort(ID::ADDR); if (GetSize(addr1) < GetSize(addr2)) addr1.extend_u0(GetSize(addr2)); else addr2.extend_u0(GetSize(addr1)); - supercell->setPort(ID::ADDR, addr1 != addr2 ? module->Mux(NEW_ID, addr2, addr1, act) : addr1); + supercell->setPort(ID::ADDR, addr1 != addr2 ? module->Mux(NEWER_ID, addr2, addr1, act) : addr1); supercell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr1)); - supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort(ID::DATA), c2->getPort(ID::DATA))); + supercell_aux.insert(module->addPos(NEWER_ID, supercell->getPort(ID::DATA), c2->getPort(ID::DATA))); supercell_aux.insert(supercell); return supercell; } @@ -1065,18 +1065,18 @@ struct ShareWorker RTLIL::SigSpec make_cell_activation_logic(const pool &activation_patterns, pool &supercell_aux) { - RTLIL::Wire *all_cases_wire = module->addWire(NEW_ID, 0); + RTLIL::Wire *all_cases_wire = module->addWire(NEWER_ID, 0); for (auto &p : activation_patterns) { all_cases_wire->width++; - supercell_aux.insert(module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, all_cases_wire->width - 1))); + supercell_aux.insert(module->addEq(NEWER_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, all_cases_wire->width - 1))); } if (all_cases_wire->width == 1) return all_cases_wire; - RTLIL::Wire *result_wire = module->addWire(NEW_ID); - supercell_aux.insert(module->addReduceOr(NEW_ID, all_cases_wire, result_wire)); + RTLIL::Wire *result_wire = module->addWire(NEWER_ID); + supercell_aux.insert(module->addReduceOr(NEWER_ID, all_cases_wire, result_wire)); return result_wire; } diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 359c76d42d7..a75989385fb 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -511,7 +511,7 @@ struct WreduceWorker continue; log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), log_id(module), log_id(w)); - Wire *nw = module->addWire(NEW_ID, GetSize(w) - unused_top_bits); + Wire *nw = module->addWire(NEWER_ID, GetSize(w) - unused_top_bits); module->connect(nw, SigSpec(w).extract(0, GetSize(nw))); module->swap_names(w, nw); } diff --git a/passes/pmgen/README.md b/passes/pmgen/README.md index 15569ebfc7f..36abed0cf23 100644 --- a/passes/pmgen/README.md +++ b/passes/pmgen/README.md @@ -367,9 +367,9 @@ test-case generation. For example: ... generate 10 0 SigSpec Y = port(ff, \D); - SigSpec A = module->addWire(NEW_ID, GetSize(Y) - rng(GetSize(Y)/2)); - SigSpec B = module->addWire(NEW_ID, GetSize(Y) - rng(GetSize(Y)/2)); - module->addMul(NEW_ID, A, B, Y, rng(2)); + SigSpec A = module->addWire(NEWER_ID, GetSize(Y) - rng(GetSize(Y)/2)); + SigSpec B = module->addWire(NEWER_ID, GetSize(Y) - rng(GetSize(Y)/2)); + module->addMul(NEWER_ID, A, B, Y, rng(2)); endmatch The expression `rng(n)` returns a non-negative integer less than `n`. diff --git a/passes/pmgen/generate.h b/passes/pmgen/generate.h index 85e2087746a..8a3a7eb7a6e 100644 --- a/passes/pmgen/generate.h +++ b/passes/pmgen/generate.h @@ -78,7 +78,7 @@ void generate_pattern(std::function)> run, const while (modcnt < maxmodcnt) { int submodcnt = 0, itercnt = 0, cellcnt = 0; - Module *mod = design->addModule(NEW_ID); + Module *mod = design->addModule(NEWER_ID); while (modcnt < maxmodcnt && submodcnt < maxsubcnt && itercnt++ < 1000) { @@ -130,7 +130,7 @@ void generate_pattern(std::function)> run, const for (auto mod : mods) { Cell *c = m->addCell(mod->name, mod->name); for (auto port : mod->ports) { - Wire *w = m->addWire(NEW_ID, GetSize(mod->wire(port))); + Wire *w = m->addWire(NEWER_ID, GetSize(mod->wire(port))); c->setPort(port, w); } } diff --git a/passes/pmgen/test_pmgen.cc b/passes/pmgen/test_pmgen.cc index 892500850df..cecfaa2129a 100644 --- a/passes/pmgen/test_pmgen.cc +++ b/passes/pmgen/test_pmgen.cc @@ -58,11 +58,11 @@ void reduce_chain(test_pmgen_pm &pm) Cell *c; if (last_cell->type == ID($_AND_)) - c = pm.module->addReduceAnd(NEW_ID, A, Y); + c = pm.module->addReduceAnd(NEWER_ID, A, Y); else if (last_cell->type == ID($_OR_)) - c = pm.module->addReduceOr(NEW_ID, A, Y); + c = pm.module->addReduceOr(NEWER_ID, A, Y); else if (last_cell->type == ID($_XOR_)) - c = pm.module->addReduceXor(NEW_ID, A, Y); + c = pm.module->addReduceXor(NEWER_ID, A, Y); else log_abort(); @@ -87,11 +87,11 @@ void reduce_tree(test_pmgen_pm &pm) Cell *c; if (st.first->type == ID($_AND_)) - c = pm.module->addReduceAnd(NEW_ID, A, Y); + c = pm.module->addReduceAnd(NEWER_ID, A, Y); else if (st.first->type == ID($_OR_)) - c = pm.module->addReduceOr(NEW_ID, A, Y); + c = pm.module->addReduceOr(NEWER_ID, A, Y); else if (st.first->type == ID($_XOR_)) - c = pm.module->addReduceXor(NEW_ID, A, Y); + c = pm.module->addReduceXor(NEWER_ID, A, Y); else log_abort(); @@ -112,7 +112,7 @@ void opt_eqpmux(test_pmgen_pm &pm) log_signal(Y), log_id(st.eq), log_id(st.ne), log_id(st.pmux)); pm.autoremove(st.pmux); - Cell *c = pm.module->addMux(NEW_ID, NE, EQ, st.eq->getPort(ID::Y), Y); + Cell *c = pm.module->addMux(NEWER_ID, NE, EQ, st.eq->getPort(ID::Y), Y); log(" -> %s (%s)\n", log_id(c), log_id(c->type)); } diff --git a/passes/pmgen/test_pmgen.pmg b/passes/pmgen/test_pmgen.pmg index 287ed97d847..3fb1ebada4c 100644 --- a/passes/pmgen/test_pmgen.pmg +++ b/passes/pmgen/test_pmgen.pmg @@ -14,19 +14,19 @@ match first select first->type.in($_AND_, $_OR_, $_XOR_) filter !non_first_cells.count(first) generate - SigSpec A = module->addWire(NEW_ID); - SigSpec B = module->addWire(NEW_ID); - SigSpec Y = module->addWire(NEW_ID); + SigSpec A = module->addWire(NEWER_ID); + SigSpec B = module->addWire(NEWER_ID); + SigSpec Y = module->addWire(NEWER_ID); switch (rng(3)) { case 0: - module->addAndGate(NEW_ID, A, B, Y); + module->addAndGate(NEWER_ID, A, B, Y); break; case 1: - module->addOrGate(NEW_ID, A, B, Y); + module->addOrGate(NEWER_ID, A, B, Y); break; case 2: - module->addXorGate(NEW_ID, A, B, Y); + module->addXorGate(NEWER_ID, A, B, Y); break; } endmatch @@ -82,10 +82,10 @@ match next index next->type === chain.back().first->type index port(next, \Y) === port(chain.back().first, chain.back().second) generate 10 - SigSpec A = module->addWire(NEW_ID); - SigSpec B = module->addWire(NEW_ID); + SigSpec A = module->addWire(NEWER_ID); + SigSpec B = module->addWire(NEWER_ID); SigSpec Y = port(chain.back().first, chain.back().second); - Cell *c = module->addAndGate(NEW_ID, A, B, Y); + Cell *c = module->addAndGate(NEWER_ID, A, B, Y); c->type = chain.back().first->type; endmatch @@ -121,10 +121,10 @@ match eq set eq_inB port(eq, \B) set eq_ne_signed param(eq, \A_SIGNED).as_bool() generate 100 10 - SigSpec A = module->addWire(NEW_ID, rng(7)+1); - SigSpec B = module->addWire(NEW_ID, rng(7)+1); - SigSpec Y = module->addWire(NEW_ID); - module->addEq(NEW_ID, A, B, Y, rng(2)); + SigSpec A = module->addWire(NEWER_ID, rng(7)+1); + SigSpec B = module->addWire(NEWER_ID, rng(7)+1); + SigSpec Y = module->addWire(NEWER_ID); + module->addEq(NEWER_ID, A, B, Y, rng(2)); endmatch match pmux @@ -137,16 +137,16 @@ generate 100 10 int numsel = rng(4) + 1; int idx = rng(numsel); - SigSpec A = module->addWire(NEW_ID, width); - SigSpec Y = module->addWire(NEW_ID, width); + SigSpec A = module->addWire(NEWER_ID, width); + SigSpec Y = module->addWire(NEWER_ID, width); SigSpec B, S; for (int i = 0; i < numsel; i++) { - B.append(module->addWire(NEW_ID, width)); - S.append(i == idx ? port(eq, \Y) : module->addWire(NEW_ID)); + B.append(module->addWire(NEWER_ID, width)); + S.append(i == idx ? port(eq, \Y) : module->addWire(NEWER_ID)); } - module->addPmux(NEW_ID, A, B, S, Y); + module->addPmux(NEWER_ID, A, B, S, Y); endmatch match ne @@ -169,11 +169,11 @@ generate 100 10 if (GetSize(Y)) Y = Y[rng(GetSize(Y))]; else - Y = module->addWire(NEW_ID); + Y = module->addWire(NEWER_ID); } else { - Y = module->addWire(NEW_ID); + Y = module->addWire(NEWER_ID); } - module->addNe(NEW_ID, A, B, Y, rng(2)); + module->addNe(NEWER_ID, A, B, Y, rng(2)); endmatch match pmux2 diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 06c740a8846..c1fd6843c26 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -66,16 +66,16 @@ void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec for (auto it = async_rules.crbegin(); it != async_rules.crend(); it++) { const auto& [sync_value, rule] = *it; - const auto pos_trig = rule->type == RTLIL::SyncType::ST1 ? rule->signal : mod->Not(NEW_ID, rule->signal); + const auto pos_trig = rule->type == RTLIL::SyncType::ST1 ? rule->signal : mod->Not(NEWER_ID, rule->signal); // If pos_trig is true, we have priority at this point in the tree so // set a bit if sync_value has a set bit. Otherwise, defer to the rest // of the priority tree - sig_sr_set = mod->Mux(NEW_ID, sig_sr_set, sync_value, pos_trig); + sig_sr_set = mod->Mux(NEWER_ID, sig_sr_set, sync_value, pos_trig); // Same deal with clear bit - const auto sync_value_inv = mod->Not(NEW_ID, sync_value); - sig_sr_clr = mod->Mux(NEW_ID, sig_sr_clr, sync_value_inv, pos_trig); + const auto sync_value_inv = mod->Not(NEWER_ID, sync_value); + sig_sr_clr = mod->Mux(NEWER_ID, sig_sr_clr, sync_value_inv, pos_trig); } std::stringstream sstr; @@ -217,12 +217,12 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) // (with appropriate negation) RTLIL::SigSpec triggers; for (const auto &[_, it] : async_rules) - triggers.append(it->type == RTLIL::SyncType::ST1 ? it->signal : mod->Not(NEW_ID, it->signal)); + triggers.append(it->type == RTLIL::SyncType::ST1 ? it->signal : mod->Not(NEWER_ID, it->signal)); // Put this into the dummy sync rule so it can be treated the same // as ones coming from the module single_async_rule.type = RTLIL::SyncType::ST1; - single_async_rule.signal = mod->ReduceOr(NEW_ID, triggers); + single_async_rule.signal = mod->ReduceOr(NEWER_ID, triggers); single_async_rule.actions.push_back(RTLIL::SigSig(sig, rstval)); // Replace existing rules with this new rule @@ -239,9 +239,9 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) if (async_rules.size() == 1 && async_rules.front().first == sig) { const auto& [_, rule] = async_rules.front(); if (rule->type == RTLIL::SyncType::ST1) - insig = mod->Mux(NEW_ID, insig, sig, rule->signal); + insig = mod->Mux(NEWER_ID, insig, sig, rule->signal); else - insig = mod->Mux(NEW_ID, sig, insig, rule->signal); + insig = mod->Mux(NEWER_ID, sig, insig, rule->signal); async_rules.clear(); } diff --git a/passes/proc/proc_dlatch.cc b/passes/proc/proc_dlatch.cc index bda2d272f8f..f47446f1f7b 100644 --- a/passes/proc/proc_dlatch.cc +++ b/passes/proc/proc_dlatch.cc @@ -246,20 +246,20 @@ struct proc_dlatch_db_t if (rule.match == State::S1) and_bits.append(rule.signal); else if (rule.match == State::S0) - and_bits.append(module->Not(NEW_ID, rule.signal, false, src)); + and_bits.append(module->Not(NEWER_ID, rule.signal, false, src)); else - and_bits.append(module->Eq(NEW_ID, rule.signal, rule.match, false, src)); + and_bits.append(module->Eq(NEWER_ID, rule.signal, rule.match, false, src)); } if (!rule.children.empty()) { SigSpec or_bits; for (int k : rule.children) or_bits.append(make_hold(k, src)); - and_bits.append(module->ReduceOr(NEW_ID, or_bits, false, src)); + and_bits.append(module->ReduceOr(NEWER_ID, or_bits, false, src)); } if (GetSize(and_bits) == 2) - and_bits = module->And(NEW_ID, and_bits[0], and_bits[1], false, src); + and_bits = module->And(NEWER_ID, and_bits[0], and_bits[1], false, src); log_assert(GetSize(and_bits) == 1); rules_sig[n] = and_bits[0]; @@ -429,7 +429,7 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) SigSpec lhs = latches_bits.first.extract(offset, width); SigSpec rhs = latches_bits.second.extract(offset, width); - Cell *cell = db.module->addDlatch(NEW_ID, db.module->Not(NEW_ID, db.make_hold(n, src)), rhs, lhs); + Cell *cell = db.module->addDlatch(NEWER_ID, db.module->Not(NEWER_ID, db.make_hold(n, src)), rhs, lhs); cell->set_src_attribute(src); db.generated_dlatches.insert(cell); diff --git a/passes/proc/proc_memwr.cc b/passes/proc/proc_memwr.cc index a5ae0d6d549..ec17f33056d 100644 --- a/passes/proc/proc_memwr.cc +++ b/passes/proc/proc_memwr.cc @@ -42,7 +42,7 @@ void proc_memwr(RTLIL::Module *mod, RTLIL::Process *proc, dict &n priority_mask.set(prev_port_ids[i], State::S1); prev_port_ids.push_back(port_id); - RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($memwr_v2)); + RTLIL::Cell *cell = mod->addCell(NEWER_ID, ID($memwr_v2)); cell->attributes = memwr.attributes; cell->setParam(ID::MEMID, Const(memwr.memid.str())); cell->setParam(ID::ABITS, GetSize(memwr.address)); @@ -55,10 +55,10 @@ void proc_memwr(RTLIL::Module *mod, RTLIL::Process *proc, dict &n for (auto sr2 : proc->syncs) { if (sr2->type == RTLIL::SyncType::ST0) { log_assert(sr2->mem_write_actions.empty()); - enable = mod->Mux(NEW_ID, Const(State::S0, GetSize(enable)), enable, sr2->signal); + enable = mod->Mux(NEWER_ID, Const(State::S0, GetSize(enable)), enable, sr2->signal); } else if (sr2->type == RTLIL::SyncType::ST1) { log_assert(sr2->mem_write_actions.empty()); - enable = mod->Mux(NEW_ID, enable, Const(State::S0, GetSize(enable)), sr2->signal); + enable = mod->Mux(NEWER_ID, enable, Const(State::S0, GetSize(enable)), sr2->signal); } } cell->setPort(ID::EN, enable); diff --git a/passes/proc/proc_rom.cc b/passes/proc/proc_rom.cc index a7b485194c0..a064c7f58e8 100644 --- a/passes/proc/proc_rom.cc +++ b/passes/proc/proc_rom.cc @@ -151,8 +151,8 @@ struct RomWorker } // Ok, let's do it. - SigSpec rdata = module->addWire(NEW_ID, GetSize(lhs)); - Mem mem(module, NEW_ID, GetSize(lhs), 0, 1 << abits); + SigSpec rdata = module->addWire(NEWER_ID, GetSize(lhs)); + Mem mem(module, NEWER_ID, GetSize(lhs), 0, 1 << abits); mem.attributes = sw->attributes; Const::Builder builder(mem.size * GetSize(lhs)); diff --git a/passes/sat/assertpmux.cc b/passes/sat/assertpmux.cc index 7b3357f820f..ee698bd2956 100644 --- a/passes/sat/assertpmux.cc +++ b/passes/sat/assertpmux.cc @@ -100,12 +100,12 @@ struct AssertpmuxWorker if (muxport_actsignal.count(muxport) == 0) { if (portidx == 0) - muxport_actsignal[muxport] = module->LogicNot(NEW_ID, cell->getPort(ID::S)); + muxport_actsignal[muxport] = module->LogicNot(NEWER_ID, cell->getPort(ID::S)); else muxport_actsignal[muxport] = cell->getPort(ID::S)[portidx-1]; } - output.append(module->LogicAnd(NEW_ID, muxport_actsignal.at(muxport), get_bit_activation(cell->getPort(ID::Y)[bitidx]))); + output.append(module->LogicAnd(NEWER_ID, muxport_actsignal.at(muxport), get_bit_activation(cell->getPort(ID::Y)[bitidx]))); } output.sort_and_unify(); @@ -113,7 +113,7 @@ struct AssertpmuxWorker if (GetSize(output) == 0) output = State::S0; else if (GetSize(output) > 1) - output = module->ReduceOr(NEW_ID, output); + output = module->ReduceOr(NEWER_ID, output); sigbit_actsignals[bit] = output.as_bit(); } @@ -138,7 +138,7 @@ struct AssertpmuxWorker if (GetSize(output) == 0) output = State::S0; else if (GetSize(output) > 1) - output = module->ReduceOr(NEW_ID, output); + output = module->ReduceOr(NEWER_ID, output); sigspec_actsignals[sig] = output.as_bit(); } @@ -157,13 +157,13 @@ struct AssertpmuxWorker SigSpec cnt(State::S0, cntbits); for (int i = 0; i < swidth; i++) - cnt = module->Add(NEW_ID, cnt, sel[i]); + cnt = module->Add(NEWER_ID, cnt, sel[i]); - SigSpec assert_a = module->Le(NEW_ID, cnt, SigSpec(1, cntbits)); + SigSpec assert_a = module->Le(NEWER_ID, cnt, SigSpec(1, cntbits)); SigSpec assert_en; if (flag_noinit) - assert_en.append(module->LogicNot(NEW_ID, module->Initstate(NEW_ID))); + assert_en.append(module->LogicNot(NEWER_ID, module->Initstate(NEWER_ID))); if (!flag_always) assert_en.append(get_activation(pmux->getPort(ID::Y))); @@ -172,9 +172,9 @@ struct AssertpmuxWorker assert_en = State::S1; if (GetSize(assert_en) == 2) - assert_en = module->LogicAnd(NEW_ID, assert_en[0], assert_en[1]); + assert_en = module->LogicAnd(NEWER_ID, assert_en[0], assert_en[1]); - Cell *assert_cell = module->addAssert(NEW_ID, assert_a, assert_en); + Cell *assert_cell = module->addAssert(NEWER_ID, assert_a, assert_en); if (pmux->attributes.count(ID::src) != 0) assert_cell->attributes[ID::src] = pmux->attributes.at(ID::src); diff --git a/passes/sat/async2sync.cc b/passes/sat/async2sync.cc index e86a78d812c..4463ec2d757 100644 --- a/passes/sat/async2sync.cc +++ b/passes/sat/async2sync.cc @@ -95,27 +95,27 @@ struct Async2syncPass : public Pass { if (trg_width == 0) { if (initstate == State::S0) - initstate = module->Initstate(NEW_ID); + initstate = module->Initstate(NEWER_ID); SigBit sig_en = cell->getPort(ID::EN); - cell->setPort(ID::EN, module->And(NEW_ID, sig_en, initstate)); + cell->setPort(ID::EN, module->And(NEWER_ID, sig_en, initstate)); } else { SigBit sig_en = cell->getPort(ID::EN); SigSpec sig_args = cell->getPort(ID::ARGS); bool trg_polarity = cell->getParam(ID(TRG_POLARITY)).as_bool(); SigBit sig_trg = cell->getPort(ID::TRG); - Wire *sig_en_q = module->addWire(NEW_ID); - Wire *sig_args_q = module->addWire(NEW_ID, GetSize(sig_args)); + Wire *sig_en_q = module->addWire(NEWER_ID); + Wire *sig_args_q = module->addWire(NEWER_ID, GetSize(sig_args)); sig_en_q->attributes.emplace(ID::init, State::S0); - module->addDff(NEW_ID, sig_trg, sig_en, sig_en_q, trg_polarity, cell->get_src_attribute()); - module->addDff(NEW_ID, sig_trg, sig_args, sig_args_q, trg_polarity, cell->get_src_attribute()); + module->addDff(NEWER_ID, sig_trg, sig_en, sig_en_q, trg_polarity, cell->get_src_attribute()); + module->addDff(NEWER_ID, sig_trg, sig_args, sig_args_q, trg_polarity, cell->get_src_attribute()); cell->setPort(ID::EN, sig_en_q); cell->setPort(ID::ARGS, sig_args_q); if (cell->type == ID($check)) { SigBit sig_a = cell->getPort(ID::A); - Wire *sig_a_q = module->addWire(NEW_ID); + Wire *sig_a_q = module->addWire(NEWER_ID); sig_a_q->attributes.emplace(ID::init, State::S1); - module->addDff(NEW_ID, sig_trg, sig_a, sig_a_q, trg_polarity, cell->get_src_attribute()); + module->addDff(NEWER_ID, sig_trg, sig_a, sig_a_q, trg_polarity, cell->get_src_attribute()); cell->setPort(ID::A, sig_a_q); } } @@ -152,38 +152,38 @@ struct Async2syncPass : public Pass { initvals.remove_init(ff.sig_q); - Wire *new_d = module->addWire(NEW_ID, ff.width); - Wire *new_q = module->addWire(NEW_ID, ff.width); + Wire *new_d = module->addWire(NEWER_ID, ff.width); + Wire *new_q = module->addWire(NEWER_ID, ff.width); SigSpec sig_set = ff.sig_set; SigSpec sig_clr = ff.sig_clr; if (!ff.pol_set) { if (!ff.is_fine) - sig_set = module->Not(NEW_ID, sig_set); + sig_set = module->Not(NEWER_ID, sig_set); else - sig_set = module->NotGate(NEW_ID, sig_set); + sig_set = module->NotGate(NEWER_ID, sig_set); } if (ff.pol_clr) { if (!ff.is_fine) - sig_clr = module->Not(NEW_ID, sig_clr); + sig_clr = module->Not(NEWER_ID, sig_clr); else - sig_clr = module->NotGate(NEW_ID, sig_clr); + sig_clr = module->NotGate(NEWER_ID, sig_clr); } if (!ff.is_fine) { - SigSpec tmp = module->Or(NEW_ID, ff.sig_d, sig_set); - module->addAnd(NEW_ID, tmp, sig_clr, new_d); + SigSpec tmp = module->Or(NEWER_ID, ff.sig_d, sig_set); + module->addAnd(NEWER_ID, tmp, sig_clr, new_d); - tmp = module->Or(NEW_ID, new_q, sig_set); - module->addAnd(NEW_ID, tmp, sig_clr, ff.sig_q); + tmp = module->Or(NEWER_ID, new_q, sig_set); + module->addAnd(NEWER_ID, tmp, sig_clr, ff.sig_q); } else { - SigSpec tmp = module->OrGate(NEW_ID, ff.sig_d, sig_set); - module->addAndGate(NEW_ID, tmp, sig_clr, new_d); + SigSpec tmp = module->OrGate(NEWER_ID, ff.sig_d, sig_set); + module->addAndGate(NEWER_ID, tmp, sig_clr, new_d); - tmp = module->OrGate(NEW_ID, new_q, sig_set); - module->addAndGate(NEW_ID, tmp, sig_clr, ff.sig_q); + tmp = module->OrGate(NEWER_ID, new_q, sig_set); + module->addAndGate(NEWER_ID, tmp, sig_clr, ff.sig_q); } ff.sig_d = new_d; @@ -198,24 +198,24 @@ struct Async2syncPass : public Pass { initvals.remove_init(ff.sig_q); - Wire *new_d = module->addWire(NEW_ID, ff.width); - Wire *new_q = module->addWire(NEW_ID, ff.width); + Wire *new_d = module->addWire(NEWER_ID, ff.width); + Wire *new_q = module->addWire(NEWER_ID, ff.width); if (ff.pol_aload) { if (!ff.is_fine) { - module->addMux(NEW_ID, new_q, ff.sig_ad, ff.sig_aload, ff.sig_q); - module->addMux(NEW_ID, ff.sig_d, ff.sig_ad, ff.sig_aload, new_d); + module->addMux(NEWER_ID, new_q, ff.sig_ad, ff.sig_aload, ff.sig_q); + module->addMux(NEWER_ID, ff.sig_d, ff.sig_ad, ff.sig_aload, new_d); } else { - module->addMuxGate(NEW_ID, new_q, ff.sig_ad, ff.sig_aload, ff.sig_q); - module->addMuxGate(NEW_ID, ff.sig_d, ff.sig_ad, ff.sig_aload, new_d); + module->addMuxGate(NEWER_ID, new_q, ff.sig_ad, ff.sig_aload, ff.sig_q); + module->addMuxGate(NEWER_ID, ff.sig_d, ff.sig_ad, ff.sig_aload, new_d); } } else { if (!ff.is_fine) { - module->addMux(NEW_ID, ff.sig_ad, new_q, ff.sig_aload, ff.sig_q); - module->addMux(NEW_ID, ff.sig_ad, ff.sig_d, ff.sig_aload, new_d); + module->addMux(NEWER_ID, ff.sig_ad, new_q, ff.sig_aload, ff.sig_q); + module->addMux(NEWER_ID, ff.sig_ad, ff.sig_d, ff.sig_aload, new_d); } else { - module->addMuxGate(NEW_ID, ff.sig_ad, new_q, ff.sig_aload, ff.sig_q); - module->addMuxGate(NEW_ID, ff.sig_ad, ff.sig_d, ff.sig_aload, new_d); + module->addMuxGate(NEWER_ID, ff.sig_ad, new_q, ff.sig_aload, ff.sig_q); + module->addMuxGate(NEWER_ID, ff.sig_ad, ff.sig_d, ff.sig_aload, new_d); } } @@ -231,18 +231,18 @@ struct Async2syncPass : public Pass { initvals.remove_init(ff.sig_q); - Wire *new_q = module->addWire(NEW_ID, ff.width); + Wire *new_q = module->addWire(NEWER_ID, ff.width); if (ff.pol_arst) { if (!ff.is_fine) - module->addMux(NEW_ID, new_q, ff.val_arst, ff.sig_arst, ff.sig_q); + module->addMux(NEWER_ID, new_q, ff.val_arst, ff.sig_arst, ff.sig_q); else - module->addMuxGate(NEW_ID, new_q, ff.val_arst[0], ff.sig_arst, ff.sig_q); + module->addMuxGate(NEWER_ID, new_q, ff.val_arst[0], ff.sig_arst, ff.sig_q); } else { if (!ff.is_fine) - module->addMux(NEW_ID, ff.val_arst, new_q, ff.sig_arst, ff.sig_q); + module->addMux(NEWER_ID, ff.val_arst, new_q, ff.sig_arst, ff.sig_q); else - module->addMuxGate(NEW_ID, ff.val_arst[0], new_q, ff.sig_arst, ff.sig_q); + module->addMuxGate(NEWER_ID, ff.val_arst[0], new_q, ff.sig_arst, ff.sig_q); } ff.sig_q = new_q; @@ -265,21 +265,21 @@ struct Async2syncPass : public Pass { initvals.remove_init(ff.sig_q); - Wire *new_q = module->addWire(NEW_ID, ff.width); + Wire *new_q = module->addWire(NEWER_ID, ff.width); Wire *new_d; if (ff.has_aload) { - new_d = module->addWire(NEW_ID, ff.width); + new_d = module->addWire(NEWER_ID, ff.width); if (ff.pol_aload) { if (!ff.is_fine) - module->addMux(NEW_ID, new_q, ff.sig_ad, ff.sig_aload, new_d); + module->addMux(NEWER_ID, new_q, ff.sig_ad, ff.sig_aload, new_d); else - module->addMuxGate(NEW_ID, new_q, ff.sig_ad, ff.sig_aload, new_d); + module->addMuxGate(NEWER_ID, new_q, ff.sig_ad, ff.sig_aload, new_d); } else { if (!ff.is_fine) - module->addMux(NEW_ID, ff.sig_ad, new_q, ff.sig_aload, new_d); + module->addMux(NEWER_ID, ff.sig_ad, new_q, ff.sig_aload, new_d); else - module->addMuxGate(NEW_ID, ff.sig_ad, new_q, ff.sig_aload, new_d); + module->addMuxGate(NEWER_ID, ff.sig_ad, new_q, ff.sig_aload, new_d); } } else { new_d = new_q; @@ -291,36 +291,36 @@ struct Async2syncPass : public Pass { if (!ff.pol_set) { if (!ff.is_fine) - sig_set = module->Not(NEW_ID, sig_set); + sig_set = module->Not(NEWER_ID, sig_set); else - sig_set = module->NotGate(NEW_ID, sig_set); + sig_set = module->NotGate(NEWER_ID, sig_set); } if (ff.pol_clr) { if (!ff.is_fine) - sig_clr = module->Not(NEW_ID, sig_clr); + sig_clr = module->Not(NEWER_ID, sig_clr); else - sig_clr = module->NotGate(NEW_ID, sig_clr); + sig_clr = module->NotGate(NEWER_ID, sig_clr); } if (!ff.is_fine) { - SigSpec tmp = module->Or(NEW_ID, new_d, sig_set); - module->addAnd(NEW_ID, tmp, sig_clr, ff.sig_q); + SigSpec tmp = module->Or(NEWER_ID, new_d, sig_set); + module->addAnd(NEWER_ID, tmp, sig_clr, ff.sig_q); } else { - SigSpec tmp = module->OrGate(NEW_ID, new_d, sig_set); - module->addAndGate(NEW_ID, tmp, sig_clr, ff.sig_q); + SigSpec tmp = module->OrGate(NEWER_ID, new_d, sig_set); + module->addAndGate(NEWER_ID, tmp, sig_clr, ff.sig_q); } } else if (ff.has_arst) { if (ff.pol_arst) { if (!ff.is_fine) - module->addMux(NEW_ID, new_d, ff.val_arst, ff.sig_arst, ff.sig_q); + module->addMux(NEWER_ID, new_d, ff.val_arst, ff.sig_arst, ff.sig_q); else - module->addMuxGate(NEW_ID, new_d, ff.val_arst[0], ff.sig_arst, ff.sig_q); + module->addMuxGate(NEWER_ID, new_d, ff.val_arst[0], ff.sig_arst, ff.sig_q); } else { if (!ff.is_fine) - module->addMux(NEW_ID, ff.val_arst, new_d, ff.sig_arst, ff.sig_q); + module->addMux(NEWER_ID, ff.val_arst, new_d, ff.sig_arst, ff.sig_q); else - module->addMuxGate(NEW_ID, ff.val_arst[0], new_d, ff.sig_arst, ff.sig_q); + module->addMuxGate(NEWER_ID, ff.val_arst[0], new_d, ff.sig_arst, ff.sig_q); } } else { module->connect(ff.sig_q, new_d); diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index db1eaad4b71..3b60f319a39 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -66,31 +66,31 @@ struct Clk2fflogicPass : public Pass { SampledSig sample_control(Module *module, SigSpec sig, bool polarity, bool is_fine) { if (!polarity) { if (is_fine) - sig = module->NotGate(NEW_ID, sig); + sig = module->NotGate(NEWER_ID, sig); else - sig = module->Not(NEW_ID, sig); + sig = module->Not(NEWER_ID, sig); } std::string sig_str = log_signal(sig); sig_str.erase(std::remove(sig_str.begin(), sig_str.end(), ' '), sig_str.end()); - Wire *sampled_sig = module->addWire(NEW_ID_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig)); + Wire *sampled_sig = module->addWire(NEWER_ID_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig)); sampled_sig->attributes[ID::init] = RTLIL::Const(State::S0, GetSize(sig)); if (is_fine) - module->addFfGate(NEW_ID, sig, sampled_sig); + module->addFfGate(NEWER_ID, sig, sampled_sig); else - module->addFf(NEW_ID, sig, sampled_sig); + module->addFf(NEWER_ID, sig, sampled_sig); return {sampled_sig, sig}; } // Active-high trigger signal for an edge-triggered control signal. Initial values is low/non-edge. SigSpec sample_control_edge(Module *module, SigSpec sig, bool polarity, bool is_fine) { std::string sig_str = log_signal(sig); sig_str.erase(std::remove(sig_str.begin(), sig_str.end(), ' '), sig_str.end()); - Wire *sampled_sig = module->addWire(NEW_ID_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig)); + Wire *sampled_sig = module->addWire(NEWER_ID_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig)); sampled_sig->attributes[ID::init] = RTLIL::Const(polarity ? State::S1 : State::S0, GetSize(sig)); if (is_fine) - module->addFfGate(NEW_ID, sig, sampled_sig); + module->addFfGate(NEWER_ID, sig, sampled_sig); else - module->addFf(NEW_ID, sig, sampled_sig); - return module->Eqx(NEW_ID, {sampled_sig, sig}, polarity ? SigSpec {State::S0, State::S1} : SigSpec {State::S1, State::S0}); + module->addFf(NEWER_ID, sig, sampled_sig); + return module->Eqx(NEWER_ID, {sampled_sig, sig}, polarity ? SigSpec {State::S0, State::S1} : SigSpec {State::S1, State::S0}); } // Sampled and current value of a data signal. SampledSig sample_data(Module *module, SigSpec sig, RTLIL::Const init, bool is_fine, bool set_attribute = false) { @@ -98,14 +98,14 @@ struct Clk2fflogicPass : public Pass { sig_str.erase(std::remove(sig_str.begin(), sig_str.end(), ' '), sig_str.end()); - Wire *sampled_sig = module->addWire(NEW_ID_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig)); + Wire *sampled_sig = module->addWire(NEWER_ID_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig)); sampled_sig->attributes[ID::init] = init; Cell *cell; if (is_fine) - cell = module->addFfGate(NEW_ID, sig, sampled_sig); + cell = module->addFfGate(NEWER_ID, sig, sampled_sig); else - cell = module->addFf(NEW_ID, sig, sampled_sig); + cell = module->addFf(NEWER_ID, sig, sampled_sig); if (set_attribute) { for (auto &chunk : sig.chunks()) @@ -118,15 +118,15 @@ struct Clk2fflogicPass : public Pass { } SigSpec mux(Module *module, SigSpec a, SigSpec b, SigSpec s, bool is_fine) { if (is_fine) - return module->MuxGate(NEW_ID, a, b, s); + return module->MuxGate(NEWER_ID, a, b, s); else - return module->Mux(NEW_ID, a, b, s); + return module->Mux(NEWER_ID, a, b, s); } SigSpec bitwise_sr(Module *module, SigSpec a, SigSpec s, SigSpec r, bool is_fine) { if (is_fine) - return module->AndGate(NEW_ID, module->OrGate(NEW_ID, a, s), module->NotGate(NEW_ID, r)); + return module->AndGate(NEWER_ID, module->OrGate(NEWER_ID, a, s), module->NotGate(NEWER_ID, r)); else - return module->And(NEW_ID, module->Or(NEW_ID, a, s), module->Not(NEW_ID, r)); + return module->And(NEWER_ID, module->Or(NEWER_ID, a, s), module->Not(NEWER_ID, r)); } void execute(std::vector args, RTLIL::Design *design) override { @@ -183,9 +183,9 @@ struct Clk2fflogicPass : public Pass { i, log_id(module), log_id(mem.memid), log_signal(port.clk), log_signal(port.addr), log_signal(port.data)); - Wire *past_clk = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#past_clk#%s", log_id(mem.memid), i, log_signal(port.clk)))); + Wire *past_clk = module->addWire(NEWER_ID_SUFFIX(stringf("%s#%d#past_clk#%s", log_id(mem.memid), i, log_signal(port.clk)))); past_clk->attributes[ID::init] = port.clk_polarity ? State::S1 : State::S0; - module->addFf(NEW_ID, port.clk, past_clk); + module->addFf(NEWER_ID, port.clk, past_clk); SigSpec clock_edge_pattern; @@ -197,19 +197,19 @@ struct Clk2fflogicPass : public Pass { clock_edge_pattern.append(State::S0); } - SigSpec clock_edge = module->Eqx(NEW_ID, {port.clk, SigSpec(past_clk)}, clock_edge_pattern); + SigSpec clock_edge = module->Eqx(NEWER_ID, {port.clk, SigSpec(past_clk)}, clock_edge_pattern); - SigSpec en_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#en_q", log_id(mem.memid), i)), GetSize(port.en)); - module->addFf(NEW_ID, port.en, en_q); + SigSpec en_q = module->addWire(NEWER_ID_SUFFIX(stringf("%s#%d#en_q", log_id(mem.memid), i)), GetSize(port.en)); + module->addFf(NEWER_ID, port.en, en_q); - SigSpec addr_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#addr_q", log_id(mem.memid), i)), GetSize(port.addr)); - module->addFf(NEW_ID, port.addr, addr_q); + SigSpec addr_q = module->addWire(NEWER_ID_SUFFIX(stringf("%s#%d#addr_q", log_id(mem.memid), i)), GetSize(port.addr)); + module->addFf(NEWER_ID, port.addr, addr_q); - SigSpec data_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#data_q", log_id(mem.memid), i)), GetSize(port.data)); - module->addFf(NEW_ID, port.data, data_q); + SigSpec data_q = module->addWire(NEWER_ID_SUFFIX(stringf("%s#%d#data_q", log_id(mem.memid), i)), GetSize(port.data)); + module->addFf(NEWER_ID, port.data, data_q); port.clk = State::S0; - port.en = module->Mux(NEW_ID, Const(0, GetSize(en_q)), en_q, clock_edge); + port.en = module->Mux(NEWER_ID, Const(0, GetSize(en_q)), en_q, clock_edge); port.addr = addr_q; port.data = data_q; @@ -237,10 +237,10 @@ struct Clk2fflogicPass : public Pass { if (trg_width == 0) { if (initstate == State::S0) - initstate = module->Initstate(NEW_ID); + initstate = module->Initstate(NEWER_ID); SigBit sig_en = cell->getPort(ID::EN); - cell->setPort(ID::EN, module->And(NEW_ID, sig_en, initstate)); + cell->setPort(ID::EN, module->And(NEWER_ID, sig_en, initstate)); } else { SigBit sig_en = cell->getPort(ID::EN); SigSpec sig_args = cell->getPort(ID::ARGS); @@ -254,9 +254,9 @@ struct Clk2fflogicPass : public Pass { SigSpec sig_args_sampled = sample_data(module, sig_args, Const(State::S0, GetSize(sig_args)), false, false).sampled; SigBit sig_en_sampled = sample_data(module, sig_en, State::S0, false, false).sampled; - SigBit sig_trg_combined = module->ReduceOr(NEW_ID, sig_trg_sampled); + SigBit sig_trg_combined = module->ReduceOr(NEWER_ID, sig_trg_sampled); - cell->setPort(ID::EN, module->And(NEW_ID, sig_en_sampled, sig_trg_combined)); + cell->setPort(ID::EN, module->And(NEWER_ID, sig_en_sampled, sig_trg_combined)); cell->setPort(ID::ARGS, sig_args_sampled); if (cell->type == ID($check)) { SigBit sig_a = cell->getPort(ID::A); diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc index 7522d716e82..056381de842 100644 --- a/passes/sat/cutpoint.cc +++ b/passes/sat/cutpoint.cc @@ -102,7 +102,7 @@ struct CutpointPass : public Pass { if (wire->port_output) output_wires.push_back(wire); for (auto wire : output_wires) - module->connect(wire, flag_undef ? Const(State::Sx, GetSize(wire)) : module->Anyseq(NEW_ID, GetSize(wire))); + module->connect(wire, flag_undef ? Const(State::Sx, GetSize(wire)) : module->Anyseq(NEWER_ID, GetSize(wire))); continue; } @@ -115,13 +115,13 @@ struct CutpointPass : public Pass { log("Removing cell %s.%s, making all cell outputs cutpoints.\n", log_id(module), log_id(cell)); for (auto &conn : cell->connections()) { if (cell->output(conn.first)) - module->connect(conn.second, flag_undef ? Const(State::Sx, GetSize(conn.second)) : module->Anyseq(NEW_ID, GetSize(conn.second))); + module->connect(conn.second, flag_undef ? Const(State::Sx, GetSize(conn.second)) : module->Anyseq(NEWER_ID, GetSize(conn.second))); } RTLIL::Cell *scopeinfo = nullptr; auto cell_name = cell->name; if (flag_scopeinfo && cell_name.isPublic()) { - auto scopeinfo = module->addCell(NEW_ID, ID($scopeinfo)); + auto scopeinfo = module->addCell(NEWER_ID, ID($scopeinfo)); scopeinfo->setParam(ID::TYPE, RTLIL::Const("blackbox")); for (auto const &attr : cell->attributes) @@ -142,9 +142,9 @@ struct CutpointPass : public Pass { for (auto wire : module->selected_wires()) { if (wire->port_output) { log("Making output wire %s.%s a cutpoint.\n", log_id(module), log_id(wire)); - Wire *new_wire = module->addWire(NEW_ID, wire); + Wire *new_wire = module->addWire(NEWER_ID, wire); module->swap_names(wire, new_wire); - module->connect(new_wire, flag_undef ? Const(State::Sx, GetSize(new_wire)) : module->Anyseq(NEW_ID, GetSize(new_wire))); + module->connect(new_wire, flag_undef ? Const(State::Sx, GetSize(new_wire)) : module->Anyseq(NEWER_ID, GetSize(new_wire))); wire->port_id = 0; wire->port_input = false; wire->port_output = false; @@ -169,7 +169,7 @@ struct CutpointPass : public Pass { } if (bit_count == 0) continue; - SigSpec dummy = module->addWire(NEW_ID, bit_count); + SigSpec dummy = module->addWire(NEWER_ID, bit_count); bit_count = 0; for (auto &bit : sig) { if (cutpoint_bits.count(bit)) @@ -193,7 +193,7 @@ struct CutpointPass : public Pass { } for (auto wire : rewrite_wires) { - Wire *new_wire = module->addWire(NEW_ID, wire); + Wire *new_wire = module->addWire(NEWER_ID, wire); SigSpec lhs, rhs, sig = sigmap(wire); for (int i = 0; i < GetSize(sig); i++) if (!cutpoint_bits.count(sig[i])) { @@ -213,7 +213,7 @@ struct CutpointPass : public Pass { for (auto chunk : sig.chunks()) { SigSpec s(chunk); - module->connect(s, flag_undef ? Const(State::Sx, GetSize(s)) : module->Anyseq(NEW_ID, GetSize(s))); + module->connect(s, flag_undef ? Const(State::Sx, GetSize(s)) : module->Anyseq(NEWER_ID, GetSize(s))); } } } diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 1e975db0fd1..9f48a09928e 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -472,7 +472,7 @@ struct ExposePass : public Pass { if (!w->port_input) { w->port_input = true; log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name)); - wire_map[w] = NEW_ID; + wire_map[w] = NEWER_ID; } } else @@ -542,7 +542,7 @@ struct ExposePass : public Pass { dff_map_info_t &info = dq.second; - RTLIL::Wire *wire_dummy_q = add_new_wire(module, NEW_ID, 0); + RTLIL::Wire *wire_dummy_q = add_new_wire(module, NEWER_ID, 0); for (auto &cell_name : info.cells) { RTLIL::Cell *cell = module->cell(cell_name); @@ -578,7 +578,7 @@ struct ExposePass : public Pass { if (info.clk_polarity) { module->connect(RTLIL::SigSig(wire_c, info.sig_clk)); } else { - RTLIL::Cell *c = module->addCell(NEW_ID, ID($not)); + RTLIL::Cell *c = module->addCell(NEWER_ID, ID($not)); c->parameters[ID::A_SIGNED] = 0; c->parameters[ID::A_WIDTH] = 1; c->parameters[ID::Y_WIDTH] = 1; @@ -594,7 +594,7 @@ struct ExposePass : public Pass { if (info.arst_polarity) { module->connect(RTLIL::SigSig(wire_r, info.sig_arst)); } else { - RTLIL::Cell *c = module->addCell(NEW_ID, ID($not)); + RTLIL::Cell *c = module->addCell(NEWER_ID, ID($not)); c->parameters[ID::A_SIGNED] = 0; c->parameters[ID::A_WIDTH] = 1; c->parameters[ID::Y_WIDTH] = 1; diff --git a/passes/sat/fmcombine.cc b/passes/sat/fmcombine.cc index 2d31822c4fa..b72df957336 100644 --- a/passes/sat/fmcombine.cc +++ b/passes/sat/fmcombine.cc @@ -121,9 +121,9 @@ struct FmcombineWorker if (RTLIL::builtin_ff_cell_types().count(cell->type)) { SigSpec gold_q = gold->getPort(ID::Q); SigSpec gate_q = gate->getPort(ID::Q); - SigSpec en = module->Initstate(NEW_ID); - SigSpec eq = module->Eq(NEW_ID, gold_q, gate_q); - module->addAssume(NEW_ID, eq, en); + SigSpec en = module->Initstate(NEWER_ID); + SigSpec eq = module->Eq(NEWER_ID, gold_q, gate_q); + module->addAssume(NEWER_ID, eq, en); } } } @@ -163,7 +163,7 @@ struct FmcombineWorker SigSpec A = import_sig(conn.second, "_gold"); SigSpec B = import_sig(conn.second, "_gate"); - SigBit EQ = module->Eq(NEW_ID, A, B); + SigBit EQ = module->Eq(NEWER_ID, A, B); for (auto bit : sigmap({A, B})) data_bit_to_eq_net[bit] = EQ; @@ -205,7 +205,7 @@ struct FmcombineWorker if (GetSize(antecedent) > 1) { if (reduce_db.count(antecedent) == 0) - reduce_db[antecedent] = module->ReduceAnd(NEW_ID, antecedent); + reduce_db[antecedent] = module->ReduceAnd(NEWER_ID, antecedent); antecedent = reduce_db.at(antecedent); } @@ -214,22 +214,22 @@ struct FmcombineWorker if (GetSize(consequent) > 1) { if (reduce_db.count(consequent) == 0) - reduce_db[consequent] = module->ReduceAnd(NEW_ID, consequent); + reduce_db[consequent] = module->ReduceAnd(NEWER_ID, consequent); consequent = reduce_db.at(consequent); } if (opts.fwd) - module->addAssume(NEW_ID, consequent, antecedent); + module->addAssume(NEWER_ID, consequent, antecedent); if (opts.bwd) { if (invert_db.count(antecedent) == 0) - invert_db[antecedent] = module->Not(NEW_ID, antecedent); + invert_db[antecedent] = module->Not(NEWER_ID, antecedent); if (invert_db.count(consequent) == 0) - invert_db[consequent] = module->Not(NEW_ID, consequent); + invert_db[consequent] = module->Not(NEWER_ID, consequent); - module->addAssume(NEW_ID, invert_db.at(antecedent), invert_db.at(consequent)); + module->addAssume(NEWER_ID, invert_db.at(antecedent), invert_db.at(consequent)); } } } diff --git a/passes/sat/fminit.cc b/passes/sat/fminit.cc index 4627a6c96b3..591302c3bdb 100644 --- a/passes/sat/fminit.cc +++ b/passes/sat/fminit.cc @@ -131,8 +131,8 @@ struct FminitPass : public Pass { } if (!final_lhs.empty()) { - SigSpec eq = module->Eq(NEW_ID, final_lhs, final_rhs); - module->addAssume(NEW_ID, eq, State::S1); + SigSpec eq = module->Eq(NEWER_ID, final_lhs, final_rhs); + module->addAssume(NEWER_ID, eq, State::S1); } } @@ -152,13 +152,13 @@ struct FminitPass : public Pass { { SigSpec insig = i > 0 ? ctrlsig.at(i-1) : State::S0; - Wire *outwire = module->addWire(NEW_ID); + Wire *outwire = module->addWire(NEWER_ID); outwire->attributes[ID::init] = i > 0 ? State::S0 : State::S1; if (clksig.empty()) - module->addFf(NEW_ID, insig, outwire); + module->addFf(NEWER_ID, insig, outwire); else - module->addDff(NEW_ID, clksig, insig, outwire, clockedge); + module->addDff(NEWER_ID, clksig, insig, outwire, clockedge); ctrlsig.push_back(outwire); ctrlsig_latched.push_back(SigSpec()); @@ -166,14 +166,14 @@ struct FminitPass : public Pass { if (i+1 == GetSize(it.second) && ctrlsig_latched[i].empty()) { - Wire *ffwire = module->addWire(NEW_ID); + Wire *ffwire = module->addWire(NEWER_ID); ffwire->attributes[ID::init] = State::S0; - SigSpec outsig = module->Or(NEW_ID, ffwire, ctrlsig[i]); + SigSpec outsig = module->Or(NEWER_ID, ffwire, ctrlsig[i]); if (clksig.empty()) - module->addFf(NEW_ID, outsig, ffwire); + module->addFf(NEWER_ID, outsig, ffwire); else - module->addDff(NEW_ID, clksig, outsig, ffwire, clockedge); + module->addDff(NEWER_ID, clksig, outsig, ffwire, clockedge); ctrlsig_latched[i] = outsig; } @@ -192,8 +192,8 @@ struct FminitPass : public Pass { } if (!final_lhs.empty()) { - SigSpec eq = module->Eq(NEW_ID, final_lhs, final_rhs); - module->addAssume(NEW_ID, eq, ctrl); + SigSpec eq = module->Eq(NEWER_ID, final_lhs, final_rhs); + module->addAssume(NEWER_ID, eq, ctrl); } } } diff --git a/passes/sat/formalff.cc b/passes/sat/formalff.cc index c0b0cfc1517..14040a1edfb 100644 --- a/passes/sat/formalff.cc +++ b/passes/sat/formalff.cc @@ -420,7 +420,7 @@ struct PropagateWorker replaced_clk_inputs.emplace_back(ReplacedPort {port, i, it->second}); if (it->second) { - bit = module->Not(NEW_ID, bit); + bit = module->Not(NEWER_ID, bit); } } } @@ -445,7 +445,7 @@ struct PropagateWorker if (add_attribute) { Wire *clk_wire = bit.wire; if (bit.offset != 0 || GetSize(bit.wire) != 1) { - clk_wire = module->addWire(NEW_ID); + clk_wire = module->addWire(NEWER_ID); module->connect(RTLIL::SigBit(clk_wire), bit); } clk_wire->attributes[ID::replaced_by_gclk] = polarity ? State::S1 : State::S0; @@ -802,9 +802,9 @@ struct FormalFfPass : public Pass { log_debug("patching rd port\n"); changed = true; rd_port.clk = gate_clock; - SigBit en_bit = pol_clk ? sig_gate : SigBit(module->Not(NEW_ID, sig_gate)); + SigBit en_bit = pol_clk ? sig_gate : SigBit(module->Not(NEWER_ID, sig_gate)); SigSpec en_mask = SigSpec(en_bit, GetSize(rd_port.en)); - rd_port.en = module->And(NEW_ID, rd_port.en, en_mask); + rd_port.en = module->And(NEWER_ID, rd_port.en, en_mask); } } for (auto &wr_port : mem.wr_ports) { @@ -812,9 +812,9 @@ struct FormalFfPass : public Pass { log_debug("patching wr port\n"); changed = true; wr_port.clk = gate_clock; - SigBit en_bit = pol_clk ? sig_gate : SigBit(module->Not(NEW_ID, sig_gate)); + SigBit en_bit = pol_clk ? sig_gate : SigBit(module->Not(NEWER_ID, sig_gate)); SigSpec en_mask = SigSpec(en_bit, GetSize(wr_port.en)); - wr_port.en = module->And(NEW_ID, wr_port.en, en_mask); + wr_port.en = module->And(NEWER_ID, wr_port.en, en_mask); } } if (changed) @@ -900,7 +900,7 @@ struct FormalFfPass : public Pass { auto clk_wire = ff.sig_clk.is_wire() ? ff.sig_clk.as_wire() : nullptr; if (clk_wire == nullptr) { - clk_wire = module->addWire(NEW_ID); + clk_wire = module->addWire(NEWER_ID); module->connect(RTLIL::SigBit(clk_wire), ff.sig_clk); } @@ -982,9 +982,9 @@ struct FormalFfPass : public Pass { SigBit clk = pair.first; if (pair.second) - clk = module->Not(NEW_ID, clk); + clk = module->Not(NEWER_ID, clk); - module->addAssume(NEW_ID, clk, State::S1); + module->addAssume(NEWER_ID, clk, State::S1); } } diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 4b0669c25ce..249f3f17b41 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -716,7 +716,7 @@ struct FreduceWorker log(" Connect slave%s: %s\n", grp[i].inverted ? " using inverter" : "", log_signal(grp[i].bit)); RTLIL::Cell *drv = drivers.at(grp[i].bit).first; - RTLIL::Wire *dummy_wire = module->addWire(NEW_ID); + RTLIL::Wire *dummy_wire = module->addWire(NEWER_ID); for (auto &port : drv->connections_) if (ct.cell_output(drv->type, port.first)) sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second); @@ -725,9 +725,9 @@ struct FreduceWorker { if (inv_sig.size() == 0) { - inv_sig = module->addWire(NEW_ID); + inv_sig = module->addWire(NEWER_ID); - RTLIL::Cell *inv_cell = module->addCell(NEW_ID, ID($_NOT_)); + RTLIL::Cell *inv_cell = module->addCell(NEWER_ID, ID($_NOT_)); inv_cell->setPort(ID::A, grp[0].bit); inv_cell->setPort(ID::Y, inv_sig); } diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 9bcf25547e4..38bd5e91d5a 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -146,12 +146,12 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: SigSpec w = miter_module->addWire("\\cross_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width); gold_cell->setPort(gold_wire->name, w); if (flag_ignore_gold_x) { - RTLIL::SigSpec w_x = miter_module->addWire(NEW_ID, GetSize(w)); + RTLIL::SigSpec w_x = miter_module->addWire(NEWER_ID, GetSize(w)); for (int i = 0; i < GetSize(w); i++) - miter_module->addEqx(NEW_ID, w[i], State::Sx, w_x[i]); - RTLIL::SigSpec w_any = miter_module->And(NEW_ID, miter_module->Anyseq(NEW_ID, GetSize(w)), w_x); - RTLIL::SigSpec w_masked = miter_module->And(NEW_ID, w, miter_module->Not(NEW_ID, w_x)); - w = miter_module->And(NEW_ID, w_any, w_masked); + miter_module->addEqx(NEWER_ID, w[i], State::Sx, w_x[i]); + RTLIL::SigSpec w_any = miter_module->And(NEWER_ID, miter_module->Anyseq(NEWER_ID, GetSize(w)), w_x); + RTLIL::SigSpec w_masked = miter_module->And(NEWER_ID, w, miter_module->Not(NEWER_ID, w_x)); + w = miter_module->And(NEWER_ID, w_any, w_masked); } gate_cell->setPort(gold_wire->name, w); continue; @@ -181,9 +181,9 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: if (flag_ignore_gold_x) { - RTLIL::SigSpec gold_x = miter_module->addWire(NEW_ID, w_gold->width); + RTLIL::SigSpec gold_x = miter_module->addWire(NEWER_ID, w_gold->width); for (int i = 0; i < w_gold->width; i++) { - RTLIL::Cell *eqx_cell = miter_module->addCell(NEW_ID, ID($eqx)); + RTLIL::Cell *eqx_cell = miter_module->addCell(NEWER_ID, ID($eqx)); eqx_cell->parameters[ID::A_WIDTH] = 1; eqx_cell->parameters[ID::B_WIDTH] = 1; eqx_cell->parameters[ID::Y_WIDTH] = 1; @@ -194,10 +194,10 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: eqx_cell->setPort(ID::Y, gold_x.extract(i, 1)); } - RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w_gold->width); - RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_ID, w_gate->width); + RTLIL::SigSpec gold_masked = miter_module->addWire(NEWER_ID, w_gold->width); + RTLIL::SigSpec gate_masked = miter_module->addWire(NEWER_ID, w_gate->width); - RTLIL::Cell *or_gold_cell = miter_module->addCell(NEW_ID, ID($or)); + RTLIL::Cell *or_gold_cell = miter_module->addCell(NEWER_ID, ID($or)); or_gold_cell->parameters[ID::A_WIDTH] = w_gold->width; or_gold_cell->parameters[ID::B_WIDTH] = w_gold->width; or_gold_cell->parameters[ID::Y_WIDTH] = w_gold->width; @@ -207,7 +207,7 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: or_gold_cell->setPort(ID::B, gold_x); or_gold_cell->setPort(ID::Y, gold_masked); - RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, ID($or)); + RTLIL::Cell *or_gate_cell = miter_module->addCell(NEWER_ID, ID($or)); or_gate_cell->parameters[ID::A_WIDTH] = w_gate->width; or_gate_cell->parameters[ID::B_WIDTH] = w_gate->width; or_gate_cell->parameters[ID::Y_WIDTH] = w_gate->width; @@ -217,7 +217,7 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: or_gate_cell->setPort(ID::B, gold_x); or_gate_cell->setPort(ID::Y, gate_masked); - RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, ID($eqx)); + RTLIL::Cell *eq_cell = miter_module->addCell(NEWER_ID, ID($eqx)); eq_cell->parameters[ID::A_WIDTH] = w_gold->width; eq_cell->parameters[ID::B_WIDTH] = w_gate->width; eq_cell->parameters[ID::Y_WIDTH] = 1; @@ -225,12 +225,12 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: eq_cell->parameters[ID::B_SIGNED] = 0; eq_cell->setPort(ID::A, gold_masked); eq_cell->setPort(ID::B, gate_masked); - eq_cell->setPort(ID::Y, miter_module->addWire(NEW_ID)); + eq_cell->setPort(ID::Y, miter_module->addWire(NEWER_ID)); this_condition = eq_cell->getPort(ID::Y); } else { - RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, ID($eqx)); + RTLIL::Cell *eq_cell = miter_module->addCell(NEWER_ID, ID($eqx)); eq_cell->parameters[ID::A_WIDTH] = w_gold->width; eq_cell->parameters[ID::B_WIDTH] = w_gate->width; eq_cell->parameters[ID::Y_WIDTH] = 1; @@ -238,7 +238,7 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: eq_cell->parameters[ID::B_SIGNED] = 0; eq_cell->setPort(ID::A, w_gold); eq_cell->setPort(ID::B, w_gate); - eq_cell->setPort(ID::Y, miter_module->addWire(NEW_ID)); + eq_cell->setPort(ID::Y, miter_module->addWire(NEWER_ID)); this_condition = eq_cell->getPort(ID::Y); } @@ -251,7 +251,7 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: if (flag_make_cover) { - auto cover_condition = miter_module->Not(NEW_ID, this_condition); + auto cover_condition = miter_module->Not(NEWER_ID, this_condition); miter_module->addCover("\\cover_" + RTLIL::unescape_id(gold_wire->name), cover_condition, State::S1); } @@ -260,17 +260,17 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: } if (all_conditions.size() != 1) { - RTLIL::Cell *reduce_cell = miter_module->addCell(NEW_ID, ID($reduce_and)); + RTLIL::Cell *reduce_cell = miter_module->addCell(NEWER_ID, ID($reduce_and)); reduce_cell->parameters[ID::A_WIDTH] = all_conditions.size(); reduce_cell->parameters[ID::Y_WIDTH] = 1; reduce_cell->parameters[ID::A_SIGNED] = 0; reduce_cell->setPort(ID::A, all_conditions); - reduce_cell->setPort(ID::Y, miter_module->addWire(NEW_ID)); + reduce_cell->setPort(ID::Y, miter_module->addWire(NEWER_ID)); all_conditions = reduce_cell->getPort(ID::Y); } if (flag_make_assert) { - RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, ID($assert)); + RTLIL::Cell *assert_cell = miter_module->addCell(NEWER_ID, ID($assert)); assert_cell->setPort(ID::A, all_conditions); assert_cell->setPort(ID::EN, State::S1); } @@ -278,7 +278,7 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: RTLIL::Wire *w_trigger = miter_module->addWire(ID(trigger)); w_trigger->port_output = true; - RTLIL::Cell *not_cell = miter_module->addCell(NEW_ID, ID($not)); + RTLIL::Cell *not_cell = miter_module->addCell(NEWER_ID, ID($not)); not_cell->parameters[ID::A_WIDTH] = all_conditions.size(); not_cell->parameters[ID::A_WIDTH] = all_conditions.size(); not_cell->parameters[ID::Y_WIDTH] = w_trigger->width; @@ -355,13 +355,13 @@ void create_miter_assert(struct Pass *that, std::vector args, RTLIL if (!cell->type.in(ID($assert), ID($assume))) continue; - SigBit is_active = module->Nex(NEW_ID, cell->getPort(ID::A), State::S1); - SigBit is_enabled = module->Eqx(NEW_ID, cell->getPort(ID::EN), State::S1); + SigBit is_active = module->Nex(NEWER_ID, cell->getPort(ID::A), State::S1); + SigBit is_enabled = module->Eqx(NEWER_ID, cell->getPort(ID::EN), State::S1); if (cell->type == ID($assert)) { - assert_signals.append(module->And(NEW_ID, is_active, is_enabled)); + assert_signals.append(module->And(NEWER_ID, is_active, is_enabled)); } else { - assume_signals.append(module->And(NEW_ID, is_active, is_enabled)); + assume_signals.append(module->And(NEWER_ID, is_active, is_enabled)); } module->remove(cell); @@ -369,20 +369,20 @@ void create_miter_assert(struct Pass *that, std::vector args, RTLIL if (assume_signals.empty()) { - module->addReduceOr(NEW_ID, assert_signals, trigger); + module->addReduceOr(NEWER_ID, assert_signals, trigger); } else { - Wire *assume_q = module->addWire(NEW_ID); + Wire *assume_q = module->addWire(NEWER_ID); assume_q->attributes[ID::init] = State::S0; assume_signals.append(assume_q); - SigSpec assume_nok = module->ReduceOr(NEW_ID, assume_signals); - SigSpec assume_ok = module->Not(NEW_ID, assume_nok); - module->addFf(NEW_ID, assume_nok, assume_q); + SigSpec assume_nok = module->ReduceOr(NEWER_ID, assume_signals); + SigSpec assume_ok = module->Not(NEWER_ID, assume_nok); + module->addFf(NEWER_ID, assume_nok, assume_q); - SigSpec assert_fail = module->ReduceOr(NEW_ID, assert_signals); - module->addAnd(NEW_ID, assert_fail, assume_ok, trigger); + SigSpec assert_fail = module->ReduceOr(NEWER_ID, assert_signals); + module->addAnd(NEWER_ID, assert_fail, assume_ok, trigger); } if (flag_flatten) { diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc index 58d932f201d..24e4a6af1cc 100644 --- a/passes/sat/mutate.cc +++ b/passes/sat/mutate.cc @@ -629,7 +629,7 @@ SigBit mutate_ctrl(Module *module, const mutate_opts_t &opts) return State::S1; SigSpec sig = mutate_ctrl_sig(module, opts.ctrl_name, opts.ctrl_width); - return module->Eq(NEW_ID, sig, Const(opts.ctrl_value, GetSize(sig))); + return module->Eq(NEWER_ID, sig, Const(opts.ctrl_value, GetSize(sig))); } SigSpec mutate_ctrl_mux(Module *module, const mutate_opts_t &opts, SigSpec unchanged_sig, SigSpec changed_sig) @@ -639,7 +639,7 @@ SigSpec mutate_ctrl_mux(Module *module, const mutate_opts_t &opts, SigSpec uncha return unchanged_sig; if (ctrl_bit == State::S1) return changed_sig; - return module->Mux(NEW_ID, unchanged_sig, changed_sig, ctrl_bit); + return module->Mux(NEWER_ID, unchanged_sig, changed_sig, ctrl_bit); } void mutate_inv(Design *design, const mutate_opts_t &opts) @@ -653,14 +653,14 @@ void mutate_inv(Design *design, const mutate_opts_t &opts) if (cell->input(opts.port)) { log("Add input inverter at %s.%s.%s[%d].\n", log_id(module), log_id(cell), log_id(opts.port), opts.portbit); - SigBit outbit = module->Not(NEW_ID, bit); + SigBit outbit = module->Not(NEWER_ID, bit); bit = mutate_ctrl_mux(module, opts, bit, outbit); } else { log("Add output inverter at %s.%s.%s[%d].\n", log_id(module), log_id(cell), log_id(opts.port), opts.portbit); - SigBit inbit = module->addWire(NEW_ID); - SigBit outbit = module->Not(NEW_ID, inbit); + SigBit inbit = module->addWire(NEWER_ID); + SigBit outbit = module->Not(NEWER_ID, inbit); module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit)); bit = inbit; } @@ -687,7 +687,7 @@ void mutate_const(Design *design, const mutate_opts_t &opts, bool one) else { log("Add output constant %d at %s.%s.%s[%d].\n", one ? 1 : 0, log_id(module), log_id(cell), log_id(opts.port), opts.portbit); - SigBit inbit = module->addWire(NEW_ID); + SigBit inbit = module->addWire(NEWER_ID); SigBit outbit = one ? State::S1 : State::S0; module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit)); bit = inbit; @@ -710,14 +710,14 @@ void mutate_cnot(Design *design, const mutate_opts_t &opts, bool one) if (cell->input(opts.port)) { log("Add input cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, log_id(module), log_id(cell), log_id(opts.port), opts.portbit, opts.ctrlbit); - SigBit outbit = one ? module->Xor(NEW_ID, bit, ctrl) : module->Xnor(NEW_ID, bit, ctrl); + SigBit outbit = one ? module->Xor(NEWER_ID, bit, ctrl) : module->Xnor(NEWER_ID, bit, ctrl); bit = mutate_ctrl_mux(module, opts, bit, outbit); } else { log("Add output cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, log_id(module), log_id(cell), log_id(opts.port), opts.portbit, opts.ctrlbit); - SigBit inbit = module->addWire(NEW_ID); - SigBit outbit = one ? module->Xor(NEW_ID, inbit, ctrl) : module->Xnor(NEW_ID, inbit, ctrl); + SigBit inbit = module->addWire(NEWER_ID); + SigBit outbit = one ? module->Xor(NEWER_ID, inbit, ctrl) : module->Xnor(NEWER_ID, inbit, ctrl); module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit)); bit = inbit; } diff --git a/passes/sat/qbfsat.cc b/passes/sat/qbfsat.cc index 20cee795646..c238a3d4c05 100644 --- a/passes/sat/qbfsat.cc +++ b/passes/sat/qbfsat.cc @@ -312,8 +312,8 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) { if (cur_thresh != 0) { //Add thresholding logic (but not on the initial run when we don't have a sense of where to start): - RTLIL::SigSpec comparator = maximize? module->Ge(NEW_ID, module->wire(wire_to_optimize_name), RTLIL::Const(cur_thresh), false) - : module->Le(NEW_ID, module->wire(wire_to_optimize_name), RTLIL::Const(cur_thresh), false); + RTLIL::SigSpec comparator = maximize? module->Ge(NEWER_ID, module->wire(wire_to_optimize_name), RTLIL::Const(cur_thresh), false) + : module->Le(NEWER_ID, module->wire(wire_to_optimize_name), RTLIL::Const(cur_thresh), false); module->addAssume(wire_to_optimize_name.str() + "__threshold", comparator, RTLIL::Const(1, 1)); log("Trying to solve with %s %s %d.\n", wire_to_optimize_name, (maximize? ">=" : "<="), cur_thresh); diff --git a/passes/sat/recover_names.cc b/passes/sat/recover_names.cc index 7939a64e05a..4640b48b18d 100644 --- a/passes/sat/recover_names.cc +++ b/passes/sat/recover_names.cc @@ -95,7 +95,7 @@ struct RecoverModuleWorker { { // Create a derivative of the module with whiteboxes flattened so we can // run eval and sat on it - flat = design->addModule(NEW_ID); + flat = design->addModule(NEWER_ID); mod->cloneInto(flat); Pass::call_on_module(design, flat, "flatten -wb"); ce = new ConstEval(flat); diff --git a/passes/sat/supercover.cc b/passes/sat/supercover.cc index f1b3ad09c06..1d71c11fe04 100644 --- a/passes/sat/supercover.cc +++ b/passes/sat/supercover.cc @@ -78,9 +78,9 @@ struct SupercoverPass : public Pass { if (handled_bits.count(bit)) continue; - SigSpec inv = module->Not(NEW_ID, bit); - module->addCover(NEW_ID, bit, State::S1, src); - module->addCover(NEW_ID, inv, State::S1, src); + SigSpec inv = module->Not(NEWER_ID, bit); + module->addCover(NEWER_ID, bit, State::S1, src); + module->addCover(NEWER_ID, inv, State::S1, src); handled_bits.insert(bit); if (!counted_wire) { diff --git a/passes/sat/synthprop.cc b/passes/sat/synthprop.cc index d94b4a7f796..740a3a9cb46 100644 --- a/passes/sat/synthprop.cc +++ b/passes/sat/synthprop.cc @@ -107,16 +107,16 @@ void SynthPropWorker::run() int num = 0; RTLIL::Wire *port_wire = data.first->wire(port_name); if (!reset_name.empty() && data.first == module) { - port_wire = data.first->addWire(NEW_ID, data.second.names.size()); + port_wire = data.first->addWire(NEWER_ID, data.second.names.size()); output = port_wire; } pool connected; for (auto cell : data.second.assertion_cells) { if (cell->type == ID($assert)) { - RTLIL::Wire *neg_wire = data.first->addWire(NEW_ID); - RTLIL::Wire *result_wire = data.first->addWire(NEW_ID); - data.first->addNot(NEW_ID, cell->getPort(ID::A), neg_wire); - data.first->addAnd(NEW_ID, cell->getPort(ID::EN), neg_wire, result_wire); + RTLIL::Wire *neg_wire = data.first->addWire(NEWER_ID); + RTLIL::Wire *result_wire = data.first->addWire(NEWER_ID); + data.first->addNot(NEWER_ID, cell->getPort(ID::A), neg_wire); + data.first->addAnd(NEWER_ID, cell->getPort(ID::EN), neg_wire, result_wire); if (!or_outputs) { data.first->connect(SigBit(port_wire,num), result_wire); } else { @@ -132,7 +132,7 @@ void SynthPropWorker::run() if (!or_outputs) { cell->setPort(port_name, SigChunk(port_wire, num, tracing_data[submod].names.size())); } else { - RTLIL::Wire *result_wire = data.first->addWire(NEW_ID); + RTLIL::Wire *result_wire = data.first->addWire(NEWER_ID); cell->setPort(port_name, result_wire); connected.emplace(result_wire); } @@ -146,8 +146,8 @@ void SynthPropWorker::run() if (!prev_wire) { prev_wire = wire; } else { - RTLIL::Wire *result = data.first->addWire(NEW_ID); - data.first->addOr(NEW_ID, prev_wire, wire, result); + RTLIL::Wire *result = data.first->addWire(NEWER_ID); + data.first->addOr(NEWER_ID, prev_wire, wire, result); prev_wire = result; } } @@ -163,7 +163,7 @@ void SynthPropWorker::run() SigSpec reset = module->wire(reset_name); reset.extend_u0(width, true); - module->addDlatchsr(NEW_ID, State::S1, Const(State::S0,width), reset, output, module->wire(port_name), true, true, reset_pol); + module->addDlatchsr(NEWER_ID, State::S1, Const(State::S0,width), reset, output, module->wire(port_name), true, true, reset_pol); } if (!map_file.empty()) { diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 069b94204f9..65ca93a824d 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -344,7 +344,7 @@ void prep_bypass(RTLIL::Design *design) // For these new input ports driven by the replaced // cell, then create a new simple-path specify entry: // (input => output) = 0 - auto specify = bypass_module->addCell(NEW_ID, ID($specify2)); + auto specify = bypass_module->addCell(NEWER_ID, ID($specify2)); specify->setPort(ID::EN, State::S1); specify->setPort(ID::SRC, src); specify->setPort(ID::DST, dst); @@ -405,7 +405,7 @@ void prep_bypass(RTLIL::Design *design) } sig = std::move(new_sig); }; - auto specify = bypass_module->addCell(NEW_ID, cell); + auto specify = bypass_module->addCell(NEWER_ID, cell); specify->rewrite_sigspecs(rw); } bypass_module->fixup_ports(); @@ -415,7 +415,7 @@ void prep_bypass(RTLIL::Design *design) // original cell, but with additional inputs taken from the // replaced cell auto replace_cell = map_module->addCell(ID::_TECHMAP_REPLACE_, cell->type); - auto bypass_cell = map_module->addCell(NEW_ID, cell->type.str() + "_$abc9_byp"); + auto bypass_cell = map_module->addCell(NEWER_ID, cell->type.str() + "_$abc9_byp"); for (const auto &conn : cell->connections()) { auto port = map_module->wire(conn.first); if (cell->input(conn.first)) { @@ -503,8 +503,8 @@ void prep_dff_submod(RTLIL::Design *design) // Add an always-enabled CE mux that drives $_DFF_[NP]_.D so that: // (a) flop box will have an output // (b) $_DFF_[NP]_.Q will be present as an input - SigBit D = module->addWire(NEW_ID); - module->addMuxGate(NEW_ID, dff_cell->getPort(ID::D), Q, State::S0, D); + SigBit D = module->addWire(NEWER_ID); + module->addMuxGate(NEWER_ID, dff_cell->getPort(ID::D), Q, State::S0, D); dff_cell->setPort(ID::D, D); // Rewrite $specify cells that end with $_DFF_[NP]_.Q @@ -592,7 +592,7 @@ void break_scc(RTLIL::Module *module) for (auto &c : cell->connections_) { if (c.second.is_fully_const()) continue; if (cell->output(c.first)) { - Wire *w = module->addWire(NEW_ID, GetSize(c.second)); + Wire *w = module->addWire(NEWER_ID, GetSize(c.second)); I.append(w); O.append(c.second); c.second = w; @@ -602,7 +602,7 @@ void break_scc(RTLIL::Module *module) if (!I.empty()) { - auto cell = module->addCell(NEW_ID, ID($__ABC9_SCC_BREAKER)); + auto cell = module->addCell(NEWER_ID, ID($__ABC9_SCC_BREAKER)); log_assert(GetSize(I) == GetSize(O)); cell->setParam(ID::WIDTH, GetSize(I)); cell->setPort(ID::I, std::move(I)); @@ -680,7 +680,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode) auto rhs = cell->getPort(i.first.name); if (offset >= rhs.size()) continue; - auto O = module->addWire(NEW_ID); + auto O = module->addWire(NEWER_ID); #ifndef NDEBUG if (ys_debug(1)) { @@ -694,7 +694,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode) r.first->second = delay_module->derive(design, {{ID::DELAY, d}}); log_assert(r.first->second.begins_with("$paramod$__ABC9_DELAY\\DELAY=")); } - auto box = module->addCell(NEW_ID, r.first->second); + auto box = module->addCell(NEWER_ID, r.first->second); box->setPort(ID::I, rhs[offset]); box->setPort(ID::O, O); rhs[offset] = O; @@ -831,7 +831,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff) auto &holes_cell = r.first->second; if (r.second) { if (box_module->get_bool_attribute(ID::whitebox)) { - holes_cell = holes_module->addCell(NEW_ID, cell->type); + holes_cell = holes_module->addCell(NEWER_ID, cell->type); if (box_module->has_processes()) Pass::call_on_module(design, box_module, "proc -noopt"); @@ -1256,7 +1256,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode) bit_drivers[y_bit].insert(mapped_cell->name); if (!a_bit.wire) { - mapped_cell->setPort(ID::Y, module->addWire(NEW_ID)); + mapped_cell->setPort(ID::Y, module->addWire(NEWER_ID)); RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name)); log_assert(wire); module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1); @@ -1549,7 +1549,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode) if (b == RTLIL::State::S0) b = RTLIL::State::S1; else if (b == RTLIL::State::S1) b = RTLIL::State::S0; } - auto cell = module->addLut(NEW_ID, + auto cell = module->addLut(NEWER_ID, driver_lut->getPort(ID::A), y_bit, driver_mask); diff --git a/passes/techmap/aigmap.cc b/passes/techmap/aigmap.cc index 19e568a6147..352123c0112 100644 --- a/passes/techmap/aigmap.cc +++ b/passes/techmap/aigmap.cc @@ -108,8 +108,8 @@ struct AigmapPass : public Pass { SigBit A = sigs.at(node.left_parent); SigBit B = sigs.at(node.right_parent); if (nand_mode && node.inverter) { - bit = module->addWire(NEW_ID); - auto gate = module->addNandGate(NEW_ID, A, B, bit); + bit = module->addWire(NEWER_ID); + auto gate = module->addNandGate(NEWER_ID, A, B, bit); if (select_mode) new_sel.insert(gate->name); @@ -119,8 +119,8 @@ struct AigmapPass : public Pass { if (and_cache.count(key)) bit = and_cache.at(key); else { - bit = module->addWire(NEW_ID); - auto gate = module->addAndGate(NEW_ID, A, B, bit); + bit = module->addWire(NEWER_ID); + auto gate = module->addAndGate(NEWER_ID, A, B, bit); if (select_mode) new_sel.insert(gate->name); } @@ -128,8 +128,8 @@ struct AigmapPass : public Pass { } if (node.inverter) { - SigBit new_bit = module->addWire(NEW_ID); - auto gate = module->addNotGate(NEW_ID, bit, new_bit); + SigBit new_bit = module->addWire(NEWER_ID); + auto gate = module->addNotGate(NEWER_ID, bit, new_bit); bit = new_bit; if (select_mode) new_sel.insert(gate->name); diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc index 3dc54e8bb4f..af33d5a20d9 100644 --- a/passes/techmap/alumacc.cc +++ b/passes/techmap/alumacc.cc @@ -52,7 +52,7 @@ struct AlumaccWorker if (is_signed) { get_of(); get_sf(); - cached_lt = alu_cell->module->Xor(NEW_ID, cached_of, cached_sf); + cached_lt = alu_cell->module->Xor(NEWER_ID, cached_of, cached_sf); } else cached_lt = get_cf(); @@ -64,21 +64,21 @@ struct AlumaccWorker if (GetSize(cached_gt) == 0) { get_lt(); get_eq(); - SigSpec Or = alu_cell->module->Or(NEW_ID, cached_lt, cached_eq); - cached_gt = alu_cell->module->Not(NEW_ID, Or, false, alu_cell->get_src_attribute()); + SigSpec Or = alu_cell->module->Or(NEWER_ID, cached_lt, cached_eq); + cached_gt = alu_cell->module->Not(NEWER_ID, Or, false, alu_cell->get_src_attribute()); } return cached_gt; } RTLIL::SigSpec get_eq() { if (GetSize(cached_eq) == 0) - cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort(ID::X), false, alu_cell->get_src_attribute()); + cached_eq = alu_cell->module->ReduceAnd(NEWER_ID, alu_cell->getPort(ID::X), false, alu_cell->get_src_attribute()); return cached_eq; } RTLIL::SigSpec get_ne() { if (GetSize(cached_ne) == 0) - cached_ne = alu_cell->module->Not(NEW_ID, get_eq(), false, alu_cell->get_src_attribute()); + cached_ne = alu_cell->module->Not(NEWER_ID, get_eq(), false, alu_cell->get_src_attribute()); return cached_ne; } @@ -86,7 +86,7 @@ struct AlumaccWorker if (GetSize(cached_cf) == 0) { cached_cf = alu_cell->getPort(ID::CO); log_assert(GetSize(cached_cf) >= 1); - cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1], false, alu_cell->get_src_attribute()); + cached_cf = alu_cell->module->Not(NEWER_ID, cached_cf[GetSize(cached_cf)-1], false, alu_cell->get_src_attribute()); } return cached_cf; } @@ -95,7 +95,7 @@ struct AlumaccWorker if (GetSize(cached_of) == 0) { cached_of = {alu_cell->getPort(ID::CO), alu_cell->getPort(ID::CI)}; log_assert(GetSize(cached_of) >= 2); - cached_of = alu_cell->module->Xor(NEW_ID, cached_of[GetSize(cached_of)-1], cached_of[GetSize(cached_of)-2]); + cached_of = alu_cell->module->Xor(NEWER_ID, cached_of[GetSize(cached_of)-1], cached_of[GetSize(cached_of)-2]); } return cached_of; } @@ -362,7 +362,7 @@ struct AlumaccWorker for (auto &it : sig_macc) { auto n = it.second; - auto cell = module->addCell(NEW_ID, ID($macc)); + auto cell = module->addCell(NEWER_ID, ID($macc)); macc_counter++; @@ -428,7 +428,7 @@ struct AlumaccWorker n->a = A; n->b = B; n->c = State::S1; - n->y = module->addWire(NEW_ID, max(GetSize(A), GetSize(B))); + n->y = module->addWire(NEWER_ID, max(GetSize(A), GetSize(B))); n->is_signed = is_signed; n->invert_b = true; sig_alu[RTLIL::SigSig(A, B)].insert(n); @@ -482,7 +482,7 @@ struct AlumaccWorker { if (GetSize(n->b) == 0 && GetSize(n->c) == 0 && GetSize(n->cmp) == 0) { - n->alu_cell = module->addPos(NEW_ID, n->a, n->y, n->is_signed); + n->alu_cell = module->addPos(NEWER_ID, n->a, n->y, n->is_signed); log(" creating $pos cell for "); for (int i = 0; i < GetSize(n->cells); i++) @@ -492,7 +492,7 @@ struct AlumaccWorker goto delete_node; } - n->alu_cell = module->addCell(NEW_ID, ID($alu)); + n->alu_cell = module->addCell(NEWER_ID, ID($alu)); alu_counter++; log(" creating $alu cell for "); @@ -508,8 +508,8 @@ struct AlumaccWorker n->alu_cell->setPort(ID::CI, GetSize(n->c) ? n->c : State::S0); n->alu_cell->setPort(ID::BI, n->invert_b ? State::S1 : State::S0); n->alu_cell->setPort(ID::Y, n->y); - n->alu_cell->setPort(ID::X, module->addWire(NEW_ID, GetSize(n->y))); - n->alu_cell->setPort(ID::CO, module->addWire(NEW_ID, GetSize(n->y))); + n->alu_cell->setPort(ID::X, module->addWire(NEWER_ID, GetSize(n->y))); + n->alu_cell->setPort(ID::CO, module->addWire(NEWER_ID, GetSize(n->y))); n->alu_cell->fixup_parameters(n->is_signed, n->is_signed); for (auto &it : n->cmp) @@ -527,7 +527,7 @@ struct AlumaccWorker if (cmp_ne) sig.append(n->get_ne()); if (GetSize(sig) > 1) - sig = module->ReduceOr(NEW_ID, sig); + sig = module->ReduceOr(NEWER_ID, sig); sig.extend_u0(GetSize(cmp_y)); module->connect(cmp_y, sig); diff --git a/passes/techmap/bmuxmap.cc b/passes/techmap/bmuxmap.cc index 7aa67d3c071..338aefc983c 100644 --- a/passes/techmap/bmuxmap.cc +++ b/passes/techmap/bmuxmap.cc @@ -68,22 +68,22 @@ struct BmuxmapPass : public Pass { { int num_cases = 1 << s_width; SigSpec new_a = SigSpec(State::Sx, width); - SigSpec new_s = module->addWire(NEW_ID, num_cases); - SigSpec new_data = module->addWire(NEW_ID, width); + SigSpec new_s = module->addWire(NEWER_ID, num_cases); + SigSpec new_data = module->addWire(NEWER_ID, width); for (int val = 0; val < num_cases; val++) { - module->addEq(NEW_ID, sel, SigSpec(val, GetSize(sel)), new_s[val]); + module->addEq(NEWER_ID, sel, SigSpec(val, GetSize(sel)), new_s[val]); } - RTLIL::Cell *pmux = module->addPmux(NEW_ID, new_a, data, new_s, new_data); + RTLIL::Cell *pmux = module->addPmux(NEWER_ID, new_a, data, new_s, new_data); pmux->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); data = new_data; } else { for (int idx = 0; idx < GetSize(sel); idx++) { - SigSpec new_data = module->addWire(NEW_ID, GetSize(data)/2); + SigSpec new_data = module->addWire(NEWER_ID, GetSize(data)/2); for (int i = 0; i < GetSize(new_data); i += width) { - RTLIL::Cell *mux = module->addMux(NEW_ID, + RTLIL::Cell *mux = module->addMux(NEWER_ID, data.extract(i*2, width), data.extract(i*2+width, width), sel[idx], diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index 11ff71b29f7..165cd57789e 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -75,44 +75,44 @@ struct BoothPassWorker { // Booth unsigned decoder lsb SigBit Bur4d_lsb(std::string name, SigBit lsb_i, SigBit one_i, SigBit s_i) { - SigBit and_op = module->AndGate(NEW_ID_SUFFIX(name), lsb_i, one_i); - return module->XorGate(NEW_ID_SUFFIX(name), and_op, s_i); + SigBit and_op = module->AndGate(NEWER_ID_SUFFIX(name), lsb_i, one_i); + return module->XorGate(NEWER_ID_SUFFIX(name), and_op, s_i); } // Booth unsigned radix4 decoder SigBit Bur4d_n(std::string name, SigBit yn_i, SigBit ynm1_i, SigBit one_i, SigBit two_i, SigBit s_i) { // ppij = ((yn & one) | (ynm1 & two)) ^ s; - SigBit an1 = module->AndGate(NEW_ID_SUFFIX(name), yn_i, one_i); - SigBit an2 = module->AndGate(NEW_ID_SUFFIX(name), ynm1_i, two_i); - SigBit or1 = module->OrGate(NEW_ID_SUFFIX(name), an1, an2); - return module->XorGate(NEW_ID_SUFFIX(name), s_i, or1); + SigBit an1 = module->AndGate(NEWER_ID_SUFFIX(name), yn_i, one_i); + SigBit an2 = module->AndGate(NEWER_ID_SUFFIX(name), ynm1_i, two_i); + SigBit or1 = module->OrGate(NEWER_ID_SUFFIX(name), an1, an2); + return module->XorGate(NEWER_ID_SUFFIX(name), s_i, or1); } // Booth unsigned radix4 decoder SigBit Bur4d_msb(std::string name, SigBit msb_i, SigBit two_i, SigBit s_i) { // ppij = (msb & two) ^ s; - SigBit an1 = module->AndGate(NEW_ID_SUFFIX(name), msb_i, two_i); - return module->XorGate(NEW_ID_SUFFIX(name), s_i, an1); + SigBit an1 = module->AndGate(NEWER_ID_SUFFIX(name), msb_i, two_i); + return module->XorGate(NEWER_ID_SUFFIX(name), s_i, an1); } // half adder, used in CPA void BuildHa(std::string name, SigBit a_i, SigBit b_i, SigBit &s_o, SigBit &c_o) { - s_o = module->XorGate(NEW_ID_SUFFIX(name), a_i, b_i); - c_o = module->AndGate(NEW_ID_SUFFIX(name), a_i, b_i); + s_o = module->XorGate(NEWER_ID_SUFFIX(name), a_i, b_i); + c_o = module->AndGate(NEWER_ID_SUFFIX(name), a_i, b_i); } // Booth unsigned radix 4 encoder void BuildBur4e(std::string name, SigBit y0_i, SigBit y1_i, SigBit y2_i, SigBit &one_o, SigBit &two_o, SigBit &s_o, SigBit &sb_o) { - one_o = module->XorGate(NEW_ID_SUFFIX(name), y0_i, y1_i); + one_o = module->XorGate(NEWER_ID_SUFFIX(name), y0_i, y1_i); s_o = y2_i; - sb_o = module->NotGate(NEW_ID_SUFFIX(name), y2_i); - SigBit y1_xnor_y2 = module->XnorGate(NEW_ID_SUFFIX(name), y1_i, y2_i); - two_o = module->NorGate(NEW_ID_SUFFIX(name), y1_xnor_y2, one_o); + sb_o = module->NotGate(NEWER_ID_SUFFIX(name), y2_i); + SigBit y1_xnor_y2 = module->XnorGate(NEWER_ID_SUFFIX(name), y1_i, y2_i); + two_o = module->NorGate(NEWER_ID_SUFFIX(name), y1_xnor_y2, one_o); } void BuildBr4e(std::string name, SigBit y2_m1_i, @@ -120,9 +120,9 @@ struct BoothPassWorker { SigBit y2_p1_i, SigBit &negi_o, SigBit &twoi_n_o, SigBit &onei_n_o, SigBit &cori_o) { - auto y2_p1_n = module->NotGate(NEW_ID_SUFFIX(name), y2_p1_i); - auto y2_n = module->NotGate(NEW_ID_SUFFIX(name), y2_i); - auto y2_m1_n = module->NotGate(NEW_ID_SUFFIX(name), y2_m1_i); + auto y2_p1_n = module->NotGate(NEWER_ID_SUFFIX(name), y2_p1_i); + auto y2_n = module->NotGate(NEWER_ID_SUFFIX(name), y2_i); + auto y2_m1_n = module->NotGate(NEWER_ID_SUFFIX(name), y2_m1_i); negi_o = y2_p1_i; @@ -130,15 +130,15 @@ struct BoothPassWorker { // (y2_p1_n & y2_i & y2_m1_i) | // (y2_p1 & y2_n & y2_m1_n) // ) - twoi_n_o = module->NorGate(NEW_ID_SUFFIX(name), - module->AndGate(NEW_ID_SUFFIX(name), y2_p1_n, module->AndGate(NEW_ID_SUFFIX(name), y2_i, y2_m1_i)), - module->AndGate(NEW_ID_SUFFIX(name), y2_p1_i, module->AndGate(NEW_ID_SUFFIX(name), y2_n, y2_m1_n)) + twoi_n_o = module->NorGate(NEWER_ID_SUFFIX(name), + module->AndGate(NEWER_ID_SUFFIX(name), y2_p1_n, module->AndGate(NEWER_ID_SUFFIX(name), y2_i, y2_m1_i)), + module->AndGate(NEWER_ID_SUFFIX(name), y2_p1_i, module->AndGate(NEWER_ID_SUFFIX(name), y2_n, y2_m1_n)) ); // onei_n = ~(y2_m1_i ^ y2_i); - onei_n_o = module->XnorGate(NEW_ID_SUFFIX(name), y2_m1_i, y2_i); + onei_n_o = module->XnorGate(NEWER_ID_SUFFIX(name), y2_m1_i, y2_i); // cori = (y2_m1_n | y2_n) & y2_p1_i; - cori_o = module->AndGate(NEW_ID_SUFFIX(name), module->OrGate(NEW_ID_SUFFIX(name), y2_m1_n, y2_n), y2_p1_i); + cori_o = module->AndGate(NEWER_ID_SUFFIX(name), module->OrGate(NEWER_ID_SUFFIX(name), y2_m1_n, y2_n), y2_p1_i); } // @@ -150,10 +150,10 @@ struct BoothPassWorker { // nxj_in = xnor(xj,negi) // nxj_o = xnj_in, // ppij = ~( (nxj_m1_i | twoi_n_i) & (nxj_int | onei_n_i)); - nxj_o = module->XnorGate(NEW_ID_SUFFIX(name), xj_i, negi_i); - ppij_o = module->NandGate(NEW_ID_SUFFIX(name), - module->OrGate(NEW_ID_SUFFIX(name), nxj_m1_i, twoi_n_i), - module->OrGate(NEW_ID_SUFFIX(name), nxj_o, onei_n_i) + nxj_o = module->XnorGate(NEWER_ID_SUFFIX(name), xj_i, negi_i); + ppij_o = module->NandGate(NEWER_ID_SUFFIX(name), + module->OrGate(NEWER_ID_SUFFIX(name), nxj_m1_i, twoi_n_i), + module->OrGate(NEWER_ID_SUFFIX(name), nxj_o, onei_n_i) ); } @@ -177,14 +177,14 @@ struct BoothPassWorker { //correction propagation assign CORO = (~PP1 & ~PP0)? CORI : 1'b0; */ - nxj_o = module->XnorGate(NEW_ID_SUFFIX(name), x1_i, negi_i); - pp0_o = module->AndGate(NEW_ID_SUFFIX(name), x0_i, y0_i); - SigBit pp1_1_int = module->AndGate(NEW_ID_SUFFIX(name), x1_i, y0_i); - SigBit pp1_2_int = module->AndGate(NEW_ID_SUFFIX(name), x0_i, y1_i); - pp1_o = module->XorGate(NEW_ID_SUFFIX(name), pp1_1_int, pp1_2_int); - - SigBit pp1_nor_pp0 = module->NorGate(NEW_ID_SUFFIX(name), pp1_o, pp0_o); - cor_o = module->AndGate(NEW_ID_SUFFIX(name), pp1_nor_pp0, cori_i); + nxj_o = module->XnorGate(NEWER_ID_SUFFIX(name), x1_i, negi_i); + pp0_o = module->AndGate(NEWER_ID_SUFFIX(name), x0_i, y0_i); + SigBit pp1_1_int = module->AndGate(NEWER_ID_SUFFIX(name), x1_i, y0_i); + SigBit pp1_2_int = module->AndGate(NEWER_ID_SUFFIX(name), x0_i, y1_i); + pp1_o = module->XorGate(NEWER_ID_SUFFIX(name), pp1_1_int, pp1_2_int); + + SigBit pp1_nor_pp0 = module->NorGate(NEWER_ID_SUFFIX(name), pp1_o, pp0_o); + cor_o = module->AndGate(NEWER_ID_SUFFIX(name), pp1_nor_pp0, cori_i); } void BuildBitwiseFa(Module *mod, std::string name, const SigSpec &sig_a, const SigSpec &sig_b, @@ -289,7 +289,7 @@ struct BoothPassWorker { int required_op_size = x_sz_revised + y_sz_revised; if (required_op_size != z_sz) { - SigSpec expanded_Y = module->addWire(NEW_ID, required_op_size); + SigSpec expanded_Y = module->addWire(NEWER_ID, required_op_size); SigSpec Y_driver = expanded_Y; Y_driver.extend_u0(Y.size(), is_signed); module->connect(Y, Y_driver); @@ -326,9 +326,9 @@ struct BoothPassWorker { std::vector new_summands; int i; for (i = 0; i < (int) summands.size() - 2; i += 3) { - SigSpec x = module->addWire(NEW_ID, width); - SigSpec y = module->addWire(NEW_ID, width); - BuildBitwiseFa(module, NEW_ID.str(), summands[i], summands[i + 1], + SigSpec x = module->addWire(NEWER_ID, width); + SigSpec y = module->addWire(NEWER_ID, width); + BuildBitwiseFa(module, NEWER_ID.str(), summands[i], summands[i + 1], summands[i + 2], x, y); new_summands.push_back(y); new_summands.push_back({x.extract(0, width - 1), State::S0}); @@ -424,7 +424,7 @@ struct BoothPassWorker { if (mapped_cpa) BuildCPA(module, wtree_sum.first, {State::S0, wtree_sum.second.extract_end(1)}, Z); else - module->addAdd(NEW_ID, wtree_sum.first, {wtree_sum.second.extract_end(1), State::S0}, Z); + module->addAdd(NEWER_ID, wtree_sum.first, {wtree_sum.second.extract_end(1), State::S0}, Z); } /* @@ -460,11 +460,11 @@ struct BoothPassWorker { // append the sign bits if (is_signed) { - SigBit e = module->XorGate(NEW_ID, s_int[0], module->AndGate(NEW_ID, X.msb(), module->OrGate(NEW_ID, two_int[0], one_int[0]))); - ppij_vec.append({module->NotGate(NEW_ID, e), e, e}); + SigBit e = module->XorGate(NEWER_ID, s_int[0], module->AndGate(NEWER_ID, X.msb(), module->OrGate(NEWER_ID, two_int[0], one_int[0]))); + ppij_vec.append({module->NotGate(NEWER_ID, e), e, e}); } else { // append the sign bits - ppij_vec.append({module->NotGate(NEW_ID, s_int[0]), s_int[0], s_int[0]}); + ppij_vec.append({module->NotGate(NEWER_ID, s_int[0]), s_int[0], s_int[0]}); } } @@ -494,7 +494,7 @@ struct BoothPassWorker { one_int, two_int, s_int)); } - ppij_vec.append(!is_signed ? sb_int[0] : module->XorGate(NEW_ID, sb_int, module->AndGate(NEW_ID, X.msb(), module->OrGate(NEW_ID, two_int, one_int)))); + ppij_vec.append(!is_signed ? sb_int[0] : module->XorGate(NEWER_ID, sb_int, module->AndGate(NEWER_ID, X.msb(), module->OrGate(NEWER_ID, two_int, one_int)))); ppij_vec.append(State::S1); } @@ -721,7 +721,7 @@ struct BoothPassWorker { // Base Case: Bit 0 is sum 0 if (n == 0) { - module->addBufGate(NEW_ID_SUFFIX(stringf("base_buf_%d_%d", cpa_id, n)), s_vec[0], result[0]); + module->addBufGate(NEWER_ID_SUFFIX(stringf("base_buf_%d_%d", cpa_id, n)), s_vec[0], result[0]); #ifdef DEBUG_CPA printf("CPA bit [%d] Cell %s IP 0 %s \n", n, buf->name.c_str(), s_vec[0]->name.c_str()); @@ -747,8 +747,8 @@ struct BoothPassWorker { // End Case else if (n == s_vec.size() - 1) { // Make the carry results.. Two extra bits after fa. - SigBit carry_out = module->addWire(NEW_ID, 1); - module->addFa(NEW_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)), + SigBit carry_out = module->addWire(NEWER_ID, 1); + module->addFa(NEWER_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)), /* A */ s_vec[n], /* B */ c_vec[n - 1], /* C */ carry, @@ -775,8 +775,8 @@ struct BoothPassWorker { } // Step case else { - SigBit carry_out = module->addWire(NEW_ID_SUFFIX(stringf("cpa_%d_carry_%d", cpa_id, n)), 1); - module->addFa(NEW_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)), + SigBit carry_out = module->addWire(NEWER_ID_SUFFIX(stringf("cpa_%d_carry_%d", cpa_id, n)), 1); + module->addFa(NEWER_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)), /* A */ s_vec[n], /* B */ c_vec[n - 1], /* C */ carry, @@ -814,10 +814,10 @@ struct BoothPassWorker { if (first_csa_ips.size() > 0) { // build the first csa - auto s_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1); - auto c_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1); + auto s_wire = module->addWire(NEWER_ID_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1); + auto c_wire = module->addWire(NEWER_ID_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1); - auto csa = module->addFa(NEW_ID_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)), + auto csa = module->addFa(NEWER_ID_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)), /* A */ first_csa_ips[0], /* B */ first_csa_ips.size() > 1 ? first_csa_ips[1] : State::S0, /* C */ first_csa_ips.size() > 2 ? first_csa_ips[2] : State::S0, @@ -846,10 +846,10 @@ struct BoothPassWorker { } if (csa_ips.size() > 0) { - auto c_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1); - auto s_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1); + auto c_wire = module->addWire(NEWER_ID_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1); + auto s_wire = module->addWire(NEWER_ID_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1); - auto csa = module->addFa(NEW_ID_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)), + auto csa = module->addFa(NEWER_ID_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)), /* A */ s_result, /* B */ csa_ips[0], /* C */ csa_ips.size() > 1 ? csa_ips[1] : State::S0, @@ -879,10 +879,10 @@ struct BoothPassWorker { for (int y_ix = 0; y_ix < (!is_signed ? y_sz : y_sz - 1);) { std::string enc_name = stringf("bur_enc_%d", encoder_ix); - two_int.append(module->addWire(NEW_ID_SUFFIX(stringf("two_int_%d", encoder_ix)), 1)); - one_int.append(module->addWire(NEW_ID_SUFFIX(stringf("one_int_%d", encoder_ix)), 1)); - s_int.append(module->addWire(NEW_ID_SUFFIX(stringf("s_int_%d", encoder_ix)), 1)); - sb_int.append(module->addWire(NEW_ID_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1)); + two_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("two_int_%d", encoder_ix)), 1)); + one_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("one_int_%d", encoder_ix)), 1)); + s_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("s_int_%d", encoder_ix)), 1)); + sb_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1)); if (y_ix == 0) { BuildBur4e(enc_name, State::S0, Y[y_ix], @@ -939,10 +939,10 @@ struct BoothPassWorker { std::string enc_name = stringf("br_enc_pad_%d", encoder_ix); - two_int.append(module->addWire(NEW_ID_SUFFIX(stringf("two_int_%d", encoder_ix)), 1)); - one_int.append(module->addWire(NEW_ID_SUFFIX(stringf("one_int_%d", encoder_ix)), 1)); - s_int.append(module->addWire(NEW_ID_SUFFIX(stringf("s_int_%d", encoder_ix)), 1)); - sb_int.append(module->addWire(NEW_ID_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1)); + two_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("two_int_%d", encoder_ix)), 1)); + one_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("one_int_%d", encoder_ix)), 1)); + s_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("s_int_%d", encoder_ix)), 1)); + sb_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1)); SigBit one_o_int, two_o_int, s_o_int, sb_o_int; BuildBur4e(enc_name, Y[y_ix], State::S0, @@ -986,10 +986,10 @@ struct BoothPassWorker { for (unsigned encoder_ix = 1; encoder_ix <= enc_count; encoder_ix++) { std::string enc_name = stringf("enc_%d", encoder_ix); - negi_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("negi_n_int_%d", encoder_ix)), 1); - twoi_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("twoi_n_int_%d", encoder_ix)), 1); - onei_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("onei_n_int_%d", encoder_ix)), 1); - cori_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("cori_n_int_%d", encoder_ix)), 1); + negi_n_int[encoder_ix - 1] = module->addWire(NEWER_ID_SUFFIX(stringf("negi_n_int_%d", encoder_ix)), 1); + twoi_n_int[encoder_ix - 1] = module->addWire(NEWER_ID_SUFFIX(stringf("twoi_n_int_%d", encoder_ix)), 1); + onei_n_int[encoder_ix - 1] = module->addWire(NEWER_ID_SUFFIX(stringf("onei_n_int_%d", encoder_ix)), 1); + cori_n_int[encoder_ix - 1] = module->addWire(NEWER_ID_SUFFIX(stringf("cori_n_int_%d", encoder_ix)), 1); if (encoder_ix == 1) { BuildBr4e(enc_name, State::S0, Y[0], Y[1], @@ -1024,10 +1024,10 @@ struct BoothPassWorker { for (int encoder_ix = 1; encoder_ix <= (int)enc_count; encoder_ix++) { for (int decoder_ix = 1; decoder_ix <= dec_count; decoder_ix++) { PPij[((encoder_ix - 1) * dec_count) + decoder_ix - 1] = - module->addWire(NEW_ID_SUFFIX(stringf("ppij_%d_%d", encoder_ix, decoder_ix)), 1); + module->addWire(NEWER_ID_SUFFIX(stringf("ppij_%d_%d", encoder_ix, decoder_ix)), 1); nxj[((encoder_ix - 1) * dec_count) + decoder_ix - 1] = - module->addWire(NEW_ID_SUFFIX(stringf("nxj_%s%d_%d", decoder_ix == 1 ? "pre_dec_" : "", + module->addWire(NEWER_ID_SUFFIX(stringf("nxj_%s%d_%d", decoder_ix == 1 ? "pre_dec_" : "", encoder_ix, decoder_ix)), 1); } } @@ -1042,7 +1042,7 @@ struct BoothPassWorker { if (encoder_ix == 1) { // quadrant 1 optimization } else { - module->addNotGate(NEW_ID_SUFFIX(stringf("pre_dec_%d", encoder_ix)), + module->addNotGate(NEWER_ID_SUFFIX(stringf("pre_dec_%d", encoder_ix)), negi_n_int[encoder_ix - 1], nxj[(encoder_ix - 1) * dec_count] ); @@ -1094,16 +1094,16 @@ struct BoothPassWorker { std::vector fa_carry; for (fa_row_ix = 0; fa_row_ix < fa_row_count; fa_row_ix++) { - fa_sum.push_back(module->addWire(NEW_ID_SUFFIX(stringf("fa_sum_%d", fa_row_ix)), fa_count)); - fa_carry.push_back(module->addWire(NEW_ID_SUFFIX(stringf("fa_carry_%d", fa_row_ix)), fa_count)); + fa_sum.push_back(module->addWire(NEWER_ID_SUFFIX(stringf("fa_sum_%d", fa_row_ix)), fa_count)); + fa_carry.push_back(module->addWire(NEWER_ID_SUFFIX(stringf("fa_carry_%d", fa_row_ix)), fa_count)); } // full adder creation // base case: 1st row: Inputs from decoders // 1st row exception: two localized inverters due to sign extension structure - SigBit d08_inv = module->NotGate(NEW_ID_SUFFIX("bfa_0_exc_inv1"), PPij[(0 * dec_count) + dec_count - 1]); - SigBit d18_inv = module->NotGate(NEW_ID_SUFFIX("bfa_0_exc_inv2"), PPij[(1 * dec_count) + dec_count - 1]); - BuildBitwiseFa(module, NEW_ID_SUFFIX("fa_row_0").str(), + SigBit d08_inv = module->NotGate(NEWER_ID_SUFFIX("bfa_0_exc_inv1"), PPij[(0 * dec_count) + dec_count - 1]); + SigBit d18_inv = module->NotGate(NEWER_ID_SUFFIX("bfa_0_exc_inv2"), PPij[(1 * dec_count) + dec_count - 1]); + BuildBitwiseFa(module, NEWER_ID_SUFFIX("fa_row_0").str(), /* A */ {State::S0, d08_inv, PPij[(0 * dec_count) + x_sz], PPij.extract((0 * dec_count) + 2, x_sz - 1)}, /* B */ {State::S1, d18_inv, PPij.extract((1 * dec_count), x_sz)}, /* C */ fa_carry[0].extract(1, x_sz + 2), @@ -1116,10 +1116,10 @@ struct BoothPassWorker { // special because these are driven by a decoder and prior fa. for (fa_row_ix = 1; fa_row_ix < fa_row_count; fa_row_ix++) { // end two bits: sign extension - SigBit d_inv = module->NotGate(NEW_ID_SUFFIX(stringf("bfa_se_inv_%d_L", fa_row_ix)), + SigBit d_inv = module->NotGate(NEWER_ID_SUFFIX(stringf("bfa_se_inv_%d_L", fa_row_ix)), PPij[((fa_row_ix + 1) * dec_count) + dec_count - 1]); - BuildBitwiseFa(module, NEW_ID_SUFFIX(stringf("fa_row_%d", fa_row_ix)).str(), + BuildBitwiseFa(module, NEWER_ID_SUFFIX(stringf("fa_row_%d", fa_row_ix)).str(), /* A */ {State::S0, fa_carry[fa_row_ix - 1][fa_count - 1], fa_sum[fa_row_ix - 1].extract(2, x_sz + 2)}, /* B */ {State::S1, d_inv, PPij.extract((fa_row_ix + 1) * dec_count, x_sz), State::S0, State::S0}, @@ -1132,7 +1132,7 @@ struct BoothPassWorker { // instantiate the cpa SigSpec cpa_carry; if (z_sz > fa_row_count * 2) - cpa_carry = module->addWire(NEW_ID_SUFFIX("cpa_carry"), z_sz - fa_row_count * 2); + cpa_carry = module->addWire(NEWER_ID_SUFFIX("cpa_carry"), z_sz - fa_row_count * 2); // The end case where we pass the last two summands // from prior row directly to product output diff --git a/passes/techmap/bufnorm.cc b/passes/techmap/bufnorm.cc index a4552c71bd4..7ea978bcef9 100644 --- a/passes/techmap/bufnorm.cc +++ b/passes/techmap/bufnorm.cc @@ -384,7 +384,7 @@ struct BufnormPass : public Pass { it->second.sort(compare_wires_f); w = *(it->second.begin()); } else { - w = module->addWire(NEW_ID, GetSize(conn.second)); + w = module->addWire(NEWER_ID, GetSize(conn.second)); for (int i = 0; i < GetSize(w); i++) sigmap.add(SigBit(w, i), keysig[i]); } @@ -434,7 +434,7 @@ struct BufnormPass : public Pass { return; } - Cell *cell = module->addCell(NEW_ID, type); + Cell *cell = module->addCell(NEWER_ID, type); added_buffers.insert(cell); cell->setPort(ID::A, src); diff --git a/passes/techmap/bwmuxmap.cc b/passes/techmap/bwmuxmap.cc index 7fe1cded777..07dcaa72a3a 100644 --- a/passes/techmap/bwmuxmap.cc +++ b/passes/techmap/bwmuxmap.cc @@ -57,10 +57,10 @@ struct BwmuxmapPass : public Pass { auto &sig_b = cell->getPort(ID::B); auto &sig_s = cell->getPort(ID::S); - auto not_s = module->Not(NEW_ID, sig_s); - auto masked_b = module->And(NEW_ID, sig_s, sig_b); - auto masked_a = module->And(NEW_ID, not_s, sig_a); - module->addOr(NEW_ID, masked_a, masked_b, sig_y); + auto not_s = module->Not(NEWER_ID, sig_s); + auto masked_b = module->And(NEWER_ID, sig_s, sig_b); + auto masked_a = module->And(NEWER_ID, not_s, sig_a); + module->addOr(NEWER_ID, masked_a, masked_b, sig_y); module->remove(cell); } diff --git a/passes/techmap/clkbufmap.cc b/passes/techmap/clkbufmap.cc index 7003c66569a..f36ad3e7c1b 100644 --- a/passes/techmap/clkbufmap.cc +++ b/passes/techmap/clkbufmap.cc @@ -258,21 +258,21 @@ struct ClkbufmapPass : public Pass { bool is_input = wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute(ID::top); if (!buf_celltype.empty() && (!is_input || buffer_inputs)) { log("Inserting %s on %s.%s[%d].\n", buf_celltype, log_id(module), log_id(wire), i); - cell = module->addCell(NEW_ID, RTLIL::escape_id(buf_celltype)); - iwire = module->addWire(NEW_ID); + cell = module->addCell(NEWER_ID, RTLIL::escape_id(buf_celltype)); + iwire = module->addWire(NEWER_ID); cell->setPort(RTLIL::escape_id(buf_portname), mapped_wire_bit); cell->setPort(RTLIL::escape_id(buf_portname2), iwire); } if (is_input) { log("Inserting %s on %s.%s[%d].\n", inpad_celltype, log_id(module), log_id(wire), i); - RTLIL::Cell *cell2 = module->addCell(NEW_ID, RTLIL::escape_id(inpad_celltype)); + RTLIL::Cell *cell2 = module->addCell(NEWER_ID, RTLIL::escape_id(inpad_celltype)); if (iwire) { cell2->setPort(RTLIL::escape_id(inpad_portname), iwire); } else { cell2->setPort(RTLIL::escape_id(inpad_portname), mapped_wire_bit); cell = cell2; } - iwire = module->addWire(NEW_ID); + iwire = module->addWire(NEWER_ID); cell2->setPort(RTLIL::escape_id(inpad_portname2), iwire); } if (iwire) @@ -291,7 +291,7 @@ struct ClkbufmapPass : public Pass { if (!input_bits.empty()) { // This is an input port and some buffers were inserted -- we need // to create a new input wire and transfer attributes. - Wire *new_wire = module->addWire(NEW_ID, wire); + Wire *new_wire = module->addWire(NEWER_ID, wire); for (int i = 0; i < wire->width; i++) { SigBit wire_bit(wire, i); diff --git a/passes/techmap/clockgate.cc b/passes/techmap/clockgate.cc index b834b8f35ac..31b27131c2e 100644 --- a/passes/techmap/clockgate.cc +++ b/passes/techmap/clockgate.cc @@ -371,17 +371,17 @@ struct ClockgatePass : public Pass { if (!matching_icg_desc) continue; - Cell* icg = module->addCell(NEW_ID, matching_icg_desc->name); + Cell* icg = module->addCell(NEWER_ID, matching_icg_desc->name); icg->setPort(matching_icg_desc->ce_pin, clk.ce_bit); icg->setPort(matching_icg_desc->clk_in_pin, clk.clk_bit); - gclk.new_net = module->addWire(NEW_ID); + gclk.new_net = module->addWire(NEWER_ID); icg->setPort(matching_icg_desc->clk_out_pin, gclk.new_net); // Tie low DFT ports like scan chain enable for (auto port : matching_icg_desc->tie_lo_pins) icg->setPort(port, Const(0, 1)); // Fix CE polarity if needed if (!clk.pol_ce) { - SigBit ce_fixed_pol = module->NotGate(NEW_ID, clk.ce_bit); + SigBit ce_fixed_pol = module->NotGate(NEWER_ID, clk.ce_bit); icg->setPort(matching_icg_desc->ce_pin, ce_fixed_pol); } } diff --git a/passes/techmap/constmap.cc b/passes/techmap/constmap.cc index f0757403d92..98c94c8dd4a 100644 --- a/passes/techmap/constmap.cc +++ b/passes/techmap/constmap.cc @@ -32,8 +32,8 @@ static RTLIL::SigChunk value; void constmap_worker(RTLIL::SigSpec &sig) { if (sig.is_fully_const()){ - value = module->addWire(NEW_ID, sig.size()); - RTLIL::Cell *cell = module->addCell(NEW_ID, celltype); + value = module->addWire(NEWER_ID, sig.size()); + RTLIL::Cell *cell = module->addCell(NEWER_ID, celltype); cell->setParam(cell_paramname, sig.as_const()); cell->setPort(cell_portname, value); sig = value; diff --git a/passes/techmap/demuxmap.cc b/passes/techmap/demuxmap.cc index 292b18badf0..0fd58e2746c 100644 --- a/passes/techmap/demuxmap.cc +++ b/passes/techmap/demuxmap.cc @@ -57,13 +57,13 @@ struct DemuxmapPass : public Pass { for (int i = 0; i < 1 << GetSize(sel); i++) { if (width == 1 && data == State::S1) { - RTLIL::Cell *eq_cell = module->addEq(NEW_ID, sel, Const(i, GetSize(sel)), out[i]); + RTLIL::Cell *eq_cell = module->addEq(NEWER_ID, sel, Const(i, GetSize(sel)), out[i]); eq_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); } else { - Wire *eq = module->addWire(NEW_ID); - RTLIL::Cell *eq_cell = module->addEq(NEW_ID, sel, Const(i, GetSize(sel)), eq); + Wire *eq = module->addWire(NEWER_ID); + RTLIL::Cell *eq_cell = module->addEq(NEWER_ID, sel, Const(i, GetSize(sel)), eq); eq_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); - RTLIL::Cell *mux = module->addMux(NEW_ID, + RTLIL::Cell *mux = module->addMux(NEWER_ID, Const(State::S0, width), data, eq, diff --git a/passes/techmap/dfflegalize.cc b/passes/techmap/dfflegalize.cc index 5a622c611bd..55504af78c8 100644 --- a/passes/techmap/dfflegalize.cc +++ b/passes/techmap/dfflegalize.cc @@ -280,7 +280,7 @@ struct DffLegalizePass : public Pass { void emulate_split_init_arst(FfData &ff) { ff.remove(); - FfData ff_dff(ff.module, &initvals, NEW_ID); + FfData ff_dff(ff.module, &initvals, NEWER_ID); ff_dff.width = ff.width; ff_dff.has_aload = ff.has_aload; ff_dff.sig_aload = ff.sig_aload; @@ -293,11 +293,11 @@ struct DffLegalizePass : public Pass { ff_dff.has_ce = ff.has_ce; ff_dff.sig_ce = ff.sig_ce; ff_dff.pol_ce = ff.pol_ce; - ff_dff.sig_q = ff.module->addWire(NEW_ID, ff.width); + ff_dff.sig_q = ff.module->addWire(NEWER_ID, ff.width); ff_dff.val_init = ff.val_init; ff_dff.is_fine = ff.is_fine; - FfData ff_adff(ff.module, &initvals, NEW_ID); + FfData ff_adff(ff.module, &initvals, NEWER_ID); ff_adff.width = ff.width; ff_adff.has_aload = ff.has_aload; ff_adff.sig_aload = ff.sig_aload; @@ -310,7 +310,7 @@ struct DffLegalizePass : public Pass { ff_adff.has_ce = ff.has_ce; ff_adff.sig_ce = ff.sig_ce; ff_adff.pol_ce = ff.pol_ce; - ff_adff.sig_q = ff.module->addWire(NEW_ID, ff.width); + ff_adff.sig_q = ff.module->addWire(NEWER_ID, ff.width); ff_adff.val_init = Const(State::Sx, ff.width); ff_adff.has_arst = true; ff_adff.sig_arst = ff.sig_arst; @@ -318,9 +318,9 @@ struct DffLegalizePass : public Pass { ff_adff.val_arst = ff.val_arst; ff_adff.is_fine = ff.is_fine; - FfData ff_sel(ff.module, &initvals, NEW_ID); + FfData ff_sel(ff.module, &initvals, NEWER_ID); ff_sel.width = 1; - ff_sel.sig_q = ff.module->addWire(NEW_ID); + ff_sel.sig_q = ff.module->addWire(NEWER_ID); ff_sel.has_arst = true; ff_sel.sig_arst = ff.sig_arst; ff_sel.pol_arst = ff.pol_arst; @@ -329,9 +329,9 @@ struct DffLegalizePass : public Pass { ff_sel.is_fine = ff.is_fine; if (ff.is_fine) - ff.module->addMuxGate(NEW_ID, ff_dff.sig_q, ff_adff.sig_q, ff_sel.sig_q, ff.sig_q); + ff.module->addMuxGate(NEWER_ID, ff_dff.sig_q, ff_adff.sig_q, ff_sel.sig_q, ff.sig_q); else - ff.module->addMux(NEW_ID, ff_dff.sig_q, ff_adff.sig_q, ff_sel.sig_q, ff.sig_q); + ff.module->addMux(NEWER_ID, ff_dff.sig_q, ff_adff.sig_q, ff_sel.sig_q, ff.sig_q); legalize_ff(ff_dff); legalize_ff(ff_adff); @@ -386,7 +386,7 @@ struct DffLegalizePass : public Pass { log_assert(ff.width == 1); ff.remove(); - FfData ff_clr(ff.module, &initvals, NEW_ID); + FfData ff_clr(ff.module, &initvals, NEWER_ID); ff_clr.width = ff.width; ff_clr.has_aload = ff.has_aload; ff_clr.sig_aload = ff.sig_aload; @@ -403,11 +403,11 @@ struct DffLegalizePass : public Pass { ff_clr.sig_arst = ff.sig_clr; ff_clr.pol_arst = ff.pol_clr; ff_clr.val_arst = Const(State::S0, ff.width); - ff_clr.sig_q = ff.module->addWire(NEW_ID, ff.width); + ff_clr.sig_q = ff.module->addWire(NEWER_ID, ff.width); ff_clr.val_init = init_clr ? ff.val_init : Const(State::Sx, ff.width); ff_clr.is_fine = ff.is_fine; - FfData ff_set(ff.module, &initvals, NEW_ID); + FfData ff_set(ff.module, &initvals, NEWER_ID); ff_set.width = ff.width; ff_set.has_aload = ff.has_aload; ff_set.sig_aload = ff.sig_aload; @@ -424,25 +424,25 @@ struct DffLegalizePass : public Pass { ff_set.sig_arst = ff.sig_set; ff_set.pol_arst = ff.pol_set; ff_set.val_arst = Const(State::S1, ff.width); - ff_set.sig_q = ff.module->addWire(NEW_ID, ff.width); + ff_set.sig_q = ff.module->addWire(NEWER_ID, ff.width); ff_set.val_init = init_set ? ff.val_init : Const(State::Sx, ff.width); ff_set.is_fine = ff.is_fine; - FfData ff_sel(ff.module, &initvals, NEW_ID); + FfData ff_sel(ff.module, &initvals, NEWER_ID); ff_sel.width = ff.width; ff_sel.has_sr = true; ff_sel.pol_clr = ff.pol_clr; ff_sel.pol_set = ff.pol_set; ff_sel.sig_clr = ff.sig_clr; ff_sel.sig_set = ff.sig_set; - ff_sel.sig_q = ff.module->addWire(NEW_ID, ff.width); + ff_sel.sig_q = ff.module->addWire(NEWER_ID, ff.width); ff_sel.val_init = Const(initsel, ff.width); ff_sel.is_fine = ff.is_fine; if (!ff.is_fine) - ff.module->addMux(NEW_ID, ff_clr.sig_q, ff_set.sig_q, ff_sel.sig_q, ff.sig_q); + ff.module->addMux(NEWER_ID, ff_clr.sig_q, ff_set.sig_q, ff_sel.sig_q, ff.sig_q); else - ff.module->addMuxGate(NEW_ID, ff_clr.sig_q, ff_set.sig_q, ff_sel.sig_q, ff.sig_q); + ff.module->addMuxGate(NEWER_ID, ff_clr.sig_q, ff_set.sig_q, ff_sel.sig_q, ff.sig_q); legalize_ff(ff_clr); legalize_ff(ff_set); @@ -841,11 +841,11 @@ struct DffLegalizePass : public Pass { ff.sig_ad = State::S0; ff.val_arst = State::S1; ff.remove_init(); - Wire *new_q = ff.module->addWire(NEW_ID); + Wire *new_q = ff.module->addWire(NEWER_ID); if (ff.is_fine) - ff.module->addNotGate(NEW_ID, new_q, ff.sig_q); + ff.module->addNotGate(NEWER_ID, new_q, ff.sig_q); else - ff.module->addNot(NEW_ID, new_q, ff.sig_q); + ff.module->addNot(NEWER_ID, new_q, ff.sig_q); ff.sig_q = new_q; if (ff.val_init == State::S0) ff.val_init = State::S1; @@ -938,9 +938,9 @@ struct DffLegalizePass : public Pass { } else if (sig == State::S1) { sig = State::S0; } else if (ff.is_fine) { - sig = ff.module->NotGate(NEW_ID, sig); + sig = ff.module->NotGate(NEWER_ID, sig); } else { - sig = ff.module->Not(NEW_ID, sig); + sig = ff.module->Not(NEWER_ID, sig); } pol = !pol; } diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 062a63ec3a8..4410c0e0549 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -529,25 +529,25 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module) } else if (port.second == 'q') { RTLIL::SigSpec old_sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))]; - sig = module->addWire(NEW_ID, GetSize(old_sig)); + sig = module->addWire(NEWER_ID, GetSize(old_sig)); if (has_q && has_qn) { for (auto &it : notmap[sigmap(old_sig)]) { module->connect(it->getPort(ID::Y), sig); - it->setPort(ID::Y, module->addWire(NEW_ID, GetSize(old_sig))); + it->setPort(ID::Y, module->addWire(NEWER_ID, GetSize(old_sig))); } } else { - module->addNotGate(NEW_ID, sig, old_sig); + module->addNotGate(NEWER_ID, sig, old_sig); } } else if ('a' <= port.second && port.second <= 'z') { sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))]; - sig = module->NotGate(NEW_ID, sig); + sig = module->NotGate(NEWER_ID, sig); } else if (port.second == '0' || port.second == '1') { sig = RTLIL::SigSpec(port.second == '0' ? 0 : 1, 1); } else if (port.second == 0) { - sig = module->addWire(NEW_ID); + sig = module->addWire(NEWER_ID); } else log_abort(); new_cell->setPort("\\" + port.first, sig); diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc index c45792f669b..fcdf57da9f4 100644 --- a/passes/techmap/extract_counter.cc +++ b/passes/techmap/extract_counter.cc @@ -639,8 +639,8 @@ void counter_worker( //If the reset is active low, infer an inverter ($__COUNT_ cells always have active high reset) if(extract.rst_inverted) { - auto realreset = cell->module->addWire(NEW_ID); - cell->module->addNot(NEW_ID, extract.rst, RTLIL::SigSpec(realreset)); + auto realreset = cell->module->addWire(NEWER_ID); + cell->module->addNot(NEWER_ID, extract.rst, RTLIL::SigSpec(realreset)); cell->setPort(ID(RST), realreset); } else @@ -665,8 +665,8 @@ void counter_worker( cell->setParam(ID(HAS_CE), RTLIL::Const(1)); if(extract.ce_inverted) { - auto realce = cell->module->addWire(NEW_ID); - cell->module->addNot(NEW_ID, extract.ce, RTLIL::SigSpec(realce)); + auto realce = cell->module->addWire(NEWER_ID); + cell->module->addNot(NEWER_ID, extract.ce, RTLIL::SigSpec(realce)); cell->setPort(ID(CE), realce); } else diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc index 1984f82f51e..ce45cc14cba 100644 --- a/passes/techmap/extract_fa.cc +++ b/passes/techmap/extract_fa.cc @@ -282,7 +282,7 @@ struct ExtractFaWorker { Cell *cell = driver.at(bit); if (sigmap(cell->getPort(ID::Y)) == SigSpec(bit)) { - cell->setPort(ID::Y, module->addWire(NEW_ID)); + cell->setPort(ID::Y, module->addWire(NEWER_ID)); module->connect(bit, new_driver); } } @@ -394,17 +394,17 @@ struct ExtractFaWorker } else { - Cell *cell = module->addCell(NEW_ID, ID($fa)); + Cell *cell = module->addCell(NEWER_ID, ID($fa)); cell->setParam(ID::WIDTH, 1); log(" Created $fa cell %s.\n", log_id(cell)); - cell->setPort(ID::A, f3i.inv_a ? module->NotGate(NEW_ID, A) : A); - cell->setPort(ID::B, f3i.inv_b ? module->NotGate(NEW_ID, B) : B); - cell->setPort(ID::C, f3i.inv_c ? module->NotGate(NEW_ID, C) : C); + cell->setPort(ID::A, f3i.inv_a ? module->NotGate(NEWER_ID, A) : A); + cell->setPort(ID::B, f3i.inv_b ? module->NotGate(NEWER_ID, B) : B); + cell->setPort(ID::C, f3i.inv_c ? module->NotGate(NEWER_ID, C) : C); - X = module->addWire(NEW_ID); - Y = module->addWire(NEW_ID); + X = module->addWire(NEWER_ID); + Y = module->addWire(NEWER_ID); cell->setPort(ID::X, X); cell->setPort(ID::Y, Y); @@ -414,18 +414,18 @@ struct ExtractFaWorker bool invert_y = f3i.inv_a ^ f3i.inv_b ^ f3i.inv_c; if (func3.at(key).count(xor3_func)) { - SigBit YY = invert_xy ^ invert_y ? module->NotGate(NEW_ID, Y) : Y; + SigBit YY = invert_xy ^ invert_y ? module->NotGate(NEWER_ID, Y) : Y; for (auto bit : func3.at(key).at(xor3_func)) assign_new_driver(bit, YY); } if (func3.at(key).count(xnor3_func)) { - SigBit YY = invert_xy ^ invert_y ? Y : module->NotGate(NEW_ID, Y); + SigBit YY = invert_xy ^ invert_y ? Y : module->NotGate(NEWER_ID, Y); for (auto bit : func3.at(key).at(xnor3_func)) assign_new_driver(bit, YY); } - SigBit XX = invert_xy != f3i.inv_y ? module->NotGate(NEW_ID, X) : X; + SigBit XX = invert_xy != f3i.inv_y ? module->NotGate(NEWER_ID, X) : X; for (auto bit : func3.at(key).at(func)) assign_new_driver(bit, XX); @@ -501,35 +501,35 @@ struct ExtractFaWorker } else { - Cell *cell = module->addCell(NEW_ID, ID($fa)); + Cell *cell = module->addCell(NEWER_ID, ID($fa)); cell->setParam(ID::WIDTH, 1); log(" Created $fa cell %s.\n", log_id(cell)); - cell->setPort(ID::A, f2i.inv_a ? module->NotGate(NEW_ID, A) : A); - cell->setPort(ID::B, f2i.inv_b ? module->NotGate(NEW_ID, B) : B); + cell->setPort(ID::A, f2i.inv_a ? module->NotGate(NEWER_ID, A) : A); + cell->setPort(ID::B, f2i.inv_b ? module->NotGate(NEWER_ID, B) : B); cell->setPort(ID::C, State::S0); - X = module->addWire(NEW_ID); - Y = module->addWire(NEW_ID); + X = module->addWire(NEWER_ID); + Y = module->addWire(NEWER_ID); cell->setPort(ID::X, X); cell->setPort(ID::Y, Y); } if (func2.at(key).count(xor2_func)) { - SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? module->NotGate(NEW_ID, Y) : Y; + SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? module->NotGate(NEWER_ID, Y) : Y; for (auto bit : func2.at(key).at(xor2_func)) assign_new_driver(bit, YY); } if (func2.at(key).count(xnor2_func)) { - SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? Y : module->NotGate(NEW_ID, Y); + SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? Y : module->NotGate(NEWER_ID, Y); for (auto bit : func2.at(key).at(xnor2_func)) assign_new_driver(bit, YY); } - SigBit XX = invert_xy != f2i.inv_y ? module->NotGate(NEW_ID, X) : X; + SigBit XX = invert_xy != f2i.inv_y ? module->NotGate(NEWER_ID, X) : X; for (auto bit : func2.at(key).at(func)) assign_new_driver(bit, XX); diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc index 1ad880be087..f8e3836b0a3 100644 --- a/passes/techmap/extract_reduce.cc +++ b/passes/techmap/extract_reduce.cc @@ -270,11 +270,11 @@ struct ExtractReducePass : public Pass } if (head_cell->type == ID($_AND_)) { - module->addReduceAnd(NEW_ID, input, output); + module->addReduceAnd(NEWER_ID, input, output); } else if (head_cell->type == ID($_OR_)) { - module->addReduceOr(NEW_ID, input, output); + module->addReduceOr(NEWER_ID, input, output); } else if (head_cell->type == ID($_XOR_)) { - module->addReduceXor(NEW_ID, input, output); + module->addReduceXor(NEWER_ID, input, output); } else { log_assert(false); } diff --git a/passes/techmap/extractinv.cc b/passes/techmap/extractinv.cc index 5050e1464bc..b97de36697b 100644 --- a/passes/techmap/extractinv.cc +++ b/passes/techmap/extractinv.cc @@ -105,10 +105,10 @@ struct ExtractinvPass : public Pass { cell->parameters.erase(param_name); if (invmask.is_fully_zero()) continue; - Wire *iwire = module->addWire(NEW_ID, sig.size()); + Wire *iwire = module->addWire(NEWER_ID, sig.size()); for (int i = 0; i < sig.size(); i++) if (invmask[i] == State::S1) { - RTLIL::Cell *icell = module->addCell(NEW_ID, RTLIL::escape_id(inv_celltype)); + RTLIL::Cell *icell = module->addCell(NEWER_ID, RTLIL::escape_id(inv_celltype)); icell->setPort(RTLIL::escape_id(inv_portname), SigSpec(iwire, i)); icell->setPort(RTLIL::escape_id(inv_portname2), sig[i]); log("Inserting %s on %s.%s.%s[%d].\n", inv_celltype, log_id(module), log_id(cell->type), log_id(port.first), i); diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc index f5f225a9bf9..77c996d2dac 100644 --- a/passes/techmap/flowmap.cc +++ b/passes/techmap/flowmap.cc @@ -1411,7 +1411,7 @@ struct FlowmapWorker if ((int)input_nodes.size() < minlut) lut_a.append(RTLIL::Const(State::Sx, minlut - input_nodes.size())); - RTLIL::Cell *lut = module->addLut(NEW_ID, lut_a, lut_y, lut_table); + RTLIL::Cell *lut = module->addLut(NEWER_ID, lut_a, lut_y, lut_table); mapped_nodes.insert(node); for (auto gate_node : lut_gates[node]) { @@ -1432,7 +1432,7 @@ struct FlowmapWorker { auto origin = node_origins[node]; RTLIL::SigSpec driver = origin.cell->getPort(origin.port); - driver[origin.offset] = module->addWire(NEW_ID); + driver[origin.offset] = module->addWire(NEWER_ID); origin.cell->setPort(origin.port, driver); } } diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc index c1b94722159..4239e64b9a8 100644 --- a/passes/techmap/hilomap.cc +++ b/passes/techmap/hilomap.cc @@ -36,16 +36,16 @@ void hilomap_worker(RTLIL::SigSpec &sig) for (auto &bit : sig) { if (bit == RTLIL::State::S1 && !hicell_celltype.empty()) { if (!singleton_mode || last_hi == RTLIL::State::Sm) { - last_hi = module->addWire(NEW_ID); - RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(hicell_celltype)); + last_hi = module->addWire(NEWER_ID); + RTLIL::Cell *cell = module->addCell(NEWER_ID, RTLIL::escape_id(hicell_celltype)); cell->setPort(RTLIL::escape_id(hicell_portname), last_hi); } bit = last_hi; } if (bit == RTLIL::State::S0 && !locell_celltype.empty()) { if (!singleton_mode || last_lo == RTLIL::State::Sm) { - last_lo = module->addWire(NEW_ID); - RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(locell_celltype)); + last_lo = module->addWire(NEWER_ID); + RTLIL::Cell *cell = module->addCell(NEWER_ID, RTLIL::escape_id(locell_celltype)); cell->setPort(RTLIL::escape_id(locell_portname), last_lo); } bit = last_lo; diff --git a/passes/techmap/insbuf.cc b/passes/techmap/insbuf.cc index f288987a116..7e78ed5c804 100644 --- a/passes/techmap/insbuf.cc +++ b/passes/techmap/insbuf.cc @@ -94,7 +94,7 @@ struct InsbufPass : public Pass { sigmap.add(outbit); } - Cell *cell = module->addCell(NEW_ID, celltype); + Cell *cell = module->addCell(NEWER_ID, celltype); cell->setPort(in_portname, rhs); cell->setPort(out_portname, lhs); diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index d929de30074..d98400d34b9 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -331,7 +331,7 @@ struct IopadmapPass : public Pass { RTLIL::escape_id(tinoutpad_celltype)); if (tinoutpad_neg_oe) - en_sig = module->NotGate(NEW_ID, en_sig); + en_sig = module->NotGate(NEWER_ID, en_sig); cell->setPort(RTLIL::escape_id(tinoutpad_portname_oe), en_sig); cell->attributes[ID::keep] = RTLIL::Const(1); @@ -355,7 +355,7 @@ struct IopadmapPass : public Pass { RTLIL::escape_id(toutpad_celltype)); if (toutpad_neg_oe) - en_sig = module->NotGate(NEW_ID, en_sig); + en_sig = module->NotGate(NEWER_ID, en_sig); cell->setPort(RTLIL::escape_id(toutpad_portname_oe), en_sig); cell->setPort(RTLIL::escape_id(toutpad_portname_i), data_sig); cell->attributes[ID::keep] = RTLIL::Const(1); diff --git a/passes/techmap/lut2mux.cc b/passes/techmap/lut2mux.cc index ef76e0deb5d..ec7a6c1b954 100644 --- a/passes/techmap/lut2mux.cc +++ b/passes/techmap/lut2mux.cc @@ -32,22 +32,22 @@ int lut2mux(Cell *cell) if (GetSize(sig_a) == 1) { - cell->module->addMuxGate(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y); + cell->module->addMuxGate(NEWER_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y); } else { SigSpec sig_a_hi = sig_a[GetSize(sig_a)-1]; SigSpec sig_a_lo = sig_a.extract(0, GetSize(sig_a)-1); - SigSpec sig_y1 = cell->module->addWire(NEW_ID); - SigSpec sig_y2 = cell->module->addWire(NEW_ID); + SigSpec sig_y1 = cell->module->addWire(NEWER_ID); + SigSpec sig_y2 = cell->module->addWire(NEWER_ID); Const lut1 = lut.extract(0, GetSize(lut)/2); Const lut2 = lut.extract(GetSize(lut)/2, GetSize(lut)/2); - count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y1, lut1)); - count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y2, lut2)); + count += lut2mux(cell->module->addLut(NEWER_ID, sig_a_lo, sig_y1, lut1)); + count += lut2mux(cell->module->addLut(NEWER_ID, sig_a_lo, sig_y2, lut2)); - cell->module->addMuxGate(NEW_ID, sig_y1, sig_y2, sig_a_hi, sig_y); + cell->module->addMuxGate(NEWER_ID, sig_y1, sig_y2, sig_a_hi, sig_y); } cell->module->remove(cell); diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc index 42b6150021e..39b3a5ceac4 100644 --- a/passes/techmap/maccmap.cc +++ b/passes/techmap/maccmap.cc @@ -52,7 +52,7 @@ struct MaccmapWorker a.extend_u0(width, is_signed); if (do_subtract) { - a = module->Not(NEW_ID, a); + a = module->Not(NEWER_ID, a); add(State::S1, 0); } @@ -73,13 +73,13 @@ struct MaccmapWorker for (int i = 0; i < GetSize(b); i++) if (is_signed && i+1 == GetSize(b)) { - a = {module->Not(NEW_ID, a.extract(i, width-i)), RTLIL::SigSpec(0, i)}; - add(module->And(NEW_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract); + a = {module->Not(NEWER_ID, a.extract(i, width-i)), RTLIL::SigSpec(0, i)}; + add(module->And(NEWER_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract); add({b[i], RTLIL::SigSpec(0, i)}, false, do_subtract); } else { - add(module->And(NEW_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract); + add(module->And(NEWER_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract); a = {a.extract(0, width-1), State::S0}; } } @@ -108,10 +108,10 @@ struct MaccmapWorker in3 = in3.extract(start_index, stop_index-start_index); int width = GetSize(in1); - RTLIL::Wire *w1 = module->addWire(NEW_ID, width); - RTLIL::Wire *w2 = module->addWire(NEW_ID, width); + RTLIL::Wire *w1 = module->addWire(NEWER_ID, width); + RTLIL::Wire *w2 = module->addWire(NEWER_ID, width); - RTLIL::Cell *cell = module->addCell(NEW_ID, ID($fa)); + RTLIL::Cell *cell = module->addCell(NEWER_ID, ID($fa)); cell->setParam(ID::WIDTH, width); cell->setPort(ID::A, in1); cell->setPort(ID::B, in2); @@ -237,14 +237,14 @@ struct MaccmapWorker } - RTLIL::Cell *c = module->addCell(NEW_ID, ID($alu)); + RTLIL::Cell *c = module->addCell(NEWER_ID, ID($alu)); c->setPort(ID::A, summands.front()); c->setPort(ID::B, summands.back()); c->setPort(ID::CI, State::S0); c->setPort(ID::BI, State::S0); - c->setPort(ID::Y, module->addWire(NEW_ID, width)); - c->setPort(ID::X, module->addWire(NEW_ID, width)); - c->setPort(ID::CO, module->addWire(NEW_ID, width)); + c->setPort(ID::Y, module->addWire(NEWER_ID, width)); + c->setPort(ID::X, module->addWire(NEWER_ID, width)); + c->setPort(ID::CO, module->addWire(NEWER_ID, width)); c->fixup_parameters(); if (!tree_sum_bits.empty()) { @@ -296,16 +296,16 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap) for (auto &term : macc.terms) { summand_t this_summand; if (GetSize(term.in_b)) { - this_summand.first = module->addWire(NEW_ID, width); - module->addMul(NEW_ID, term.in_a, term.in_b, this_summand.first, term.is_signed); + this_summand.first = module->addWire(NEWER_ID, width); + module->addMul(NEWER_ID, term.in_a, term.in_b, this_summand.first, term.is_signed); } else if (GetSize(term.in_a) == 1 && GetSize(term.in_b) == 0 && !term.is_signed && !term.do_subtract) { // Mimic old 'bit_terms' treatment in case it's relevant for performance, // i.e. defer single-bit summands to be the last ones bit_terms.append(term.in_a); continue; } else if (GetSize(term.in_a) != width) { - this_summand.first = module->addWire(NEW_ID, width); - module->addPos(NEW_ID, term.in_a, this_summand.first, term.is_signed); + this_summand.first = module->addWire(NEWER_ID, width); + module->addPos(NEWER_ID, term.in_a, this_summand.first, term.is_signed); } else { this_summand.first = term.in_a; } @@ -325,14 +325,14 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap) for (int i = 0; i < GetSize(summands); i += 2) { if (i+1 < GetSize(summands)) { summand_t this_summand; - this_summand.first = module->addWire(NEW_ID, width); + this_summand.first = module->addWire(NEWER_ID, width); this_summand.second = summands[i].second && summands[i+1].second; if (summands[i].second == summands[i+1].second) - module->addAdd(NEW_ID, summands[i].first, summands[i+1].first, this_summand.first); + module->addAdd(NEWER_ID, summands[i].first, summands[i+1].first, this_summand.first); else if (summands[i].second) - module->addSub(NEW_ID, summands[i+1].first, summands[i].first, this_summand.first); + module->addSub(NEWER_ID, summands[i+1].first, summands[i].first, this_summand.first); else if (summands[i+1].second) - module->addSub(NEW_ID, summands[i].first, summands[i+1].first, this_summand.first); + module->addSub(NEWER_ID, summands[i].first, summands[i+1].first, this_summand.first); else log_abort(); new_summands.push_back(this_summand); @@ -343,7 +343,7 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap) } if (summands.front().second) - module->addNeg(NEW_ID, summands.front().first, cell->getPort(ID::Y)); + module->addNeg(NEWER_ID, summands.front().first, cell->getPort(ID::Y)); else module->connect(cell->getPort(ID::Y), summands.front().first); } diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc index 2656f30ce56..e90cc53566e 100644 --- a/passes/techmap/muxcover.cc +++ b/passes/techmap/muxcover.cc @@ -185,7 +185,7 @@ struct MuxcoverWorker tuple key(A, B, sel); if (decode_mux_cache.count(key) == 0) { auto &entry = decode_mux_cache[key]; - std::get<0>(entry) = module->addWire(NEW_ID); + std::get<0>(entry) = module->addWire(NEWER_ID); std::get<2>(entry) = false; decode_mux_reverse_cache[std::get<0>(entry)] = key; } @@ -215,11 +215,11 @@ struct MuxcoverWorker implement_decode_mux(std::get<1>(key)); if (std::get<0>(key) == State::Sx) { - module->addBufGate(NEW_ID, std::get<1>(key), ctrl_bit); + module->addBufGate(NEWER_ID, std::get<1>(key), ctrl_bit); } else if (std::get<1>(key) == State::Sx) { - module->addBufGate(NEW_ID, std::get<0>(key), ctrl_bit); + module->addBufGate(NEWER_ID, std::get<0>(key), ctrl_bit); } else { - module->addMuxGate(NEW_ID, std::get<0>(key), std::get<1>(key), std::get<2>(key), ctrl_bit); + module->addMuxGate(NEWER_ID, std::get<0>(key), std::get<1>(key), std::get<2>(key), ctrl_bit); decode_mux_counter++; } std::get<2>(entry) = true; @@ -513,7 +513,7 @@ struct MuxcoverWorker if (GetSize(mux.inputs) == 2) { count_muxes_by_type[0]++; - Cell *cell = module->addCell(NEW_ID, ID($_MUX_)); + Cell *cell = module->addCell(NEWER_ID, ID($_MUX_)); cell->setPort(ID::A, mux.inputs[0]); cell->setPort(ID::B, mux.inputs[1]); cell->setPort(ID::S, mux.selects[0]); @@ -523,7 +523,7 @@ struct MuxcoverWorker if (GetSize(mux.inputs) == 4) { count_muxes_by_type[1]++; - Cell *cell = module->addCell(NEW_ID, ID($_MUX4_)); + Cell *cell = module->addCell(NEWER_ID, ID($_MUX4_)); cell->setPort(ID::A, mux.inputs[0]); cell->setPort(ID::B, mux.inputs[1]); cell->setPort(ID::C, mux.inputs[2]); @@ -536,7 +536,7 @@ struct MuxcoverWorker if (GetSize(mux.inputs) == 8) { count_muxes_by_type[2]++; - Cell *cell = module->addCell(NEW_ID, ID($_MUX8_)); + Cell *cell = module->addCell(NEWER_ID, ID($_MUX8_)); cell->setPort(ID::A, mux.inputs[0]); cell->setPort(ID::B, mux.inputs[1]); cell->setPort(ID::C, mux.inputs[2]); @@ -554,7 +554,7 @@ struct MuxcoverWorker if (GetSize(mux.inputs) == 16) { count_muxes_by_type[3]++; - Cell *cell = module->addCell(NEW_ID, ID($_MUX16_)); + Cell *cell = module->addCell(NEWER_ID, ID($_MUX16_)); cell->setPort(ID::A, mux.inputs[0]); cell->setPort(ID::B, mux.inputs[1]); cell->setPort(ID::C, mux.inputs[2]); diff --git a/passes/techmap/pmuxtree.cc b/passes/techmap/pmuxtree.cc index ff6bb549bdf..a59341546a1 100644 --- a/passes/techmap/pmuxtree.cc +++ b/passes/techmap/pmuxtree.cc @@ -32,9 +32,9 @@ static SigSpec or_generator(Module *module, const SigSpec &sig) case 1: return sig; case 2: - return module->Or(NEW_ID, sig[0], sig[1]); + return module->Or(NEWER_ID, sig[0], sig[1]); default: - return module->ReduceOr(NEW_ID, sig); + return module->ReduceOr(NEWER_ID, sig); } } @@ -62,7 +62,7 @@ static SigSpec recursive_mux_generator(Module *module, const SigSpec &sig_data, left_or = or_generator(module, left_or); sig_or.append(left_or); - return module->Mux(NEW_ID, right_result, left_result, left_or); + return module->Mux(NEWER_ID, right_result, left_result, left_or); } struct PmuxtreePass : public Pass { @@ -97,8 +97,8 @@ struct PmuxtreePass : public Pass { if (!cell->getPort(ID::A).is_fully_undef()) { sig_data.append(cell->getPort(ID::A)); - SigSpec sig_sel_or = module->ReduceOr(NEW_ID, sig_sel); - sig_sel.append(module->Not(NEW_ID, sig_sel_or)); + SigSpec sig_sel_or = module->ReduceOr(NEWER_ID, sig_sel); + sig_sel.append(module->Not(NEWER_ID, sig_sel_or)); } SigSpec result, result_or; diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 9281829700f..2a8f3fbcf45 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -75,7 +75,7 @@ struct ShregmapTechGreenpak4 : ShregmapTech auto D = cell->getPort(ID::D); auto C = cell->getPort(ID::C); - auto newcell = cell->module->addCell(NEW_ID, ID(GP_SHREG)); + auto newcell = cell->module->addCell(NEWER_ID, ID(GP_SHREG)); newcell->setPort(ID(nRST), State::S1); newcell->setPort(ID::CLK, C); newcell->setPort(ID(IN), D); @@ -142,7 +142,7 @@ struct ShregmapWorker // so that it can be identified as another chain // (omitting this common flop) // Link: https://github.com/YosysHQ/yosys/pull/1085 - Wire *wire = module->addWire(NEW_ID); + Wire *wire = module->addWire(NEWER_ID); module->connect(wire, d_bit); sigmap.add(wire, d_bit); sigbit_chain_next.insert(std::make_pair(wire, cell)); diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index b2398577023..b3bb544e9e2 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -35,7 +35,7 @@ void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell) sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool()); for (int i = 0; i < GetSize(sig_y); i++) { - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); + RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_NOT_)); gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::Y, sig_y[i]); @@ -80,7 +80,7 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) log_assert(!gate_type.empty()); for (int i = 0; i < GetSize(sig_y); i++) { - RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); + RTLIL::Cell *gate = module->addCell(NEWER_ID, gate_type); gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_b[i]); @@ -122,7 +122,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) while (sig_a.size() > 1) { - RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.size() / 2); + RTLIL::SigSpec sig_t = module->addWire(NEWER_ID, sig_a.size() / 2); for (int i = 0; i < sig_a.size(); i += 2) { @@ -131,7 +131,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) continue; } - RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); + RTLIL::Cell *gate = module->addCell(NEWER_ID, gate_type); gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_a[i+1]); @@ -143,8 +143,8 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) } if (cell->type == ID($reduce_xnor)) { - RTLIL::SigSpec sig_t = module->addWire(NEW_ID); - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); + RTLIL::SigSpec sig_t = module->addWire(NEWER_ID); + RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_NOT_)); gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a); gate->setPort(ID::Y, sig_t); @@ -163,7 +163,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell { while (sig.size() > 1) { - RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.size() / 2); + RTLIL::SigSpec sig_t = module->addWire(NEWER_ID, sig.size() / 2); for (int i = 0; i < sig.size(); i += 2) { @@ -172,7 +172,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell continue; } - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_OR_)); + RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_OR_)); gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig[i]); gate->setPort(ID::B, sig[i+1]); @@ -201,7 +201,7 @@ void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell) sig_y = sig_y.extract(0, 1); } - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); + RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_NOT_)); gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a); gate->setPort(ID::Y, sig_y); @@ -230,7 +230,7 @@ void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell) if (cell->type == ID($logic_or)) gate_type = ID($_OR_); log_assert(!gate_type.empty()); - RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); + RTLIL::Cell *gate = module->addCell(NEWER_ID, gate_type); gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a); gate->setPort(ID::B, sig_b); @@ -245,20 +245,20 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell) bool is_signed = cell->parameters.at(ID::A_SIGNED).as_bool(); bool is_ne = cell->type.in(ID($ne), ID($nex)); - RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b))); - RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed); + RTLIL::SigSpec xor_out = module->addWire(NEWER_ID, max(GetSize(sig_a), GetSize(sig_b))); + RTLIL::Cell *xor_cell = module->addXor(NEWER_ID, sig_a, sig_b, xor_out, is_signed); xor_cell->attributes[ID::src] = cell->attributes[ID::src]; simplemap_bitop(module, xor_cell); module->remove(xor_cell); - RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID); - RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out); + RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEWER_ID); + RTLIL::Cell *reduce_cell = module->addReduceOr(NEWER_ID, xor_out, reduce_out); reduce_cell->attributes[ID::src] = cell->attributes[ID::src]; simplemap_reduce(module, reduce_cell); module->remove(reduce_cell); if (!is_ne) { - RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID, reduce_out, sig_y); + RTLIL::Cell *not_cell = module->addLogicNot(NEWER_ID, reduce_out, sig_y); not_cell->attributes[ID::src] = cell->attributes[ID::src]; simplemap_lognot(module, not_cell); module->remove(not_cell); @@ -272,7 +272,7 @@ void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_y = cell->getPort(ID::Y); for (int i = 0; i < GetSize(sig_y); i++) { - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); + RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_MUX_)); gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_b[i]); @@ -289,7 +289,7 @@ void simplemap_bwmux(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_y = cell->getPort(ID::Y); for (int i = 0; i < GetSize(sig_y); i++) { - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); + RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_MUX_)); gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_b[i]); @@ -305,7 +305,7 @@ void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_y = cell->getPort(ID::Y); for (int i = 0; i < GetSize(sig_y); i++) { - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_TBUF_)); + RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_TBUF_)); gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::E, sig_e); @@ -320,10 +320,10 @@ void simplemap_bmux(RTLIL::Module *module, RTLIL::Cell *cell) int width = GetSize(cell->getPort(ID::Y)); for (int idx = 0; idx < GetSize(sel); idx++) { - SigSpec new_data = module->addWire(NEW_ID, GetSize(data)/2); + SigSpec new_data = module->addWire(NEWER_ID, GetSize(data)/2); for (int i = 0; i < GetSize(new_data); i += width) { for (int k = 0; k < width; k++) { - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); + RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_MUX_)); gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, data[i*2+k]); gate->setPort(ID::B, data[i*2+width+k]); @@ -344,9 +344,9 @@ void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell) lut_data.extend_u0(1 << cell->getParam(ID::WIDTH).as_int()); for (int idx = 0; GetSize(lut_data) > 1; idx++) { - SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data)/2); + SigSpec new_lut_data = module->addWire(NEWER_ID, GetSize(lut_data)/2); for (int i = 0; i < GetSize(lut_data); i += 2) { - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); + RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_MUX_)); gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, lut_data[i]); gate->setPort(ID::B, lut_data[i+1]); @@ -383,10 +383,10 @@ void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell) } } - products.append(GetSize(in) > 0 ? module->Eq(NEW_ID, in, pat) : State::S1); + products.append(GetSize(in) > 0 ? module->Eq(NEWER_ID, in, pat) : State::S1); } - module->connect(cell->getPort(ID::Y), module->ReduceOr(NEW_ID, products)); + module->connect(cell->getPort(ID::Y), module->ReduceOr(NEWER_ID, products)); } void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell) diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 281a8795aa1..c51fd45a7b0 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -205,7 +205,7 @@ struct TechmapWorker RTLIL::Wire *w = module->wire(w_name); if (w != nullptr) { temp_renamed_wires[w] = w->name; - module->rename(w, NEW_ID); + module->rename(w, NEWER_ID); w = nullptr; } if (w == nullptr) { @@ -792,7 +792,7 @@ struct TechmapWorker continue; IdString port_name = wire->name; - tpl->rename(wire, NEW_ID); + tpl->rename(wire, NEWER_ID); RTLIL::Wire *new_wire = tpl->addWire(port_name, wire); wire->port_input = false; diff --git a/passes/techmap/tribuf.cc b/passes/techmap/tribuf.cc index b45cd268a00..fa99d967e92 100644 --- a/passes/techmap/tribuf.cc +++ b/passes/techmap/tribuf.cc @@ -93,7 +93,7 @@ struct TribufWorker { } if (is_all_z(cell->getPort(ID::B))) { - cell->setPort(en_port, module->Not(NEW_ID, cell->getPort(ID::S))); + cell->setPort(en_port, module->Not(NEWER_ID, cell->getPort(ID::S))); cell->unsetPort(ID::B); cell->unsetPort(ID::S); cell->type = tri_type; @@ -138,12 +138,12 @@ struct TribufWorker { auto cell_s = cell->type == ID($tribuf) ? cell->getPort(ID::EN) : cell->getPort(ID::E); - auto other_s = module->ReduceOr(NEW_ID, others_s); + auto other_s = module->ReduceOr(NEWER_ID, others_s); - auto conflict = module->And(NEW_ID, cell_s, other_s); + auto conflict = module->And(NEWER_ID, cell_s, other_s); std::string name = stringf("$tribuf_conflict$%s", log_id(cell->name)); - auto assert_cell = module->addAssert(name, module->Not(NEW_ID, conflict), SigSpec(true)); + auto assert_cell = module->addAssert(name, module->Not(NEWER_ID, conflict), SigSpec(true)); assert_cell->set_src_attribute(cell->get_src_attribute()); assert_cell->set_bool_attribute(ID::keep); @@ -162,12 +162,12 @@ struct TribufWorker { module->remove(cell); } - SigSpec muxout = GetSize(pmux_s) > 1 ? module->Pmux(NEW_ID, SigSpec(State::Sx, GetSize(it.first)), pmux_b, pmux_s) : pmux_b; + SigSpec muxout = GetSize(pmux_s) > 1 ? module->Pmux(NEWER_ID, SigSpec(State::Sx, GetSize(it.first)), pmux_b, pmux_s) : pmux_b; if (no_tribuf) module->connect(it.first, muxout); else { - module->addTribuf(NEW_ID, muxout, module->ReduceOr(NEW_ID, pmux_s), it.first); + module->addTribuf(NEWER_ID, muxout, module->ReduceOr(NEWER_ID, pmux_s), it.first); module->design->scratchpad_set_bool("tribuf.added_something", true); } } diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 75a63b2e082..ee7d55e263b 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -364,9 +364,9 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce } if (muxdiv && cell_type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) { - auto b_not_zero = module->ReduceBool(NEW_ID, cell->getPort(ID::B)); - auto div_out = module->addWire(NEW_ID, GetSize(cell->getPort(ID::Y))); - module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort(ID::Y)); + auto b_not_zero = module->ReduceBool(NEWER_ID, cell->getPort(ID::B)); + auto div_out = module->addWire(NEWER_ID, GetSize(cell->getPort(ID::Y))); + module->addMux(NEWER_ID, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort(ID::Y)); cell->setPort(ID::Y, div_out); } diff --git a/techlibs/anlogic/anlogic_fixcarry.cc b/techlibs/anlogic/anlogic_fixcarry.cc index e8d061b9317..77a124c29be 100644 --- a/techlibs/anlogic/anlogic_fixcarry.cc +++ b/techlibs/anlogic/anlogic_fixcarry.cc @@ -79,9 +79,9 @@ static void fix_carry_chain(Module *module) SigBit canonical_bit = sigmap(bit_ci); auto bit = mapping_bits.at(canonical_bit); log("Fixing %s cell named %s breaking carry chain.\n", log_id(cell->type), log_id(cell)); - Cell *c = module->addCell(NEW_ID, ID(AL_MAP_ADDER)); - SigBit new_bit = module->addWire(NEW_ID); - SigBit dummy_bit = module->addWire(NEW_ID); + Cell *c = module->addCell(NEWER_ID, ID(AL_MAP_ADDER)); + SigBit new_bit = module->addWire(NEWER_ID); + SigBit dummy_bit = module->addWire(NEWER_ID); SigSpec bits; bits.append(dummy_bit); bits.append(new_bit); diff --git a/techlibs/efinix/efinix_fixcarry.cc b/techlibs/efinix/efinix_fixcarry.cc index c61fa79b8a4..dcaa5eb4441 100644 --- a/techlibs/efinix/efinix_fixcarry.cc +++ b/techlibs/efinix/efinix_fixcarry.cc @@ -75,8 +75,8 @@ static void fix_carry_chain(Module *module) SigBit canonical_bit = sigmap(bit_ci); auto bit = mapping_bits.at(canonical_bit); log("Fixing %s cell named %s breaking carry chain.\n", log_id(cell->type), log_id(cell)); - Cell *c = module->addCell(NEW_ID, ID(EFX_ADD)); - SigBit new_bit = module->addWire(NEW_ID); + Cell *c = module->addCell(NEWER_ID, ID(EFX_ADD)); + SigBit new_bit = module->addWire(NEWER_ID); c->setParam(ID(I0_POLARITY), State::S1); c->setParam(ID(I1_POLARITY), State::S1); c->setPort(ID(I0), bit); diff --git a/techlibs/gatemate/gatemate_foldinv.cc b/techlibs/gatemate/gatemate_foldinv.cc index 1af6a8987e6..4ad2107e637 100644 --- a/techlibs/gatemate/gatemate_foldinv.cc +++ b/techlibs/gatemate/gatemate_foldinv.cc @@ -162,7 +162,7 @@ struct FoldInvWorker { continue; // Create a duplicate of the LUT with an inverted output // (if the uninverted version becomes unused it will be swept away) - Cell *dup_lut = module->addCell(NEW_ID, orig_lut->type); + Cell *dup_lut = module->addCell(NEWER_ID, orig_lut->type); inv->unsetPort(ID::Y); dup_lut->setPort(ID::O, inv_y); for (auto conn : orig_lut->connections()) { diff --git a/techlibs/ice40/ice40_dsp.cc b/techlibs/ice40/ice40_dsp.cc index 995cdb97e33..a1f31c77905 100644 --- a/techlibs/ice40/ice40_dsp.cc +++ b/techlibs/ice40/ice40_dsp.cc @@ -66,7 +66,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm) if (cell->type == ID($mul)) { log(" replacing %s with SB_MAC16 cell.\n", log_id(st.mul->type)); - cell = pm.module->addCell(NEW_ID, ID(SB_MAC16)); + cell = pm.module->addCell(NEWER_ID, ID(SB_MAC16)); pm.module->swap_names(cell, st.mul); } else log_assert(cell->type == ID(SB_MAC16)); @@ -98,15 +98,15 @@ void create_ice40_dsp(ice40_dsp_pm &pm) SigSpec AHOLD, BHOLD, CDHOLD; if (st.ffA && st.ffA->hasPort(ID::EN)) - AHOLD = st.ffA->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_ID, st.ffA->getPort(ID::EN)) : st.ffA->getPort(ID::EN); + AHOLD = st.ffA->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEWER_ID, st.ffA->getPort(ID::EN)) : st.ffA->getPort(ID::EN); else AHOLD = State::S0; if (st.ffB && st.ffB->hasPort(ID::EN)) - BHOLD = st.ffB->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_ID, st.ffB->getPort(ID::EN)) : st.ffB->getPort(ID::EN); + BHOLD = st.ffB->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEWER_ID, st.ffB->getPort(ID::EN)) : st.ffB->getPort(ID::EN); else BHOLD = State::S0; if (st.ffCD && st.ffCD->hasPort(ID::EN)) - CDHOLD = st.ffCD->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_ID, st.ffCD->getPort(ID::EN)) : st.ffCD->getPort(ID::EN); + CDHOLD = st.ffCD->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEWER_ID, st.ffCD->getPort(ID::EN)) : st.ffCD->getPort(ID::EN); else CDHOLD = State::S0; cell->setPort(ID(AHOLD), AHOLD); @@ -116,11 +116,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm) SigSpec IRSTTOP, IRSTBOT; if (st.ffA && st.ffA->hasPort(ID::ARST)) - IRSTTOP = st.ffA->getParam(ID::ARST_POLARITY).as_bool() ? st.ffA->getPort(ID::ARST) : pm.module->Not(NEW_ID, st.ffA->getPort(ID::ARST)); + IRSTTOP = st.ffA->getParam(ID::ARST_POLARITY).as_bool() ? st.ffA->getPort(ID::ARST) : pm.module->Not(NEWER_ID, st.ffA->getPort(ID::ARST)); else IRSTTOP = State::S0; if (st.ffB && st.ffB->hasPort(ID::ARST)) - IRSTBOT = st.ffB->getParam(ID::ARST_POLARITY).as_bool() ? st.ffB->getPort(ID::ARST) : pm.module->Not(NEW_ID, st.ffB->getPort(ID::ARST)); + IRSTBOT = st.ffB->getParam(ID::ARST_POLARITY).as_bool() ? st.ffB->getPort(ID::ARST) : pm.module->Not(NEWER_ID, st.ffB->getPort(ID::ARST)); else IRSTBOT = State::S0; cell->setPort(ID(IRSTTOP), IRSTTOP); @@ -164,12 +164,12 @@ void create_ice40_dsp(ice40_dsp_pm &pm) // SB_MAC16 Cascade Interface cell->setPort(ID(SIGNEXTIN), State::Sx); - cell->setPort(ID(SIGNEXTOUT), pm.module->addWire(NEW_ID)); + cell->setPort(ID(SIGNEXTOUT), pm.module->addWire(NEWER_ID)); cell->setPort(ID::CI, State::Sx); cell->setPort(ID(ACCUMCI), State::Sx); - cell->setPort(ID(ACCUMCO), pm.module->addWire(NEW_ID)); + cell->setPort(ID(ACCUMCO), pm.module->addWire(NEWER_ID)); // SB_MAC16 Output Interface @@ -185,10 +185,10 @@ void create_ice40_dsp(ice40_dsp_pm &pm) O.remove(O_width-1); } else - cell->setPort(ID::CO, pm.module->addWire(NEW_ID)); + cell->setPort(ID::CO, pm.module->addWire(NEWER_ID)); log_assert(GetSize(O) <= 32); if (GetSize(O) < 32) - O.append(pm.module->addWire(NEW_ID, 32-GetSize(O))); + O.append(pm.module->addWire(NEWER_ID, 32-GetSize(O))); cell->setPort(ID::O, O); @@ -208,7 +208,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm) SigSpec OHOLD; if (st.ffO && st.ffO->hasPort(ID::EN)) - OHOLD = st.ffO->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_ID, st.ffO->getPort(ID::EN)) : st.ffO->getPort(ID::EN); + OHOLD = st.ffO->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEWER_ID, st.ffO->getPort(ID::EN)) : st.ffO->getPort(ID::EN); else OHOLD = State::S0; cell->setPort(ID(OHOLDTOP), OHOLD); @@ -216,7 +216,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm) SigSpec ORST; if (st.ffO && st.ffO->hasPort(ID::ARST)) - ORST = st.ffO->getParam(ID::ARST_POLARITY).as_bool() ? st.ffO->getPort(ID::ARST) : pm.module->Not(NEW_ID, st.ffO->getPort(ID::ARST)); + ORST = st.ffO->getParam(ID::ARST_POLARITY).as_bool() ? st.ffO->getPort(ID::ARST) : pm.module->Not(NEWER_ID, st.ffO->getPort(ID::ARST)); else ORST = State::S0; cell->setPort(ID(ORSTTOP), ORST); @@ -227,9 +227,9 @@ void create_ice40_dsp(ice40_dsp_pm &pm) if (st.muxAB == ID::A) acc_reset = st.mux->getPort(ID::S); else - acc_reset = pm.module->Not(NEW_ID, st.mux->getPort(ID::S)); + acc_reset = pm.module->Not(NEWER_ID, st.mux->getPort(ID::S)); } else if (st.ffO && st.ffO->hasPort(ID::SRST)) { - acc_reset = st.ffO->getParam(ID::SRST_POLARITY).as_bool() ? st.ffO->getPort(ID::SRST) : pm.module->Not(NEW_ID, st.ffO->getPort(ID::SRST)); + acc_reset = st.ffO->getParam(ID::SRST_POLARITY).as_bool() ? st.ffO->getPort(ID::SRST) : pm.module->Not(NEWER_ID, st.ffO->getPort(ID::SRST)); } cell->setPort(ID(OLOADTOP), acc_reset); cell->setPort(ID(OLOADBOT), acc_reset); @@ -259,7 +259,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm) else cell->setParam(ID(TOPOUTPUT_SELECT), Const(1, 2)); - st.ffO->connections_.at(ID::Q).replace(O, pm.module->addWire(NEW_ID, GetSize(O))); + st.ffO->connections_.at(ID::Q).replace(O, pm.module->addWire(NEWER_ID, GetSize(O))); cell->setParam(ID(BOTOUTPUT_SELECT), Const(1, 2)); } else { diff --git a/techlibs/ice40/ice40_dsp.pmg b/techlibs/ice40/ice40_dsp.pmg index 7e4c3ace2e4..3d8e9c6a707 100644 --- a/techlibs/ice40/ice40_dsp.pmg +++ b/techlibs/ice40/ice40_dsp.pmg @@ -66,7 +66,7 @@ code sigA sigB sigH wire_width++; else { if (wire_width) { // add empty wires for bit offset if needed - sigH.append(module->addWire(NEW_ID, wire_width)); + sigH.append(module->addWire(NEWER_ID, wire_width)); wire_width = 0; } sigH.append(O[j]); diff --git a/techlibs/ice40/ice40_wrapcarry.cc b/techlibs/ice40/ice40_wrapcarry.cc index fe928ba6da1..d24a33c620c 100644 --- a/techlibs/ice40/ice40_wrapcarry.cc +++ b/techlibs/ice40/ice40_wrapcarry.cc @@ -37,7 +37,7 @@ void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm) log(" replacing SB_LUT + SB_CARRY with $__ICE40_CARRY_WRAPPER cell.\n"); - Cell *cell = pm.module->addCell(NEW_ID, ID($__ICE40_CARRY_WRAPPER)); + Cell *cell = pm.module->addCell(NEWER_ID, ID($__ICE40_CARRY_WRAPPER)); pm.module->swap_names(cell, st.carry); cell->setPort(ID::A, st.carry->getPort(ID(I0))); @@ -116,13 +116,13 @@ struct Ice40WrapCarryPass : public Pass { if (cell->type != ID($__ICE40_CARRY_WRAPPER)) continue; - auto carry = module->addCell(NEW_ID, ID(SB_CARRY)); + auto carry = module->addCell(NEWER_ID, ID(SB_CARRY)); carry->setPort(ID(I0), cell->getPort(ID::A)); carry->setPort(ID(I1), cell->getPort(ID::B)); carry->setPort(ID::CI, cell->getPort(ID::CI)); carry->setPort(ID::CO, cell->getPort(ID::CO)); module->swap_names(carry, cell); - auto lut_name = cell->attributes.at(ID(SB_LUT4.name), Const(NEW_ID.str())).decode_string(); + auto lut_name = cell->attributes.at(ID(SB_LUT4.name), Const(NEWER_ID.str())).decode_string(); auto lut = module->addCell(lut_name, ID($lut)); lut->setParam(ID::WIDTH, 4); lut->setParam(ID::LUT, cell->getParam(ID::LUT)); diff --git a/techlibs/microchip/microchip_dffopt.cc b/techlibs/microchip/microchip_dffopt.cc index 98e2f17a757..b45a354d82a 100644 --- a/techlibs/microchip/microchip_dffopt.cc +++ b/techlibs/microchip/microchip_dffopt.cc @@ -309,22 +309,22 @@ struct MicrochipDffOptPass : public Pass { Cell *lut_cell = nullptr; switch (GetSize(final_lut.second)) { case 1: - lut_cell = module->addCell(NEW_ID, ID(CFG1)); + lut_cell = module->addCell(NEWER_ID, ID(CFG1)); break; case 2: - lut_cell = module->addCell(NEW_ID, ID(CFG2)); + lut_cell = module->addCell(NEWER_ID, ID(CFG2)); break; case 3: - lut_cell = module->addCell(NEW_ID, ID(CFG3)); + lut_cell = module->addCell(NEWER_ID, ID(CFG3)); break; case 4: - lut_cell = module->addCell(NEW_ID, ID(CFG4)); + lut_cell = module->addCell(NEWER_ID, ID(CFG4)); break; default: log_assert(!"unknown lut size"); } lut_cell->attributes = cell_d->attributes; - Wire *lut_out = module->addWire(NEW_ID); + Wire *lut_out = module->addWire(NEWER_ID); lut_cell->setParam(ID::INIT, final_lut.first); cell->setPort(ID::D, lut_out); lut_cell->setPort(ID::Y, lut_out); diff --git a/techlibs/microchip/microchip_dsp.cc b/techlibs/microchip/microchip_dsp.cc index df7093bc518..621be227fca 100644 --- a/techlibs/microchip/microchip_dsp.cc +++ b/techlibs/microchip/microchip_dsp.cc @@ -98,12 +98,12 @@ void microchip_dsp_pack(microchip_dsp_pm &pm) SigSpec srst = ff->getPort(ID::SRST); bool rstpol_n = !ff->getParam(ID::SRST_POLARITY).as_bool(); // active low sync rst - cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEW_ID, srst)); + cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEWER_ID, srst)); } else if (ff->type.in(ID($adff), ID($adffe))) { SigSpec arst = ff->getPort(ID::ARST); bool rstpol_n = !ff->getParam(ID::ARST_POLARITY).as_bool(); // active low async rst - cell->setPort(rstport, rstpol_n ? arst : pm.module->Not(NEW_ID, arst)); + cell->setPort(rstport, rstpol_n ? arst : pm.module->Not(NEWER_ID, arst)); } else { // active low async/sync rst cell->setPort(rstport, State::S1); @@ -113,7 +113,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm) SigSpec ce = ff->getPort(ID::EN); bool cepol = ff->getParam(ID::EN_POLARITY).as_bool(); // enables are all active high - cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce)); + cell->setPort(ceport, cepol ? ce : pm.module->Not(NEWER_ID, ce)); } else { // enables are all active high cell->setPort(ceport, State::S1); @@ -165,7 +165,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm) if (st.ffP) { SigSpec P; // unused f(P, st.ffP, ID(P_EN), ID(P_SRST_N), ID(P_BYPASS)); - st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP))); + st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEWER_ID, GetSize(st.sigP))); } log(" clock: %s (%s)\n", log_signal(st.clock), "posedge"); @@ -183,7 +183,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm) SigSpec P = st.sigP; if (GetSize(P) < 48) - P.append(pm.module->addWire(NEW_ID, 48 - GetSize(P))); + P.append(pm.module->addWire(NEWER_ID, 48 - GetSize(P))); cell->setPort(ID::P, P); pm.blacklist(cell); @@ -214,12 +214,12 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm) SigSpec srst = ff->getPort(ID::SRST); bool rstpol_n = !ff->getParam(ID::SRST_POLARITY).as_bool(); // active low sync rst - cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEW_ID, srst)); + cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEWER_ID, srst)); } else if (ff->type.in(ID($adff), ID($adffe))) { SigSpec arst = ff->getPort(ID::ARST); bool rstpol_n = !ff->getParam(ID::ARST_POLARITY).as_bool(); // active low async rst - cell->setPort(rstport, rstpol_n ? arst : pm.module->Not(NEW_ID, arst)); + cell->setPort(rstport, rstpol_n ? arst : pm.module->Not(NEWER_ID, arst)); } else { // active low async/sync rst cell->setPort(rstport, State::S1); @@ -229,7 +229,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm) SigSpec ce = ff->getPort(ID::EN); bool cepol = ff->getParam(ID::EN_POLARITY).as_bool(); // enables are all active high - cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce)); + cell->setPort(ceport, cepol ? ce : pm.module->Not(NEWER_ID, ce)); } else { // enables are all active high cell->setPort(ceport, State::S1); diff --git a/techlibs/microchip/microchip_dsp_cascade.pmg b/techlibs/microchip/microchip_dsp_cascade.pmg index d7ea5911e09..6d920dff729 100644 --- a/techlibs/microchip/microchip_dsp_cascade.pmg +++ b/techlibs/microchip/microchip_dsp_cascade.pmg @@ -112,7 +112,7 @@ finally // Chain length exceeds the maximum cascade length, must split it up if (i % MAX_DSP_CASCADE > 0) { - Wire *cascade = module->addWire(NEW_ID, 48); + Wire *cascade = module->addWire(NEWER_ID, 48); // zero port C and move wire to cascade dsp_pcin->setPort(ID(C), Const(0, 48)); diff --git a/techlibs/nanoxplore/nx_carry.cc b/techlibs/nanoxplore/nx_carry.cc index 6e6a9603542..e38f25d7dfd 100644 --- a/techlibs/nanoxplore/nx_carry.cc +++ b/techlibs/nanoxplore/nx_carry.cc @@ -81,7 +81,7 @@ static void nx_carry_chain(Module *module) IdString names_B[] = { ID(B1), ID(B2), ID(B3), ID(B4) }; IdString names_S[] = { ID(S1), ID(S2), ID(S3), ID(S4) }; if (!c.second.at(0)->getPort(ID(CI)).is_fully_const()) { - cell = module->addCell(NEW_ID, ID(NX_CY)); + cell = module->addCell(NEWER_ID, ID(NX_CY)); cell->setParam(ID(add_carry), Const(1,2)); cell->setPort(ID(CI), State::S1); @@ -92,7 +92,7 @@ static void nx_carry_chain(Module *module) for (size_t i=0 ; iaddCell(NEW_ID, ID(NX_CY)); + cell = module->addCell(NEWER_ID, ID(NX_CY)); SigBit ci = c.second.at(i)->getPort(ID(CI)).as_bit(); cell->setPort(ID(CI), ci); if (ci.is_wire()) { @@ -106,11 +106,11 @@ static void nx_carry_chain(Module *module) } if (j==3) { if (cnt !=0 && (cnt % 24 == 0)) { - SigBit new_co = module->addWire(NEW_ID); + SigBit new_co = module->addWire(NEWER_ID); cell->setPort(ID(A4), State::S0); cell->setPort(ID(B4), State::S0); cell->setPort(ID(S4), new_co); - cell = module->addCell(NEW_ID, ID(NX_CY)); + cell = module->addCell(NEWER_ID, ID(NX_CY)); cell->setParam(ID(add_carry), Const(1,2)); cell->setPort(ID(CI), State::S1); cell->setPort(ID(A1), new_co); diff --git a/techlibs/quicklogic/ql_bram_merge.cc b/techlibs/quicklogic/ql_bram_merge.cc index 7b99d74e550..cf0b793eab1 100644 --- a/techlibs/quicklogic/ql_bram_merge.cc +++ b/techlibs/quicklogic/ql_bram_merge.cc @@ -127,7 +127,7 @@ struct QlBramMergeWorker { const RTLIL::IdString merged_cell_type = ID($__QLF_TDP36K_MERGED); // Create the new cell - RTLIL::Cell* merged = module->addCell(NEW_ID, merged_cell_type); + RTLIL::Cell* merged = module->addCell(NEWER_ID, merged_cell_type); log_debug("Merging split BRAM cells %s and %s -> %s\n", log_id(bram1->name), log_id(bram2->name), log_id(merged->name)); for (auto &it : param_map(false)) diff --git a/techlibs/quicklogic/ql_dsp_macc.cc b/techlibs/quicklogic/ql_dsp_macc.cc index f0669da6c9b..f82e662d20f 100644 --- a/techlibs/quicklogic/ql_dsp_macc.cc +++ b/techlibs/quicklogic/ql_dsp_macc.cc @@ -80,7 +80,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm) log(" %s (%s)\n", log_id(cell), log_id(cell->type)); // Add the DSP cell - RTLIL::Cell *cell = pm.module->addCell(NEW_ID, type); + RTLIL::Cell *cell = pm.module->addCell(NEWER_ID, type); // Set attributes cell->set_bool_attribute(ID(is_inferred), true); @@ -102,7 +102,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm) // Connect output data port, pad if needed if ((size_t) GetSize(sig_z) < tgt_z_width) { - auto *wire = pm.module->addWire(NEW_ID, tgt_z_width - GetSize(sig_z)); + auto *wire = pm.module->addWire(NEWER_ID, tgt_z_width - GetSize(sig_z)); sig_z.append(wire); } cell->setPort(ID(z_o), sig_z); @@ -115,7 +115,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm) if (st.ff->hasPort(ID(ARST))) { if (st.ff->getParam(ID(ARST_POLARITY)).as_int() != 1) { - rst = pm.module->Not(NEW_ID, st.ff->getPort(ID(ARST))); + rst = pm.module->Not(NEWER_ID, st.ff->getPort(ID(ARST))); } else { rst = st.ff->getPort(ID(ARST)); } @@ -125,7 +125,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm) if (st.ff->hasPort(ID(EN))) { if (st.ff->getParam(ID(EN_POLARITY)).as_int() != 1) { - ena = pm.module->Not(NEW_ID, st.ff->getPort(ID(EN))); + ena = pm.module->Not(NEWER_ID, st.ff->getPort(ID(EN))); } else { ena = st.ff->getPort(ID(EN)); } @@ -143,7 +143,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm) // Depending on the mux port ordering insert inverter if needed log_assert(st.mux_ab.in(ID(A), ID(B))); if (st.mux_ab == ID(A)) - sig_s = pm.module->Not(NEW_ID, sig_s); + sig_s = pm.module->Not(NEWER_ID, sig_s); // Assemble the full control signal for the feedback_i port RTLIL::SigSpec sig_f; diff --git a/techlibs/quicklogic/ql_dsp_simd.cc b/techlibs/quicklogic/ql_dsp_simd.cc index cd509ce7f71..46ecf714225 100644 --- a/techlibs/quicklogic/ql_dsp_simd.cc +++ b/techlibs/quicklogic/ql_dsp_simd.cc @@ -148,7 +148,7 @@ struct QlDspSimdPass : public Pass { Cell *dsp_b = group[i + 1]; // Create the new cell - Cell *simd = module->addCell(NEW_ID, m_SimdDspType); + Cell *simd = module->addCell(NEWER_ID, m_SimdDspType); log(" SIMD: %s (%s) + %s (%s) => %s (%s)\n", log_id(dsp_a), log_id(dsp_a->type), log_id(dsp_b), log_id(dsp_b->type), log_id(simd), log_id(simd->type)); @@ -182,7 +182,7 @@ struct QlDspSimdPass : public Pass { if (!isOutput) sigspec.append(RTLIL::SigSpec(RTLIL::Sx, padding)); else - sigspec.append(module->addWire(NEW_ID, padding)); + sigspec.append(module->addWire(NEWER_ID, padding)); } return sigspec; }; diff --git a/techlibs/quicklogic/ql_ioff.cc b/techlibs/quicklogic/ql_ioff.cc index 87b62e855f2..a3970bdd49f 100644 --- a/techlibs/quicklogic/ql_ioff.cc +++ b/techlibs/quicklogic/ql_ioff.cc @@ -91,7 +91,7 @@ struct QlIoffPass : public Pass { if (std::any_of(ioff_cells.begin(), ioff_cells.end(), [](Cell * c) { return c != nullptr; })) { // create replacement output wire - RTLIL::Wire* new_port_output = module->addWire(NEW_ID, old_port_output->width); + RTLIL::Wire* new_port_output = module->addWire(NEWER_ID, old_port_output->width); new_port_output->start_offset = old_port_output->start_offset; module->swap_names(old_port_output, new_port_output); std::swap(old_port_output->port_id, new_port_output->port_id); @@ -108,7 +108,7 @@ struct QlIoffPass : public Pass { if (ioff_cells[i]) { log("Promoting %s to output IOFF.\n", log_signal(sig_n[i])); - RTLIL::Cell *new_cell = module->addCell(NEW_ID, ID(dff)); + RTLIL::Cell *new_cell = module->addCell(NEWER_ID, ID(dff)); new_cell->setPort(ID::C, ioff_cells[i]->getPort(ID::C)); new_cell->setPort(ID::D, ioff_cells[i]->getPort(ID::D)); new_cell->setPort(ID::Q, sig_n[i]); diff --git a/techlibs/xilinx/xilinx_dffopt.cc b/techlibs/xilinx/xilinx_dffopt.cc index 8a6d3e015b8..28ab2efb539 100644 --- a/techlibs/xilinx/xilinx_dffopt.cc +++ b/techlibs/xilinx/xilinx_dffopt.cc @@ -323,28 +323,28 @@ struct XilinxDffOptPass : public Pass { Cell *lut_cell = 0; switch (GetSize(final_lut.second)) { case 1: - lut_cell = module->addCell(NEW_ID, ID(LUT1)); + lut_cell = module->addCell(NEWER_ID, ID(LUT1)); break; case 2: - lut_cell = module->addCell(NEW_ID, ID(LUT2)); + lut_cell = module->addCell(NEWER_ID, ID(LUT2)); break; case 3: - lut_cell = module->addCell(NEW_ID, ID(LUT3)); + lut_cell = module->addCell(NEWER_ID, ID(LUT3)); break; case 4: - lut_cell = module->addCell(NEW_ID, ID(LUT4)); + lut_cell = module->addCell(NEWER_ID, ID(LUT4)); break; case 5: - lut_cell = module->addCell(NEW_ID, ID(LUT5)); + lut_cell = module->addCell(NEWER_ID, ID(LUT5)); break; case 6: - lut_cell = module->addCell(NEW_ID, ID(LUT6)); + lut_cell = module->addCell(NEWER_ID, ID(LUT6)); break; default: log_assert(!"unknown lut size"); } lut_cell->attributes = cell_d->attributes; - Wire *lut_out = module->addWire(NEW_ID); + Wire *lut_out = module->addWire(NEWER_ID); lut_cell->setParam(ID::INIT, final_lut.first); cell->setPort(ID::D, lut_out); lut_cell->setPort(ID::O, lut_out); diff --git a/techlibs/xilinx/xilinx_dsp.cc b/techlibs/xilinx/xilinx_dsp.cc index 22e6bce5b22..50ba4833b87 100644 --- a/techlibs/xilinx/xilinx_dsp.cc +++ b/techlibs/xilinx/xilinx_dsp.cc @@ -31,7 +31,7 @@ PRIVATE_NAMESPACE_BEGIN #include "techlibs/xilinx/xilinx_dsp_cascade_pm.h" static Cell* addDsp(Module *module) { - Cell *cell = module->addCell(NEW_ID, ID(DSP48E1)); + Cell *cell = module->addCell(NEWER_ID, ID(DSP48E1)); cell->setParam(ID(ACASCREG), 0); cell->setParam(ID(ADREG), 0); cell->setParam(ID(A_INPUT), Const("DIRECT")); @@ -114,7 +114,7 @@ void xilinx_simd_pack(Module *module, const std::vector &selected_cells) AB.append(A); C.append(B); if (GetSize(Y) < 13) - Y.append(module->addWire(NEW_ID, 13-GetSize(Y))); + Y.append(module->addWire(NEWER_ID, 13-GetSize(Y))); else log_assert(GetSize(Y) == 13); P.append(Y.extract(0, 12)); @@ -160,15 +160,15 @@ void xilinx_simd_pack(Module *module, const std::vector &selected_cells) else { AB.append(Const(0, 12)); C.append(Const(0, 12)); - P.append(module->addWire(NEW_ID, 12)); - CARRYOUT.append(module->addWire(NEW_ID, 1)); + P.append(module->addWire(NEWER_ID, 12)); + CARRYOUT.append(module->addWire(NEWER_ID, 1)); } } else { AB.append(Const(0, 24)); C.append(Const(0, 24)); - P.append(module->addWire(NEW_ID, 24)); - CARRYOUT.append(module->addWire(NEW_ID, 2)); + P.append(module->addWire(NEWER_ID, 24)); + CARRYOUT.append(module->addWire(NEWER_ID, 2)); } log_assert(GetSize(AB) == 48); log_assert(GetSize(C) == 48); @@ -202,11 +202,11 @@ void xilinx_simd_pack(Module *module, const std::vector &selected_cells) C.append(A); AB.append(B); if (GetSize(Y) < 25) - Y.append(module->addWire(NEW_ID, 25-GetSize(Y))); + Y.append(module->addWire(NEWER_ID, 25-GetSize(Y))); else log_assert(GetSize(Y) == 25); P.append(Y.extract(0, 24)); - CARRYOUT.append(module->addWire(NEW_ID)); // TWO24 uses every other bit + CARRYOUT.append(module->addWire(NEWER_ID)); // TWO24 uses every other bit CARRYOUT.append(Y[24]); }; auto g24 = [&f24,module](std::deque &simd24) { @@ -294,7 +294,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) if (st.ffAD->type.in(ID($dffe), ID($sdffe))) { bool pol = st.ffAD->getParam(ID::EN_POLARITY).as_bool(); SigSpec S = st.ffAD->getPort(ID::EN); - cell->setPort(ID(CEAD), pol ? S : pm.module->Not(NEW_ID, S)); + cell->setPort(ID(CEAD), pol ? S : pm.module->Not(NEWER_ID, S)); } else cell->setPort(ID(CEAD), State::S1); @@ -373,7 +373,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) if (ff->type.in(ID($sdff), ID($sdffe))) { SigSpec srst = ff->getPort(ID::SRST); bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool(); - cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_ID, srst)); + cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEWER_ID, srst)); } else { cell->setPort(rstport, State::S0); } @@ -381,7 +381,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) if (ff->type.in(ID($dffe), ID($sdffe))) { SigSpec ce = ff->getPort(ID::EN); bool cepol = ff->getParam(ID::EN_POLARITY).as_bool(); - cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce)); + cell->setPort(ceport, cepol ? ce : pm.module->Not(NEWER_ID, ce)); } else cell->setPort(ceport, State::S1); @@ -437,13 +437,13 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) if (st.ffM) { SigSpec M; // unused f(M, st.ffM, ID(CEM), ID(RSTM)); - st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM))); + st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEWER_ID, GetSize(st.sigM))); cell->setParam(ID(MREG), State::S1); } if (st.ffP) { SigSpec P; // unused f(P, st.ffP, ID(CEP), ID(RSTP)); - st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP))); + st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEWER_ID, GetSize(st.sigP))); cell->setParam(ID(PREG), State::S1); } @@ -477,7 +477,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) SigSpec P = st.sigP; if (GetSize(P) < 48) - P.append(pm.module->addWire(NEW_ID, 48-GetSize(P))); + P.append(pm.module->addWire(NEWER_ID, 48-GetSize(P))); cell->setPort(ID::P, P); pm.blacklist(cell); @@ -560,7 +560,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm) if (ff->type.in(ID($sdff), ID($sdffe))) { SigSpec srst = ff->getPort(ID::SRST); bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool(); - cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_ID, srst)); + cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEWER_ID, srst)); } else { cell->setPort(rstport, State::S0); } @@ -568,7 +568,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm) if (ff->type.in(ID($dffe), ID($sdffe))) { SigSpec ce = ff->getPort(ID::EN); bool cepol = ff->getParam(ID::EN_POLARITY).as_bool(); - cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce)); + cell->setPort(ceport, cepol ? ce : pm.module->Not(NEWER_ID, ce)); } else cell->setPort(ceport, State::S1); @@ -620,13 +620,13 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm) if (st.ffM) { SigSpec M; // unused f(M, st.ffM, ID(CEM), ID(RSTM)); - st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM))); + st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEWER_ID, GetSize(st.sigM))); cell->setParam(ID(MREG), State::S1); } if (st.ffP) { SigSpec P; // unused f(P, st.ffP, ID(CEP), ID(RSTP)); - st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP))); + st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEWER_ID, GetSize(st.sigP))); cell->setParam(ID(PREG), State::S1); } @@ -655,7 +655,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm) SigSpec P = st.sigP; if (GetSize(P) < 48) - P.append(pm.module->addWire(NEW_ID, 48-GetSize(P))); + P.append(pm.module->addWire(NEWER_ID, 48-GetSize(P))); cell->setPort(ID::P, P); pm.blacklist(cell); @@ -683,7 +683,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm) if (ff->type.in(ID($sdff), ID($sdffe))) { SigSpec srst = ff->getPort(ID::SRST); bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool(); - cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_ID, srst)); + cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEWER_ID, srst)); } else { cell->setPort(rstport, State::S0); } @@ -691,7 +691,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm) if (ff->type.in(ID($dffe), ID($sdffe))) { SigSpec ce = ff->getPort(ID::EN); bool cepol = ff->getParam(ID::EN_POLARITY).as_bool(); - cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce)); + cell->setPort(ceport, cepol ? ce : pm.module->Not(NEWER_ID, ce)); } else cell->setPort(ceport, State::S1); diff --git a/techlibs/xilinx/xilinx_dsp_cascade.pmg b/techlibs/xilinx/xilinx_dsp_cascade.pmg index 29fc27dfed6..f9424eaecbe 100644 --- a/techlibs/xilinx/xilinx_dsp_cascade.pmg +++ b/techlibs/xilinx/xilinx_dsp_cascade.pmg @@ -89,7 +89,7 @@ finally if (i % MAX_DSP_CASCADE > 0) { if (P >= 0) { - Wire *cascade = module->addWire(NEW_ID, 48); + Wire *cascade = module->addWire(NEWER_ID, 48); dsp_pcin->setPort(ID(C), Const(0, 48)); dsp_pcin->setPort(ID(PCIN), cascade); dsp->setPort(ID(PCOUT), cascade); @@ -117,7 +117,7 @@ finally log_debug("PCOUT -> PCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin)); } if (AREG >= 0) { - Wire *cascade = module->addWire(NEW_ID, 30); + Wire *cascade = module->addWire(NEWER_ID, 30); dsp_pcin->setPort(ID(A), Const(0, 30)); dsp_pcin->setPort(ID(ACIN), cascade); dsp->setPort(ID(ACOUT), cascade); @@ -131,7 +131,7 @@ finally log_debug("ACOUT -> ACIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin)); } if (BREG >= 0) { - Wire *cascade = module->addWire(NEW_ID, 18); + Wire *cascade = module->addWire(NEWER_ID, 18); if (dsp->type.in(\DSP48A, \DSP48A1)) { // According to UG389 p9 [https://www.xilinx.com/support/documentation/user_guides/ug389.pdf] // "The DSP48A1 component uses this input when cascading diff --git a/techlibs/xilinx/xilinx_srl.cc b/techlibs/xilinx/xilinx_srl.cc index 2c23f8f42b5..50421a189ce 100644 --- a/techlibs/xilinx/xilinx_srl.cc +++ b/techlibs/xilinx/xilinx_srl.cc @@ -59,7 +59,7 @@ void run_fixed(xilinx_srl_pm &pm) auto first_cell = ud.longest_chain.back(); auto last_cell = ud.longest_chain.front(); - Cell *c = pm.module->addCell(NEW_ID, ID($__XILINX_SHREG_)); + Cell *c = pm.module->addCell(NEWER_ID, ID($__XILINX_SHREG_)); pm.module->swap_names(c, first_cell); if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) { @@ -134,7 +134,7 @@ void run_variable(xilinx_srl_pm &pm) auto first_cell = ud.chain.back().first; auto first_slice = ud.chain.back().second; - Cell *c = pm.module->addCell(NEW_ID, ID($__XILINX_SHREG_)); + Cell *c = pm.module->addCell(NEWER_ID, ID($__XILINX_SHREG_)); pm.module->swap_names(c, first_cell); if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) { diff --git a/techlibs/xilinx/xilinx_srl.pmg b/techlibs/xilinx/xilinx_srl.pmg index 80f0a27c29b..28694e82e76 100644 --- a/techlibs/xilinx/xilinx_srl.pmg +++ b/techlibs/xilinx/xilinx_srl.pmg @@ -18,22 +18,22 @@ match first select !first->type.in(\FDRE, \FDRE_1) || port(first, \R, State::S0).is_fully_zero() filter !non_first_cells.count(first) generate - SigSpec C = module->addWire(NEW_ID); - SigSpec D = module->addWire(NEW_ID); - SigSpec Q = module->addWire(NEW_ID); + SigSpec C = module->addWire(NEWER_ID); + SigSpec D = module->addWire(NEWER_ID); + SigSpec Q = module->addWire(NEWER_ID); auto r = rng(8); Cell* cell; switch (r) { case 0: case 1: - cell = module->addCell(NEW_ID, \FDRE); + cell = module->addCell(NEWER_ID, \FDRE); cell->setPort(\C, C); cell->setPort(\D, D); cell->setPort(\Q, Q); - cell->setPort(\CE, module->addWire(NEW_ID)); + cell->setPort(\CE, module->addWire(NEWER_ID)); if (r & 1) - cell->setPort(\R, module->addWire(NEW_ID)); + cell->setPort(\R, module->addWire(NEWER_ID)); else { if (rng(2) == 0) cell->setPort(\R, State::S0); @@ -41,13 +41,13 @@ generate break; case 2: case 3: - cell = module->addDffGate(NEW_ID, C, D, Q, r & 1); + cell = module->addDffGate(NEWER_ID, C, D, Q, r & 1); break; case 4: case 5: case 6: case 7: - cell = module->addDffeGate(NEW_ID, C, module->addWire(NEW_ID), D, Q, r & 1, r & 2); + cell = module->addDffeGate(NEWER_ID, C, module->addWire(NEWER_ID), D, Q, r & 1, r & 2); break; default: log_abort(); } @@ -143,9 +143,9 @@ match next filter !first->type.in(\FDRE) || param(next, \IS_R_INVERTED).as_bool() == param(first, \IS_R_INVERTED).as_bool() filter !first->type.in(\FDRE, \FDRE_1) || port(next, \R, State::S0).is_fully_zero() generate - Cell *cell = module->addCell(NEW_ID, chain.back()->type); + Cell *cell = module->addCell(NEWER_ID, chain.back()->type); cell->setPort(\C, chain.back()->getPort(\C)); - cell->setPort(\D, module->addWire(NEW_ID)); + cell->setPort(\D, module->addWire(NEWER_ID)); cell->setPort(\Q, chain.back()->getPort(\D)); if (cell->type == \FDRE) { if (rng(2) == 0) @@ -191,7 +191,7 @@ match shiftx filter param(shiftx, \A_WIDTH).as_int() >= minlen generate minlen = 3; - module->addShiftx(NEW_ID, module->addWire(NEW_ID, rng(6)+minlen), module->addWire(NEW_ID, 3), module->addWire(NEW_ID)); + module->addShiftx(NEWER_ID, module->addWire(NEWER_ID, rng(6)+minlen), module->addWire(NEWER_ID, 3), module->addWire(NEWER_ID)); endmatch code shiftx_width @@ -207,28 +207,28 @@ match first index port(first, \Q)[idx] === port(shiftx, \A)[shiftx_width-1] set slice idx generate - SigSpec C = module->addWire(NEW_ID); + SigSpec C = module->addWire(NEWER_ID); auto WIDTH = rng(3)+1; - SigSpec D = module->addWire(NEW_ID, WIDTH); - SigSpec Q = module->addWire(NEW_ID, WIDTH); + SigSpec D = module->addWire(NEWER_ID, WIDTH); + SigSpec Q = module->addWire(NEWER_ID, WIDTH); auto r = rng(8); Cell *cell = nullptr; switch (r) { case 0: case 1: - cell = module->addDff(NEW_ID, C, D, Q, r & 1); + cell = module->addDff(NEWER_ID, C, D, Q, r & 1); break; case 2: case 3: case 4: case 5: - //cell = module->addDffe(NEW_ID, C, module->addWire(NEW_ID), D, Q, r & 1, r & 4); + //cell = module->addDffe(NEWER_ID, C, module->addWire(NEWER_ID), D, Q, r & 1, r & 4); //break; case 6: case 7: WIDTH = 1; - cell = module->addDffGate(NEW_ID, C, D[0], Q[0], r & 1); + cell = module->addDffGate(NEWER_ID, C, D[0], Q[0], r & 1); break; default: log_abort(); } @@ -295,19 +295,19 @@ generate back->connections_.at(\D)[slice] = port(back, \Q)[new_slice]; } else { - auto D = module->addWire(NEW_ID, WIDTH); + auto D = module->addWire(NEWER_ID, WIDTH); if (back->type == $dff) - module->addDff(NEW_ID, port(back, \CLK), D, port(back, \D), param(back, \CLK_POLARITY).as_bool()); + module->addDff(NEWER_ID, port(back, \CLK), D, port(back, \D), param(back, \CLK_POLARITY).as_bool()); else if (back->type == $dffe) - module->addDffe(NEW_ID, port(back, \CLK), port(back, \EN), D, port(back, \D), param(back, \CLK_POLARITY).as_bool(), param(back, \EN_POLARITY).as_bool()); + module->addDffe(NEWER_ID, port(back, \CLK), port(back, \EN), D, port(back, \D), param(back, \CLK_POLARITY).as_bool(), param(back, \EN_POLARITY).as_bool()); else log_abort(); } } else if (back->type.begins_with("$_DFF_")) { - Cell *cell = module->addCell(NEW_ID, back->type); + Cell *cell = module->addCell(NEWER_ID, back->type); cell->setPort(\C, back->getPort(\C)); - cell->setPort(\D, module->addWire(NEW_ID)); + cell->setPort(\D, module->addWire(NEWER_ID)); cell->setPort(\Q, back->getPort(\D)); } else From ffe87fbb343d0925a65a12fde2be88a633306816 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 16 Sep 2025 17:50:07 +0200 Subject: [PATCH 17/18] rtlil: fix roundtrip test with --no-private-id-locs --- tests/rtlil/roundtrip-text.sh | 2 +- tests/rtlil/roundtrip-text.synth.ref.il | 1435 ++++++++++++----------- 2 files changed, 719 insertions(+), 718 deletions(-) mode change 100644 => 100755 tests/rtlil/roundtrip-text.sh diff --git a/tests/rtlil/roundtrip-text.sh b/tests/rtlil/roundtrip-text.sh old mode 100644 new mode 100755 index 7a979879c28..93a7f5fc0a4 --- a/tests/rtlil/roundtrip-text.sh +++ b/tests/rtlil/roundtrip-text.sh @@ -33,7 +33,7 @@ diff temp/roundtrip-text.dump.il temp/roundtrip-text.reload-hash-nogen.il echo "Without ABC, we don't get any irreproducibility and can pin that" echo "Has this test case started failing for you? Consider updating the reference" -$YS -p "read_verilog -sv everything.v; synth -relativeshare -noabc; write_rtlil temp/roundtrip-text.synth.il" +$YS --no-private-id-locs -p "read_verilog -sv everything.v; synth -relativeshare -noabc; write_rtlil temp/roundtrip-text.synth.il" remove_empty_lines temp/roundtrip-text.synth.il tail -n +2 temp/roundtrip-text.synth.il > temp/roundtrip-text.synth-nogen.il diff temp/roundtrip-text.synth-nogen.il roundtrip-text.synth.ref.il diff --git a/tests/rtlil/roundtrip-text.synth.ref.il b/tests/rtlil/roundtrip-text.synth.ref.il index ab48affc6d1..968b1887d6a 100644 --- a/tests/rtlil/roundtrip-text.synth.ref.il +++ b/tests/rtlil/roundtrip-text.synth.ref.il @@ -10,282 +10,282 @@ module \foo attribute \src "everything.v:35.17-35.18" wire width 8 input 1 \a attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$150_Y + wire $techmap$auto$?:0:?$21.lcu.$or$+/techmap.v:240$150_Y attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$147_Y + wire $techmap$auto$?:0:?$21.lcu.$or$+/techmap.v:240$147_Y attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$173_Y + wire $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:248$173_Y attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$170_Y + wire $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:248$170_Y attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$167_Y + wire $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:248$167_Y attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$164_Y + wire $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:248$164_Y attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$151_Y + wire $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:241$151_Y attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$148_Y + wire $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:241$148_Y attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$155_Y + wire $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:240$155_Y attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$149_Y + wire $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:240$149_Y attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$146_Y + wire $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:240$146_Y attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$143_Y + wire $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:240$143_Y attribute \unused_bits "7" attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:214.23-214.24" attribute \force_downto 1 - wire width 8 $auto$alumacc.cc:495:replace_alu$21.lcu.G + wire width 8 $auto$?:0:?$21.lcu.G attribute \src "everything.v:39.16-39.22|+/techmap.v:270.23-270.24" attribute \force_downto 1 - wire width 8 $auto$alumacc.cc:495:replace_alu$21.X + wire width 8 $auto$?:0:?$21.X attribute \unused_bits "7" attribute \src "everything.v:39.16-39.22|+/techmap.v:274.23-274.25" attribute \force_downto 1 - wire width 8 $auto$alumacc.cc:495:replace_alu$21.CO + wire width 8 $auto$?:0:?$21.CO attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$219 - connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [6] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$173_Y - connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [6] + cell $_OR_ $auto$?:0:?$219 + connect \Y $auto$?:0:?$21.CO [6] + connect \B $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:248$173_Y + connect \A $auto$?:0:?$21.lcu.G [6] end attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$218 - connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [4] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$170_Y - connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [4] + cell $_OR_ $auto$?:0:?$218 + connect \Y $auto$?:0:?$21.CO [4] + connect \B $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:248$170_Y + connect \A $auto$?:0:?$21.lcu.G [4] end attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$217 - connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [2] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$167_Y - connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [2] + cell $_OR_ $auto$?:0:?$217 + connect \Y $auto$?:0:?$21.CO [2] + connect \B $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:248$167_Y + connect \A $auto$?:0:?$21.lcu.G [2] end attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$216 - connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [5] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$164_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$150_Y + cell $_OR_ $auto$?:0:?$216 + connect \Y $auto$?:0:?$21.CO [5] + connect \B $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:248$164_Y + connect \A $techmap$auto$?:0:?$21.lcu.$or$+/techmap.v:240$150_Y end attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$213 - connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [3] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$155_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$147_Y + cell $_OR_ $auto$?:0:?$213 + connect \Y $auto$?:0:?$21.CO [3] + connect \B $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:240$155_Y + connect \A $techmap$auto$?:0:?$21.lcu.$or$+/techmap.v:240$147_Y end attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$211 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$150_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$149_Y - connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [5] + cell $_OR_ $auto$?:0:?$211 + connect \Y $techmap$auto$?:0:?$21.lcu.$or$+/techmap.v:240$150_Y + connect \B $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:240$149_Y + connect \A $auto$?:0:?$21.lcu.G [5] end attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$210 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$147_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$146_Y - connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [3] + cell $_OR_ $auto$?:0:?$210 + connect \Y $techmap$auto$?:0:?$21.lcu.$or$+/techmap.v:240$147_Y + connect \B $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:240$146_Y + connect \A $auto$?:0:?$21.lcu.G [3] end attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$209 - connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [1] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$143_Y - connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [1] + cell $_OR_ $auto$?:0:?$209 + connect \Y $auto$?:0:?$21.CO [1] + connect \B $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:240$143_Y + connect \A $auto$?:0:?$21.lcu.G [1] end attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$207 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$173_Y - connect \B $auto$alumacc.cc:495:replace_alu$21.CO [5] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [6] + cell $_AND_ $auto$?:0:?$207 + connect \Y $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:248$173_Y + connect \B $auto$?:0:?$21.CO [5] + connect \A $auto$?:0:?$21.X [6] end attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$206 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$170_Y - connect \B $auto$alumacc.cc:495:replace_alu$21.CO [3] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [4] + cell $_AND_ $auto$?:0:?$206 + connect \Y $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:248$170_Y + connect \B $auto$?:0:?$21.CO [3] + connect \A $auto$?:0:?$21.X [4] end attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$205 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$167_Y - connect \B $auto$alumacc.cc:495:replace_alu$21.CO [1] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [2] + cell $_AND_ $auto$?:0:?$205 + connect \Y $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:248$167_Y + connect \B $auto$?:0:?$21.CO [1] + connect \A $auto$?:0:?$21.X [2] end attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$204 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$164_Y - connect \B $auto$alumacc.cc:495:replace_alu$21.CO [3] - connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$151_Y + cell $_AND_ $auto$?:0:?$204 + connect \Y $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:248$164_Y + connect \B $auto$?:0:?$21.CO [3] + connect \A $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:241$151_Y end attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$201 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$151_Y - connect \B $auto$alumacc.cc:495:replace_alu$21.X [4] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [5] + cell $_AND_ $auto$?:0:?$201 + connect \Y $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:241$151_Y + connect \B $auto$?:0:?$21.X [4] + connect \A $auto$?:0:?$21.X [5] end attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$200 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$148_Y - connect \B $auto$alumacc.cc:495:replace_alu$21.X [2] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [3] + cell $_AND_ $auto$?:0:?$200 + connect \Y $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:241$148_Y + connect \B $auto$?:0:?$21.X [2] + connect \A $auto$?:0:?$21.X [3] end attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$197 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$155_Y - connect \B $auto$alumacc.cc:495:replace_alu$21.CO [1] - connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$148_Y + cell $_AND_ $auto$?:0:?$197 + connect \Y $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:240$155_Y + connect \B $auto$?:0:?$21.CO [1] + connect \A $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:241$148_Y end attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$195 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$149_Y - connect \B $auto$alumacc.cc:495:replace_alu$21.lcu.G [4] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [5] + cell $_AND_ $auto$?:0:?$195 + connect \Y $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:240$149_Y + connect \B $auto$?:0:?$21.lcu.G [4] + connect \A $auto$?:0:?$21.X [5] end attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$194 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$146_Y - connect \B $auto$alumacc.cc:495:replace_alu$21.lcu.G [2] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [3] + cell $_AND_ $auto$?:0:?$194 + connect \Y $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:240$146_Y + connect \B $auto$?:0:?$21.lcu.G [2] + connect \A $auto$?:0:?$21.X [3] end attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$193 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$143_Y - connect \B $auto$alumacc.cc:495:replace_alu$21.CO [0] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [1] + cell $_AND_ $auto$?:0:?$193 + connect \Y $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:240$143_Y + connect \B $auto$?:0:?$21.CO [0] + connect \A $auto$?:0:?$21.X [1] end attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$138 - connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [6] + cell $_AND_ $auto$?:0:?$138 + connect \Y $auto$?:0:?$21.lcu.G [6] connect \B \b [6] connect \A \a [6] end attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$137 - connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [5] + cell $_AND_ $auto$?:0:?$137 + connect \Y $auto$?:0:?$21.lcu.G [5] connect \B \b [5] connect \A \a [5] end attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$136 - connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [4] + cell $_AND_ $auto$?:0:?$136 + connect \Y $auto$?:0:?$21.lcu.G [4] connect \B \b [4] connect \A \a [4] end attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$135 - connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [3] + cell $_AND_ $auto$?:0:?$135 + connect \Y $auto$?:0:?$21.lcu.G [3] connect \B \b [3] connect \A \a [3] end attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$134 - connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [2] + cell $_AND_ $auto$?:0:?$134 + connect \Y $auto$?:0:?$21.lcu.G [2] connect \B \b [2] connect \A \a [2] end attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$133 - connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [1] + cell $_AND_ $auto$?:0:?$133 + connect \Y $auto$?:0:?$21.lcu.G [1] connect \B \b [1] connect \A \a [1] end attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$132 - connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [0] + cell $_AND_ $auto$?:0:?$132 + connect \Y $auto$?:0:?$21.CO [0] connect \B \b [0] connect \A \a [0] end attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$131 - connect \Y $auto$alumacc.cc:495:replace_alu$21.X [7] + cell $_XOR_ $auto$?:0:?$131 + connect \Y $auto$?:0:?$21.X [7] connect \B \b [7] connect \A \a [7] end attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$130 - connect \Y $auto$alumacc.cc:495:replace_alu$21.X [6] + cell $_XOR_ $auto$?:0:?$130 + connect \Y $auto$?:0:?$21.X [6] connect \B \b [6] connect \A \a [6] end attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$129 - connect \Y $auto$alumacc.cc:495:replace_alu$21.X [5] + cell $_XOR_ $auto$?:0:?$129 + connect \Y $auto$?:0:?$21.X [5] connect \B \b [5] connect \A \a [5] end attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$128 - connect \Y $auto$alumacc.cc:495:replace_alu$21.X [4] + cell $_XOR_ $auto$?:0:?$128 + connect \Y $auto$?:0:?$21.X [4] connect \B \b [4] connect \A \a [4] end attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$127 - connect \Y $auto$alumacc.cc:495:replace_alu$21.X [3] + cell $_XOR_ $auto$?:0:?$127 + connect \Y $auto$?:0:?$21.X [3] connect \B \b [3] connect \A \a [3] end attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$126 - connect \Y $auto$alumacc.cc:495:replace_alu$21.X [2] + cell $_XOR_ $auto$?:0:?$126 + connect \Y $auto$?:0:?$21.X [2] connect \B \b [2] connect \A \a [2] end attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$125 - connect \Y $auto$alumacc.cc:495:replace_alu$21.X [1] + cell $_XOR_ $auto$?:0:?$125 + connect \Y $auto$?:0:?$21.X [1] connect \B \b [1] connect \A \a [1] end attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$124 + cell $_XOR_ $auto$?:0:?$124 connect \Y \y [0] connect \B \b [0] connect \A \a [0] end attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$122 + cell $_XOR_ $auto$?:0:?$122 connect \Y \y [7] - connect \B $auto$alumacc.cc:495:replace_alu$21.CO [6] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [7] + connect \B $auto$?:0:?$21.CO [6] + connect \A $auto$?:0:?$21.X [7] end attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$121 + cell $_XOR_ $auto$?:0:?$121 connect \Y \y [6] - connect \B $auto$alumacc.cc:495:replace_alu$21.CO [5] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [6] + connect \B $auto$?:0:?$21.CO [5] + connect \A $auto$?:0:?$21.X [6] end attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$120 + cell $_XOR_ $auto$?:0:?$120 connect \Y \y [5] - connect \B $auto$alumacc.cc:495:replace_alu$21.CO [4] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [5] + connect \B $auto$?:0:?$21.CO [4] + connect \A $auto$?:0:?$21.X [5] end attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$119 + cell $_XOR_ $auto$?:0:?$119 connect \Y \y [4] - connect \B $auto$alumacc.cc:495:replace_alu$21.CO [3] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [4] + connect \B $auto$?:0:?$21.CO [3] + connect \A $auto$?:0:?$21.X [4] end attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$118 + cell $_XOR_ $auto$?:0:?$118 connect \Y \y [3] - connect \B $auto$alumacc.cc:495:replace_alu$21.CO [2] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [3] + connect \B $auto$?:0:?$21.CO [2] + connect \A $auto$?:0:?$21.X [3] end attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$117 + cell $_XOR_ $auto$?:0:?$117 connect \Y \y [2] - connect \B $auto$alumacc.cc:495:replace_alu$21.CO [1] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [2] + connect \B $auto$?:0:?$21.CO [1] + connect \A $auto$?:0:?$21.X [2] end attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$116 + cell $_XOR_ $auto$?:0:?$116 connect \Y \y [1] - connect \B $auto$alumacc.cc:495:replace_alu$21.CO [0] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [1] + connect \B $auto$?:0:?$21.CO [0] + connect \A $auto$?:0:?$21.X [1] end - connect $auto$alumacc.cc:495:replace_alu$21.X [0] \y [0] - connect $auto$alumacc.cc:495:replace_alu$21.lcu.G [0] $auto$alumacc.cc:495:replace_alu$21.CO [0] + connect $auto$?:0:?$21.X [0] \y [0] + connect $auto$?:0:?$21.lcu.G [0] $auto$?:0:?$21.CO [0] connect \bb \b end attribute \src "everything.v:1.1-32.10" @@ -309,90 +309,90 @@ module \alu attribute \src "everything.v:3.14-3.15" wire width 8 input 2 \A attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$348_Y + wire $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$238.lcu.$and$+/techmap.v:241$348_Y attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$342_Y + wire $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$238.lcu.$and$+/techmap.v:241$342_Y attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$339_Y + wire $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$238.lcu.$and$+/techmap.v:241$339_Y attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$336_Y + wire $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$238.lcu.$and$+/techmap.v:241$336_Y attribute \src "+/techmap.v:270.26-270.27" attribute \force_downto 1 - wire width 9 $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y + wire width 9 $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y attribute \src "+/techmap.v:274.23-274.25" attribute \force_downto 1 - wire width 9 $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO + wire width 9 $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO attribute \src "+/techmap.v:279.21-279.23" attribute \force_downto 1 - wire width 9 $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB + wire width 9 $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$347_Y + wire $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$347_Y attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$341_Y + wire $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$341_Y attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$338_Y + wire $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$338_Y attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$335_Y + wire $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$335_Y attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$361_Y + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$361_Y attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$358_Y + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$358_Y attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$355_Y + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$355_Y attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$352_Y + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$352_Y attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$348_Y + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$348_Y attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$342_Y + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$342_Y attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$339_Y + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$339_Y attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$336_Y + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$336_Y attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$349_Y + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$349_Y attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$346_Y + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$346_Y attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$343_Y + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$343_Y attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$340_Y + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$340_Y attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$337_Y + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$337_Y attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$334_Y + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$334_Y attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$331_Y + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$331_Y wire $procmux$9_CMP wire $procmux$8_CMP - wire $auto$simplemap.cc:254:simplemap_eqne$247 - wire $auto$simplemap.cc:166:logic_reduce$268 - wire width 2 $auto$simplemap.cc:166:logic_reduce$265 - wire $auto$simplemap.cc:166:logic_reduce$235 - wire width 2 $auto$simplemap.cc:166:logic_reduce$232 - wire width 4 $auto$simplemap.cc:166:logic_reduce$227 - wire width 2 $auto$simplemap.cc:125:simplemap_reduce$249 - wire $auto$rtlil.cc:3196:NotGate$497 - wire $auto$opt_dff.cc:247:make_patterns_logic$505 + wire $auto$?:0:?$32 + wire $auto$?:0:?$268 + wire width 2 $auto$?:0:?$265 + wire width 2 $auto$?:0:?$249 + wire $auto$?:0:?$247 + wire width 4 $auto$?:0:?$241 + wire $auto$?:0:?$235 + wire width 2 $auto$?:0:?$232 + wire width 4 $auto$?:0:?$227 attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:214.23-214.24" attribute \force_downto 1 - wire width 9 $auto$alumacc.cc:495:replace_alu$18.lcu.G + wire width 9 $auto$?:0:?$18.lcu.G attribute \src "everything.v:23.11-23.16|+/techmap.v:270.26-270.27" attribute \force_downto 1 - wire width 9 $auto$alumacc.cc:495:replace_alu$18.Y + wire width 9 $auto$?:0:?$18.Y attribute \src "everything.v:23.11-23.16|+/techmap.v:270.23-270.24" attribute \force_downto 1 - wire width 9 $auto$alumacc.cc:495:replace_alu$18.X + wire width 9 $auto$?:0:?$18.X attribute \unused_bits "8" attribute \src "everything.v:23.11-23.16|+/techmap.v:274.23-274.25" attribute \force_downto 1 - wire width 9 $auto$alumacc.cc:495:replace_alu$18.CO + wire width 9 $auto$?:0:?$18.CO attribute \src "everything.v:23.11-23.16|+/techmap.v:279.21-279.23" attribute \force_downto 1 - wire width 9 $auto$alumacc.cc:495:replace_alu$18.BB + wire width 9 $auto$?:0:?$18.BB attribute \src "everything.v:23.11-23.16|+/techmap.v:268.22-268.23" attribute \force_downto 1 - wire width 9 $auto$alumacc.cc:495:replace_alu$18.B + wire width 9 $auto$?:0:?$18.B attribute \src "everything.v:17.2-31.5" wire width 8 $0\result[7:0] attribute \src "everything.v:17.2-31.5" @@ -401,793 +401,794 @@ module \alu wire $0\SF[0:0] attribute \src "everything.v:17.2-31.5" wire $0\CF[0:0] + attribute \src "everything.v:17.2-31.5" + cell $_DFFE_PP_ $auto$?:0:?$504 + connect \Q \CF + connect \E $auto$?:0:?$32 + connect \D $0\CF[0:0] + connect \C \clk + end + cell $_NOT_ $auto$?:0:?$502 + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [8] + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [8] + end + cell $_NOT_ $auto$?:0:?$500 + connect \Y $auto$?:0:?$18.Y [0] + connect \A $auto$?:0:?$18.X [0] + end + cell $_NOT_ $auto$?:0:?$496 + connect \Y $auto$?:0:?$241 [0] + connect \A \operation [0] + end attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$481 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [6] - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [5] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] + cell $_AND_ $auto$?:0:?$481 + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [6] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [5] + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [6] end attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$480 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [4] - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] + cell $_AND_ $auto$?:0:?$480 + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [4] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [3] + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [4] end attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$479 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [2] - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] + cell $_AND_ $auto$?:0:?$479 + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [2] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [1] + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [2] end attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$478 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [5] - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] - connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$339_Y + cell $_AND_ $auto$?:0:?$478 + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [5] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [3] + connect \A $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$238.lcu.$and$+/techmap.v:241$339_Y end attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$477 - connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$348_Y - connect \B $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$339_Y - connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$342_Y + cell $_AND_ $auto$?:0:?$477 + connect \Y $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$238.lcu.$and$+/techmap.v:241$348_Y + connect \B $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$238.lcu.$and$+/techmap.v:241$339_Y + connect \A $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$238.lcu.$and$+/techmap.v:241$342_Y end attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$476 - connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$342_Y - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [7] + cell $_AND_ $auto$?:0:?$476 + connect \Y $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$238.lcu.$and$+/techmap.v:241$342_Y + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [6] + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [7] end attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$475 - connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$339_Y - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [5] + cell $_AND_ $auto$?:0:?$475 + connect \Y $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$238.lcu.$and$+/techmap.v:241$339_Y + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [4] + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [5] end attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$474 - connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$336_Y - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [3] + cell $_AND_ $auto$?:0:?$474 + connect \Y $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$238.lcu.$and$+/techmap.v:241$336_Y + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [2] + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [3] end attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$473 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [8] - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] - connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$348_Y + cell $_AND_ $auto$?:0:?$473 + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [8] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [3] + connect \A $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$238.lcu.$and$+/techmap.v:241$348_Y end attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$471 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] - connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$336_Y + cell $_AND_ $auto$?:0:?$471 + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [3] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [1] + connect \A $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$238.lcu.$and$+/techmap.v:241$336_Y end attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$467 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [1] + cell $_AND_ $auto$?:0:?$467 + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [1] + connect \B $auto$?:0:?$18.BB [0] + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [1] + end + attribute \src "+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$464 + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [7] + connect \A \B [7] + end + attribute \src "+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$463 + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [6] + connect \A \B [6] + end + attribute \src "+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$462 + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [5] + connect \A \B [5] + end + attribute \src "+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$461 + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [4] + connect \A \B [4] + end + attribute \src "+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$460 + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [3] + connect \A \B [3] + end + attribute \src "+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$459 + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [2] + connect \A \B [2] + end + attribute \src "+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$458 + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [1] + connect \A \B [1] end attribute \src "+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$427 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [7] - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [6] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [7] + cell $_XOR_ $auto$?:0:?$427 + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [7] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [6] + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [7] end attribute \src "+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$426 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [6] - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [5] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] + cell $_XOR_ $auto$?:0:?$426 + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [6] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [5] + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [6] end attribute \src "+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$425 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [5] - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [4] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [5] + cell $_XOR_ $auto$?:0:?$425 + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [5] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [4] + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [5] end attribute \src "+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$424 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [4] - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] + cell $_XOR_ $auto$?:0:?$424 + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [4] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [3] + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [4] end attribute \src "+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$423 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [3] - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [2] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [3] + cell $_XOR_ $auto$?:0:?$423 + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [3] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [2] + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [3] end attribute \src "+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$422 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [2] - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] + cell $_XOR_ $auto$?:0:?$422 + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [2] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [1] + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [2] end attribute \src "+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$421 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [1] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [1] + cell $_XOR_ $auto$?:0:?$421 + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [1] + connect \B $auto$?:0:?$18.BB [0] + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [1] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$418 - connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [6] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$361_Y - connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [6] + cell $_OR_ $auto$?:0:?$418 + connect \Y $auto$?:0:?$18.CO [6] + connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$361_Y + connect \A $auto$?:0:?$18.lcu.G [6] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$417 - connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [4] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$358_Y - connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [4] + cell $_OR_ $auto$?:0:?$417 + connect \Y $auto$?:0:?$18.CO [4] + connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$358_Y + connect \A $auto$?:0:?$18.lcu.G [4] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$416 - connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [2] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$355_Y - connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [2] + cell $_OR_ $auto$?:0:?$416 + connect \Y $auto$?:0:?$18.CO [2] + connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$355_Y + connect \A $auto$?:0:?$18.lcu.G [2] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$415 - connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [5] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$352_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$338_Y + cell $_OR_ $auto$?:0:?$415 + connect \Y $auto$?:0:?$18.CO [5] + connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$352_Y + connect \A $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$338_Y end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$414 - connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [7] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$349_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$347_Y + cell $_OR_ $auto$?:0:?$414 + connect \Y $auto$?:0:?$18.CO [7] + connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$349_Y + connect \A $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$347_Y end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$413 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$347_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$346_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$341_Y + cell $_OR_ $auto$?:0:?$413 + connect \Y $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$347_Y + connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$346_Y + connect \A $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$341_Y end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$412 - connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [3] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$343_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$335_Y + cell $_OR_ $auto$?:0:?$412 + connect \Y $auto$?:0:?$18.CO [3] + connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$343_Y + connect \A $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$335_Y end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$411 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$341_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$340_Y - connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [7] + cell $_OR_ $auto$?:0:?$411 + connect \Y $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$341_Y + connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$340_Y + connect \A $auto$?:0:?$18.lcu.G [7] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$410 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$338_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$337_Y - connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [5] + cell $_OR_ $auto$?:0:?$410 + connect \Y $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$338_Y + connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$337_Y + connect \A $auto$?:0:?$18.lcu.G [5] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$409 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$335_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$334_Y - connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [3] + cell $_OR_ $auto$?:0:?$409 + connect \Y $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$335_Y + connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$334_Y + connect \A $auto$?:0:?$18.lcu.G [3] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$408 - connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [1] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$331_Y - connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [1] + cell $_OR_ $auto$?:0:?$408 + connect \Y $auto$?:0:?$18.CO [1] + connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$331_Y + connect \A $auto$?:0:?$18.lcu.G [1] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:231.10-231.28" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$407 - connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [0] - connect \B $auto$alumacc.cc:495:replace_alu$18.X [0] - connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [0] + cell $_OR_ $auto$?:0:?$407 + connect \Y $auto$?:0:?$18.CO [0] + connect \B $auto$?:0:?$18.X [0] + connect \A $auto$?:0:?$18.lcu.G [0] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$405 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$361_Y - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [5] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [6] + cell $_AND_ $auto$?:0:?$405 + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$361_Y + connect \B $auto$?:0:?$18.CO [5] + connect \A $auto$?:0:?$18.X [6] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$404 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$358_Y - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [4] + cell $_AND_ $auto$?:0:?$404 + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$358_Y + connect \B $auto$?:0:?$18.CO [3] + connect \A $auto$?:0:?$18.X [4] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$403 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$355_Y - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [1] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [2] + cell $_AND_ $auto$?:0:?$403 + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$355_Y + connect \B $auto$?:0:?$18.CO [1] + connect \A $auto$?:0:?$18.X [2] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$402 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$352_Y - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$339_Y + cell $_AND_ $auto$?:0:?$402 + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$352_Y + connect \B $auto$?:0:?$18.CO [3] + connect \A $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$339_Y end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$401 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$348_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$339_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$342_Y + cell $_AND_ $auto$?:0:?$401 + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$348_Y + connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$339_Y + connect \A $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$342_Y end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$400 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$342_Y - connect \B $auto$alumacc.cc:495:replace_alu$18.X [6] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [7] + cell $_AND_ $auto$?:0:?$400 + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$342_Y + connect \B $auto$?:0:?$18.X [6] + connect \A $auto$?:0:?$18.X [7] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$399 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$339_Y - connect \B $auto$alumacc.cc:495:replace_alu$18.X [4] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [5] + cell $_AND_ $auto$?:0:?$399 + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$339_Y + connect \B $auto$?:0:?$18.X [4] + connect \A $auto$?:0:?$18.X [5] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$398 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$336_Y - connect \B $auto$alumacc.cc:495:replace_alu$18.X [2] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [3] + cell $_AND_ $auto$?:0:?$398 + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$336_Y + connect \B $auto$?:0:?$18.X [2] + connect \A $auto$?:0:?$18.X [3] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$397 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$349_Y - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$348_Y + cell $_AND_ $auto$?:0:?$397 + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$349_Y + connect \B $auto$?:0:?$18.CO [3] + connect \A $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$348_Y end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$396 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$346_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$338_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$342_Y + cell $_AND_ $auto$?:0:?$396 + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$346_Y + connect \B $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$338_Y + connect \A $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$342_Y end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$395 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$343_Y - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [1] - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$336_Y + cell $_AND_ $auto$?:0:?$395 + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$343_Y + connect \B $auto$?:0:?$18.CO [1] + connect \A $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$336_Y end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$394 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$340_Y - connect \B $auto$alumacc.cc:495:replace_alu$18.lcu.G [6] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [7] + cell $_AND_ $auto$?:0:?$394 + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$340_Y + connect \B $auto$?:0:?$18.lcu.G [6] + connect \A $auto$?:0:?$18.X [7] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$393 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$337_Y - connect \B $auto$alumacc.cc:495:replace_alu$18.lcu.G [4] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [5] + cell $_AND_ $auto$?:0:?$393 + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$337_Y + connect \B $auto$?:0:?$18.lcu.G [4] + connect \A $auto$?:0:?$18.X [5] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$392 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$334_Y - connect \B $auto$alumacc.cc:495:replace_alu$18.lcu.G [2] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [3] + cell $_AND_ $auto$?:0:?$392 + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$334_Y + connect \B $auto$?:0:?$18.lcu.G [2] + connect \A $auto$?:0:?$18.X [3] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$391 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$331_Y - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [0] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [1] + cell $_AND_ $auto$?:0:?$391 + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$331_Y + connect \B $auto$?:0:?$18.CO [0] + connect \A $auto$?:0:?$18.X [1] + end + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$384 + connect \Y $auto$?:0:?$18.BB [8] + connect \A $auto$?:0:?$18.B [8] + end + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$383 + connect \Y $auto$?:0:?$18.BB [7] + connect \A $auto$?:0:?$18.B [7] + end + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$382 + connect \Y $auto$?:0:?$18.BB [6] + connect \A $auto$?:0:?$18.B [6] + end + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$381 + connect \Y $auto$?:0:?$18.BB [5] + connect \A $auto$?:0:?$18.B [5] + end + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$380 + connect \Y $auto$?:0:?$18.BB [4] + connect \A $auto$?:0:?$18.B [4] + end + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$379 + connect \Y $auto$?:0:?$18.BB [3] + connect \A $auto$?:0:?$18.B [3] + end + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$378 + connect \Y $auto$?:0:?$18.BB [2] + connect \A $auto$?:0:?$18.B [2] + end + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$377 + connect \Y $auto$?:0:?$18.BB [1] + connect \A $auto$?:0:?$18.B [1] + end + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$376 + connect \Y $auto$?:0:?$18.BB [0] + connect \A \B [0] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$326 - connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [7] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [7] + cell $_AND_ $auto$?:0:?$326 + connect \Y $auto$?:0:?$18.lcu.G [7] + connect \B $auto$?:0:?$18.BB [7] connect \A \A [7] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$325 - connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [6] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [6] + cell $_AND_ $auto$?:0:?$325 + connect \Y $auto$?:0:?$18.lcu.G [6] + connect \B $auto$?:0:?$18.BB [6] connect \A \A [6] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$324 - connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [5] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [5] + cell $_AND_ $auto$?:0:?$324 + connect \Y $auto$?:0:?$18.lcu.G [5] + connect \B $auto$?:0:?$18.BB [5] connect \A \A [5] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$323 - connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [4] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [4] + cell $_AND_ $auto$?:0:?$323 + connect \Y $auto$?:0:?$18.lcu.G [4] + connect \B $auto$?:0:?$18.BB [4] connect \A \A [4] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$322 - connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [3] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [3] + cell $_AND_ $auto$?:0:?$322 + connect \Y $auto$?:0:?$18.lcu.G [3] + connect \B $auto$?:0:?$18.BB [3] connect \A \A [3] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$321 - connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [2] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [2] + cell $_AND_ $auto$?:0:?$321 + connect \Y $auto$?:0:?$18.lcu.G [2] + connect \B $auto$?:0:?$18.BB [2] connect \A \A [2] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$320 - connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [1] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [1] + cell $_AND_ $auto$?:0:?$320 + connect \Y $auto$?:0:?$18.lcu.G [1] + connect \B $auto$?:0:?$18.BB [1] connect \A \A [1] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$319 - connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [0] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] + cell $_AND_ $auto$?:0:?$319 + connect \Y $auto$?:0:?$18.lcu.G [0] + connect \B $auto$?:0:?$18.BB [0] connect \A \A [0] end attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$317 - connect \Y $auto$alumacc.cc:495:replace_alu$18.X [7] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [7] + cell $_XOR_ $auto$?:0:?$317 + connect \Y $auto$?:0:?$18.X [7] + connect \B $auto$?:0:?$18.BB [7] connect \A \A [7] end attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$316 - connect \Y $auto$alumacc.cc:495:replace_alu$18.X [6] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [6] + cell $_XOR_ $auto$?:0:?$316 + connect \Y $auto$?:0:?$18.X [6] + connect \B $auto$?:0:?$18.BB [6] connect \A \A [6] end attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$315 - connect \Y $auto$alumacc.cc:495:replace_alu$18.X [5] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [5] + cell $_XOR_ $auto$?:0:?$315 + connect \Y $auto$?:0:?$18.X [5] + connect \B $auto$?:0:?$18.BB [5] connect \A \A [5] end attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$314 - connect \Y $auto$alumacc.cc:495:replace_alu$18.X [4] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [4] + cell $_XOR_ $auto$?:0:?$314 + connect \Y $auto$?:0:?$18.X [4] + connect \B $auto$?:0:?$18.BB [4] connect \A \A [4] end attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$313 - connect \Y $auto$alumacc.cc:495:replace_alu$18.X [3] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [3] + cell $_XOR_ $auto$?:0:?$313 + connect \Y $auto$?:0:?$18.X [3] + connect \B $auto$?:0:?$18.BB [3] connect \A \A [3] end attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$312 - connect \Y $auto$alumacc.cc:495:replace_alu$18.X [2] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [2] + cell $_XOR_ $auto$?:0:?$312 + connect \Y $auto$?:0:?$18.X [2] + connect \B $auto$?:0:?$18.BB [2] connect \A \A [2] end attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$311 - connect \Y $auto$alumacc.cc:495:replace_alu$18.X [1] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [1] + cell $_XOR_ $auto$?:0:?$311 + connect \Y $auto$?:0:?$18.X [1] + connect \B $auto$?:0:?$18.BB [1] connect \A \A [1] end attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$310 - connect \Y $auto$alumacc.cc:495:replace_alu$18.X [0] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] + cell $_XOR_ $auto$?:0:?$310 + connect \Y $auto$?:0:?$18.X [0] + connect \B $auto$?:0:?$18.BB [0] connect \A \A [0] end attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$308 - connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [8] - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [7] - connect \A $auto$alumacc.cc:495:replace_alu$18.BB [8] + cell $_XOR_ $auto$?:0:?$308 + connect \Y $auto$?:0:?$18.Y [8] + connect \B $auto$?:0:?$18.CO [7] + connect \A $auto$?:0:?$18.BB [8] end attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$307 - connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [7] - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [6] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [7] + cell $_XOR_ $auto$?:0:?$307 + connect \Y $auto$?:0:?$18.Y [7] + connect \B $auto$?:0:?$18.CO [6] + connect \A $auto$?:0:?$18.X [7] end attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$306 - connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [6] - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [5] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [6] + cell $_XOR_ $auto$?:0:?$306 + connect \Y $auto$?:0:?$18.Y [6] + connect \B $auto$?:0:?$18.CO [5] + connect \A $auto$?:0:?$18.X [6] end attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$305 - connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [5] - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [4] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [5] + cell $_XOR_ $auto$?:0:?$305 + connect \Y $auto$?:0:?$18.Y [5] + connect \B $auto$?:0:?$18.CO [4] + connect \A $auto$?:0:?$18.X [5] end attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$304 - connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [4] - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [4] + cell $_XOR_ $auto$?:0:?$304 + connect \Y $auto$?:0:?$18.Y [4] + connect \B $auto$?:0:?$18.CO [3] + connect \A $auto$?:0:?$18.X [4] end attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$303 - connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [3] - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [2] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [3] + cell $_XOR_ $auto$?:0:?$303 + connect \Y $auto$?:0:?$18.Y [3] + connect \B $auto$?:0:?$18.CO [2] + connect \A $auto$?:0:?$18.X [3] end attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$302 - connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [2] - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [1] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [2] + cell $_XOR_ $auto$?:0:?$302 + connect \Y $auto$?:0:?$18.Y [2] + connect \B $auto$?:0:?$18.CO [1] + connect \A $auto$?:0:?$18.X [2] end attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$301 - connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [1] - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [0] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [1] + cell $_XOR_ $auto$?:0:?$301 + connect \Y $auto$?:0:?$18.Y [1] + connect \B $auto$?:0:?$18.CO [0] + connect \A $auto$?:0:?$18.X [1] end - attribute \src "+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$464 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [7] + attribute \src 0'x + cell $_MUX_ $auto$?:0:?$299 + connect \Y $auto$?:0:?$18.B [8] + connect \S $auto$?:0:?$247 + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [8] + connect \A 1'0 + end + attribute \src 0'x + cell $_MUX_ $auto$?:0:?$298 + connect \Y $auto$?:0:?$18.B [7] + connect \S $auto$?:0:?$247 + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [7] connect \A \B [7] end - attribute \src "+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$463 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] + attribute \src 0'x + cell $_MUX_ $auto$?:0:?$297 + connect \Y $auto$?:0:?$18.B [6] + connect \S $auto$?:0:?$247 + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [6] connect \A \B [6] end - attribute \src "+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$462 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [5] + attribute \src 0'x + cell $_MUX_ $auto$?:0:?$296 + connect \Y $auto$?:0:?$18.B [5] + connect \S $auto$?:0:?$247 + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [5] connect \A \B [5] end - attribute \src "+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$461 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] + attribute \src 0'x + cell $_MUX_ $auto$?:0:?$295 + connect \Y $auto$?:0:?$18.B [4] + connect \S $auto$?:0:?$247 + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [4] connect \A \B [4] end - attribute \src "+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$460 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [3] + attribute \src 0'x + cell $_MUX_ $auto$?:0:?$294 + connect \Y $auto$?:0:?$18.B [3] + connect \S $auto$?:0:?$247 + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [3] connect \A \B [3] end - attribute \src "+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$459 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] + attribute \src 0'x + cell $_MUX_ $auto$?:0:?$293 + connect \Y $auto$?:0:?$18.B [2] + connect \S $auto$?:0:?$247 + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [2] connect \A \B [2] end - attribute \src "+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$458 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [1] + attribute \src 0'x + cell $_MUX_ $auto$?:0:?$292 + connect \Y $auto$?:0:?$18.B [1] + connect \S $auto$?:0:?$247 + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [1] connect \A \B [1] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$384 - connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [8] - connect \A $auto$alumacc.cc:495:replace_alu$18.B [8] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$383 - connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [7] - connect \A $auto$alumacc.cc:495:replace_alu$18.B [7] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$382 - connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [6] - connect \A $auto$alumacc.cc:495:replace_alu$18.B [6] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$381 - connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [5] - connect \A $auto$alumacc.cc:495:replace_alu$18.B [5] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$380 - connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [4] - connect \A $auto$alumacc.cc:495:replace_alu$18.B [4] + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$?:0:?$289 + connect \Q \tmp [7] + connect \D $0\SF[0:0] + connect \C \clk end - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$379 - connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [3] - connect \A $auto$alumacc.cc:495:replace_alu$18.B [3] + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$?:0:?$288 + connect \Q \tmp [6] + connect \D $0\result[7:0] [6] + connect \C \clk end - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$378 - connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [2] - connect \A $auto$alumacc.cc:495:replace_alu$18.B [2] + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$?:0:?$287 + connect \Q \tmp [5] + connect \D $0\result[7:0] [5] + connect \C \clk end - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$377 - connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [1] - connect \A $auto$alumacc.cc:495:replace_alu$18.B [1] + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$?:0:?$286 + connect \Q \tmp [4] + connect \D $0\result[7:0] [4] + connect \C \clk end - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$376 - connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [0] - connect \A \B [0] + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$?:0:?$285 + connect \Q \tmp [3] + connect \D $0\result[7:0] [3] + connect \C \clk end - attribute \src 0'x - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$299 - connect \Y $auto$alumacc.cc:495:replace_alu$18.B [8] - connect \S $auto$simplemap.cc:254:simplemap_eqne$247 - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [8] - connect \A 1'0 + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$?:0:?$284 + connect \Q \tmp [2] + connect \D $0\result[7:0] [2] + connect \C \clk end - attribute \src 0'x - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$298 - connect \Y $auto$alumacc.cc:495:replace_alu$18.B [7] - connect \S $auto$simplemap.cc:254:simplemap_eqne$247 - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [7] - connect \A \B [7] + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$?:0:?$283 + connect \Q \tmp [1] + connect \D $0\result[7:0] [1] + connect \C \clk end - attribute \src 0'x - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$297 - connect \Y $auto$alumacc.cc:495:replace_alu$18.B [6] - connect \S $auto$simplemap.cc:254:simplemap_eqne$247 - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [6] - connect \A \B [6] + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$?:0:?$282 + connect \Q \tmp [0] + connect \D $0\result[7:0] [0] + connect \C \clk end - attribute \src 0'x - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$296 - connect \Y $auto$alumacc.cc:495:replace_alu$18.B [5] - connect \S $auto$simplemap.cc:254:simplemap_eqne$247 - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [5] - connect \A \B [5] + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$?:0:?$280 + connect \Q \ZF + connect \D $0\ZF[0:0] + connect \C \clk end - attribute \src 0'x - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$295 - connect \Y $auto$alumacc.cc:495:replace_alu$18.B [4] - connect \S $auto$simplemap.cc:254:simplemap_eqne$247 - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [4] - connect \A \B [4] + attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" + cell $_NOT_ $auto$?:0:?$270 + connect \Y $procmux$9_CMP + connect \A $auto$?:0:?$268 end - attribute \src 0'x - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$294 - connect \Y $auto$alumacc.cc:495:replace_alu$18.B [3] - connect \S $auto$simplemap.cc:254:simplemap_eqne$247 - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [3] - connect \A \B [3] + attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" + cell $_OR_ $auto$?:0:?$269 + connect \Y $auto$?:0:?$268 + connect \B $auto$?:0:?$249 [1] + connect \A $auto$?:0:?$265 [0] end - attribute \src 0'x - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$293 - connect \Y $auto$alumacc.cc:495:replace_alu$18.B [2] - connect \S $auto$simplemap.cc:254:simplemap_eqne$247 - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [2] - connect \A \B [2] + attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" + cell $_OR_ $auto$?:0:?$267 + connect \Y $auto$?:0:?$249 [1] + connect \B \operation [3] + connect \A \operation [2] end - attribute \src 0'x - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$292 - connect \Y $auto$alumacc.cc:495:replace_alu$18.B [1] - connect \S $auto$simplemap.cc:254:simplemap_eqne$247 - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [1] - connect \A \B [1] + attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" + cell $_OR_ $auto$?:0:?$266 + connect \Y $auto$?:0:?$265 [0] + connect \B \operation [1] + connect \A \operation [0] end attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$264 + cell $_MUX_ $auto$?:0:?$264 connect \Y $0\CF[0:0] - connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 - connect \B $auto$alumacc.cc:495:replace_alu$18.Y [8] + connect \S $auto$?:0:?$32 + connect \B $auto$?:0:?$18.Y [8] connect \A 1'x end attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$263 + cell $_MUX_ $auto$?:0:?$263 connect \Y $0\SF[0:0] - connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 - connect \B $auto$alumacc.cc:495:replace_alu$18.Y [7] + connect \S $auto$?:0:?$32 + connect \B $auto$?:0:?$18.Y [7] connect \A \tmp [7] end attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$262 + cell $_MUX_ $auto$?:0:?$262 connect \Y $0\result[7:0] [6] - connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 - connect \B $auto$alumacc.cc:495:replace_alu$18.Y [6] + connect \S $auto$?:0:?$32 + connect \B $auto$?:0:?$18.Y [6] connect \A \tmp [6] end attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$261 + cell $_MUX_ $auto$?:0:?$261 connect \Y $0\result[7:0] [5] - connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 - connect \B $auto$alumacc.cc:495:replace_alu$18.Y [5] + connect \S $auto$?:0:?$32 + connect \B $auto$?:0:?$18.Y [5] connect \A \tmp [5] end attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$260 + cell $_MUX_ $auto$?:0:?$260 connect \Y $0\result[7:0] [4] - connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 - connect \B $auto$alumacc.cc:495:replace_alu$18.Y [4] + connect \S $auto$?:0:?$32 + connect \B $auto$?:0:?$18.Y [4] connect \A \tmp [4] end attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$259 + cell $_MUX_ $auto$?:0:?$259 connect \Y $0\result[7:0] [3] - connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 - connect \B $auto$alumacc.cc:495:replace_alu$18.Y [3] + connect \S $auto$?:0:?$32 + connect \B $auto$?:0:?$18.Y [3] connect \A \tmp [3] end attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$258 + cell $_MUX_ $auto$?:0:?$258 connect \Y $0\result[7:0] [2] - connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 - connect \B $auto$alumacc.cc:495:replace_alu$18.Y [2] + connect \S $auto$?:0:?$32 + connect \B $auto$?:0:?$18.Y [2] connect \A \tmp [2] end attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$257 + cell $_MUX_ $auto$?:0:?$257 connect \Y $0\result[7:0] [1] - connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 - connect \B $auto$alumacc.cc:495:replace_alu$18.Y [1] + connect \S $auto$?:0:?$32 + connect \B $auto$?:0:?$18.Y [1] connect \A \tmp [1] end attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$256 + cell $_MUX_ $auto$?:0:?$256 connect \Y $0\result[7:0] [0] - connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 - connect \B $auto$alumacc.cc:495:replace_alu$18.Y [0] + connect \S $auto$?:0:?$32 + connect \B $auto$?:0:?$18.Y [0] connect \A \tmp [0] end - attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" - cell $_NOT_ $auto$simplemap.cc:204:simplemap_lognot$270 - connect \Y $procmux$9_CMP - connect \A $auto$simplemap.cc:166:logic_reduce$268 - end attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_NOT_ $auto$simplemap.cc:204:simplemap_lognot$255 + cell $_NOT_ $auto$?:0:?$255 connect \Y $procmux$8_CMP - connect \A $auto$simplemap.cc:254:simplemap_eqne$247 + connect \A $auto$?:0:?$247 end - attribute \src "everything.v:27.9-27.22" - cell $_NOT_ $auto$simplemap.cc:204:simplemap_lognot$237 - connect \Y $0\ZF[0:0] - connect \A $auto$simplemap.cc:166:logic_reduce$235 - end - attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" - cell $_OR_ $auto$simplemap.cc:175:logic_reduce$269 - connect \Y $auto$simplemap.cc:166:logic_reduce$268 - connect \B $auto$simplemap.cc:125:simplemap_reduce$249 [1] - connect \A $auto$simplemap.cc:166:logic_reduce$265 [0] - end - attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" - cell $_OR_ $auto$simplemap.cc:175:logic_reduce$267 - connect \Y $auto$simplemap.cc:125:simplemap_reduce$249 [1] - connect \B \operation [3] - connect \A \operation [2] + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_OR_ $auto$?:0:?$253 + connect \Y $auto$?:0:?$247 + connect \B $auto$?:0:?$249 [1] + connect \A $auto$?:0:?$249 [0] end - attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" - cell $_OR_ $auto$simplemap.cc:175:logic_reduce$266 - connect \Y $auto$simplemap.cc:166:logic_reduce$265 [0] + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_OR_ $auto$?:0:?$250 + connect \Y $auto$?:0:?$249 [0] connect \B \operation [1] - connect \A \operation [0] + connect \A $auto$?:0:?$241 [0] end attribute \src "everything.v:27.9-27.22" - cell $_OR_ $auto$simplemap.cc:175:logic_reduce$236 - connect \Y $auto$simplemap.cc:166:logic_reduce$235 - connect \B $auto$simplemap.cc:166:logic_reduce$232 [1] - connect \A $auto$simplemap.cc:166:logic_reduce$232 [0] + cell $_NOT_ $auto$?:0:?$237 + connect \Y $0\ZF[0:0] + connect \A $auto$?:0:?$235 end attribute \src "everything.v:27.9-27.22" - cell $_OR_ $auto$simplemap.cc:175:logic_reduce$234 - connect \Y $auto$simplemap.cc:166:logic_reduce$232 [1] - connect \B $auto$simplemap.cc:166:logic_reduce$227 [3] - connect \A $auto$simplemap.cc:166:logic_reduce$227 [2] + cell $_OR_ $auto$?:0:?$236 + connect \Y $auto$?:0:?$235 + connect \B $auto$?:0:?$232 [1] + connect \A $auto$?:0:?$232 [0] end attribute \src "everything.v:27.9-27.22" - cell $_OR_ $auto$simplemap.cc:175:logic_reduce$233 - connect \Y $auto$simplemap.cc:166:logic_reduce$232 [0] - connect \B $auto$simplemap.cc:166:logic_reduce$227 [1] - connect \A $auto$simplemap.cc:166:logic_reduce$227 [0] + cell $_OR_ $auto$?:0:?$234 + connect \Y $auto$?:0:?$232 [1] + connect \B $auto$?:0:?$227 [3] + connect \A $auto$?:0:?$227 [2] end attribute \src "everything.v:27.9-27.22" - cell $_OR_ $auto$simplemap.cc:175:logic_reduce$231 - connect \Y $auto$simplemap.cc:166:logic_reduce$227 [3] + cell $_OR_ $auto$?:0:?$233 + connect \Y $auto$?:0:?$232 [0] + connect \B $auto$?:0:?$227 [1] + connect \A $auto$?:0:?$227 [0] + end + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$?:0:?$231 + connect \Y $auto$?:0:?$227 [3] connect \B $0\SF[0:0] connect \A $0\result[7:0] [6] end attribute \src "everything.v:27.9-27.22" - cell $_OR_ $auto$simplemap.cc:175:logic_reduce$230 - connect \Y $auto$simplemap.cc:166:logic_reduce$227 [2] + cell $_OR_ $auto$?:0:?$230 + connect \Y $auto$?:0:?$227 [2] connect \B $0\result[7:0] [5] connect \A $0\result[7:0] [4] end attribute \src "everything.v:27.9-27.22" - cell $_OR_ $auto$simplemap.cc:175:logic_reduce$229 - connect \Y $auto$simplemap.cc:166:logic_reduce$227 [1] + cell $_OR_ $auto$?:0:?$229 + connect \Y $auto$?:0:?$227 [1] connect \B $0\result[7:0] [3] connect \A $0\result[7:0] [2] end attribute \src "everything.v:27.9-27.22" - cell $_OR_ $auto$simplemap.cc:175:logic_reduce$228 - connect \Y $auto$simplemap.cc:166:logic_reduce$227 [0] + cell $_OR_ $auto$?:0:?$228 + connect \Y $auto$?:0:?$227 [0] connect \B $0\result[7:0] [1] connect \A $0\result[7:0] [0] end - attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_OR_ $auto$simplemap.cc:134:simplemap_reduce$253 - connect \Y $auto$simplemap.cc:254:simplemap_eqne$247 - connect \B $auto$simplemap.cc:125:simplemap_reduce$249 [1] - connect \A $auto$simplemap.cc:125:simplemap_reduce$249 [0] - end - attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_OR_ $auto$simplemap.cc:134:simplemap_reduce$250 - connect \Y $auto$simplemap.cc:125:simplemap_reduce$249 [0] - connect \B \operation [1] - connect \A $auto$rtlil.cc:3196:NotGate$497 - end attribute \src 0'x - cell $_OR_ $auto$simplemap.cc:134:simplemap_reduce$226 - connect \Y $auto$opt_dff.cc:247:make_patterns_logic$505 + cell $_OR_ $auto$?:0:?$226 + connect \Y $auto$?:0:?$32 connect \B $procmux$9_CMP connect \A $procmux$8_CMP end - cell $_NOT_ $auto$opt_expr.cc:617:replace_const_cells$502 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [8] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [8] - end - cell $_NOT_ $auto$opt_expr.cc:617:replace_const_cells$500 - connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [0] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [0] - end - cell $_NOT_ $auto$opt_expr.cc:617:replace_const_cells$496 - connect \Y $auto$rtlil.cc:3196:NotGate$497 - connect \A \operation [0] - end - attribute \src "everything.v:17.2-31.5" - cell $_DFFE_PP_ $auto$ff.cc:266:slice$504 - connect \Q \CF - connect \E $auto$opt_dff.cc:247:make_patterns_logic$505 - connect \D $0\CF[0:0] - connect \C \clk - end - attribute \src "everything.v:17.2-31.5" - cell $_DFF_P_ $auto$ff.cc:266:slice$289 - connect \Q \tmp [7] - connect \D $0\SF[0:0] - connect \C \clk - end - attribute \src "everything.v:17.2-31.5" - cell $_DFF_P_ $auto$ff.cc:266:slice$288 - connect \Q \tmp [6] - connect \D $0\result[7:0] [6] - connect \C \clk - end - attribute \src "everything.v:17.2-31.5" - cell $_DFF_P_ $auto$ff.cc:266:slice$287 - connect \Q \tmp [5] - connect \D $0\result[7:0] [5] - connect \C \clk - end - attribute \src "everything.v:17.2-31.5" - cell $_DFF_P_ $auto$ff.cc:266:slice$286 - connect \Q \tmp [4] - connect \D $0\result[7:0] [4] - connect \C \clk - end - attribute \src "everything.v:17.2-31.5" - cell $_DFF_P_ $auto$ff.cc:266:slice$285 - connect \Q \tmp [3] - connect \D $0\result[7:0] [3] - connect \C \clk - end - attribute \src "everything.v:17.2-31.5" - cell $_DFF_P_ $auto$ff.cc:266:slice$284 - connect \Q \tmp [2] - connect \D $0\result[7:0] [2] - connect \C \clk - end - attribute \src "everything.v:17.2-31.5" - cell $_DFF_P_ $auto$ff.cc:266:slice$283 - connect \Q \tmp [1] - connect \D $0\result[7:0] [1] - connect \C \clk - end - attribute \src "everything.v:17.2-31.5" - cell $_DFF_P_ $auto$ff.cc:266:slice$282 - connect \Q \tmp [0] - connect \D $0\result[7:0] [0] - connect \C \clk - end - attribute \src "everything.v:17.2-31.5" - cell $_DFF_P_ $auto$ff.cc:266:slice$280 - connect \Q \ZF - connect \D $0\ZF[0:0] - connect \C \clk - end connect $0\result[7:0] [7] $0\SF[0:0] - connect $auto$alumacc.cc:495:replace_alu$18.B [0] \B [0] - connect $auto$alumacc.cc:495:replace_alu$18.X [8] $auto$alumacc.cc:495:replace_alu$18.BB [8] - connect $auto$alumacc.cc:495:replace_alu$18.lcu.G [8] 1'0 - connect $auto$simplemap.cc:166:logic_reduce$265 [1] $auto$simplemap.cc:125:simplemap_reduce$249 [1] - connect { $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [8] $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [0] } { 1'1 $auto$alumacc.cc:495:replace_alu$18.BB [0] } - connect { $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [7] $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [0] } { $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [8] $auto$alumacc.cc:495:replace_alu$18.BB [0] } - connect $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [0] \B [0] + connect $auto$?:0:?$18.B [0] \B [0] + connect $auto$?:0:?$18.X [8] $auto$?:0:?$18.BB [8] + connect $auto$?:0:?$18.lcu.G [8] 1'0 + connect $auto$?:0:?$241 [3:1] \operation [3:1] + connect $auto$?:0:?$265 [1] $auto$?:0:?$249 [1] + connect { $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [8] $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [0] } { 1'1 $auto$?:0:?$18.BB [0] } + connect { $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [7] $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [0] } { $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [8] $auto$?:0:?$18.BB [0] } + connect $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [0] \B [0] connect \SF \tmp [7] connect \result \tmp [7:0] connect \tmp [8] \CF From 09c8530ceb94f1daf69bc782ed1dd51b6b03e06a Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 18 Sep 2025 20:56:25 +0200 Subject: [PATCH 18/18] Just don't sort --- backends/blif/blif.cc | 2 +- backends/jny/jny.cc | 2 +- backends/json/json.cc | 2 +- backends/table/table.cc | 2 +- backends/verilog/verilog_backend.cc | 2 +- passes/opt/opt.cc | 2 +- passes/opt/opt_clean.cc | 4 +- techlibs/ice40/ice40_opt.cc | 2 +- tests/arch/xilinx/dsp_cascade.ys | 2 +- tests/rtlil/roundtrip-text.synth.ref.il | 2023 +++++++++++------------ 10 files changed, 1017 insertions(+), 1026 deletions(-) diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index ab7861802c6..b0cc531655f 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -653,7 +653,7 @@ struct BlifBackend : public Backend { std::vector mod_list; - design->sort(); + // design->sort(); for (auto module : design->modules()) { if (module->get_blackbox_attribute() && !config.blackbox_mode) diff --git a/backends/jny/jny.cc b/backends/jny/jny.cc index ee0c0d14c4d..4c7b23cd00c 100644 --- a/backends/jny/jny.cc +++ b/backends/jny/jny.cc @@ -121,7 +121,7 @@ struct JnyWriter { log_assert(design != nullptr); - design->sort(); + // design->sort(); f << "{\n"; f << " \"$schema\": \"https://raw.githubusercontent.com/YosysHQ/yosys/main/misc/jny.schema.json\",\n"; diff --git a/backends/json/json.cc b/backends/json/json.cc index b0408362259..12a35ec9a25 100644 --- a/backends/json/json.cc +++ b/backends/json/json.cc @@ -288,7 +288,7 @@ struct JsonWriter void write_design(Design *design_) { design = design_; - design->sort(); + // design->sort(); f << stringf("{\n"); f << stringf(" \"creator\": %s,\n", get_string(yosys_maybe_version())); diff --git a/backends/table/table.cc b/backends/table/table.cc index 2bf64e7b1c6..f93c6bc0ff2 100644 --- a/backends/table/table.cc +++ b/backends/table/table.cc @@ -63,7 +63,7 @@ struct TableBackend : public Backend { } extra_args(f, filename, args, argidx); - design->sort(); + // design->sort(); for (auto module : design->modules()) { diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 987dc3ae109..682aace8309 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -2622,7 +2622,7 @@ struct VerilogBackend : public Backend { Pass::call(design, "clean_zerowidth"); log_pop(); - design->sort_modules(); + // design->sort_modules(); *f << stringf("/* Generated by %s */\n", yosys_maybe_version()); diff --git a/passes/opt/opt.cc b/passes/opt/opt.cc index ec5760cd973..43bd68a6434 100644 --- a/passes/opt/opt.cc +++ b/passes/opt/opt.cc @@ -193,7 +193,7 @@ struct OptPass : public Pass { } design->optimize(); - design->sort(); + // design->sort(); design->check(); log_header(design, "Finished fast OPT passes.%s\n", fast_mode ? "" : " (There is nothing left to do.)"); diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index cef2c0dc33c..a396a1d6e85 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -682,7 +682,7 @@ struct OptCleanPass : public Pass { log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires); design->optimize(); - design->sort(); + // design->sort(); design->check(); keep_cache.reset(); @@ -745,7 +745,7 @@ struct CleanPass : public Pass { log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires); design->optimize(); - design->sort(); + // design->sort(); design->check(); keep_cache.reset(); diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index b13d3301856..721d0e6148d 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -257,7 +257,7 @@ struct Ice40OptPass : public Pass { } design->optimize(); - design->sort(); + // design->sort(); design->check(); log_header(design, "Finished OPT passes. (There is nothing left to do.)\n"); diff --git a/tests/arch/xilinx/dsp_cascade.ys b/tests/arch/xilinx/dsp_cascade.ys index ca6b619b915..73f0e77a620 100644 --- a/tests/arch/xilinx/dsp_cascade.ys +++ b/tests/arch/xilinx/dsp_cascade.ys @@ -39,7 +39,7 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad design -load postopt cd cascade select -assert-count 3 t:DSP48A1 -select -assert-count 5 t:FDRE # No cascade for A input +select -assert-count 10 t:FDRE # No cascade for A input select -assert-none t:DSP48A1 t:BUFG t:FDRE %% t:* %D # Very crude method of checking that DSP48E1.PCOUT -> DSP48E1.PCIN # (see above for explanation) diff --git a/tests/rtlil/roundtrip-text.synth.ref.il b/tests/rtlil/roundtrip-text.synth.ref.il index 968b1887d6a..fc87f193239 100644 --- a/tests/rtlil/roundtrip-text.synth.ref.il +++ b/tests/rtlil/roundtrip-text.synth.ref.il @@ -1,1195 +1,1186 @@ -autoidx 511 -attribute \src "everything.v:34.1-40.10" -module \foo - attribute \src "everything.v:35.48-35.49" - wire width 8 output 3 \y - attribute \src "everything.v:37.16-37.18" - wire width 8 \bb - attribute \src "everything.v:35.32-35.33" - wire width 8 input 2 \b - attribute \src "everything.v:35.17-35.18" - wire width 8 input 1 \a - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - wire $techmap$auto$?:0:?$21.lcu.$or$+/techmap.v:240$150_Y - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - wire $techmap$auto$?:0:?$21.lcu.$or$+/techmap.v:240$147_Y - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - wire $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:248$173_Y - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - wire $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:248$170_Y - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - wire $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:248$167_Y - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - wire $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:248$164_Y - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:241$151_Y - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:241$148_Y - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:240$155_Y - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:240$149_Y - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:240$146_Y - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:240$143_Y - attribute \unused_bits "7" - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:214.23-214.24" +autoidx 505 +attribute \src "everything.v:1.1-32.10" +module \alu + attribute \src "everything.v:2.8-2.11" + wire input 1 \clk + attribute \src "everything.v:3.14-3.15" + wire width 8 input 2 \A + attribute \src "everything.v:4.14-4.15" + wire width 8 input 3 \B + attribute \src "everything.v:5.14-5.23" + wire width 4 input 4 \operation + attribute \src "everything.v:6.19-6.25" + wire width 8 output 5 \result + attribute \src "everything.v:7.13-7.15" + wire output 6 \CF + attribute \src "everything.v:8.13-8.15" + wire output 7 \ZF + attribute \src "everything.v:9.13-9.15" + wire output 8 \SF + attribute \src "everything.v:15.12-15.15" + wire width 9 \tmp + attribute \src "everything.v:17.2-31.5" + wire width 8 $0\result[7:0] + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$110.lcu.$and$+/techmap.v:241$234_Y + attribute \src "everything.v:17.2-31.5" + wire $0\ZF[0:0] + attribute \src "everything.v:17.2-31.5" + wire $0\SF[0:0] + wire $procmux$9_CMP + wire $procmux$8_CMP + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$256_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$226_Y + attribute \src "+/techmap.v:279.21-279.23" attribute \force_downto 1 - wire width 8 $auto$?:0:?$21.lcu.G - attribute \src "everything.v:39.16-39.22|+/techmap.v:270.23-270.24" + wire width 9 $techmap$auto$?:0:?$24.$auto$?:0:?$110.BB + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$110.lcu.$and$+/techmap.v:241$237_Y + attribute \src "+/techmap.v:274.23-274.25" attribute \force_downto 1 - wire width 8 $auto$?:0:?$21.X - attribute \unused_bits "7" - attribute \src "everything.v:39.16-39.22|+/techmap.v:274.23-274.25" + wire width 9 $techmap$auto$?:0:?$24.$auto$?:0:?$110.CO + wire $auto$?:0:?$32 + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$244_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$241_Y + attribute \src "+/techmap.v:270.26-270.27" attribute \force_downto 1 - wire width 8 $auto$?:0:?$21.CO - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" - cell $_OR_ $auto$?:0:?$219 - connect \Y $auto$?:0:?$21.CO [6] - connect \B $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:248$173_Y - connect \A $auto$?:0:?$21.lcu.G [6] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" - cell $_OR_ $auto$?:0:?$218 - connect \Y $auto$?:0:?$21.CO [4] - connect \B $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:248$170_Y - connect \A $auto$?:0:?$21.lcu.G [4] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" - cell $_OR_ $auto$?:0:?$217 - connect \Y $auto$?:0:?$21.CO [2] - connect \B $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:248$167_Y - connect \A $auto$?:0:?$21.lcu.G [2] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" - cell $_OR_ $auto$?:0:?$216 - connect \Y $auto$?:0:?$21.CO [5] - connect \B $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:248$164_Y - connect \A $techmap$auto$?:0:?$21.lcu.$or$+/techmap.v:240$150_Y - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$?:0:?$213 - connect \Y $auto$?:0:?$21.CO [3] - connect \B $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:240$155_Y - connect \A $techmap$auto$?:0:?$21.lcu.$or$+/techmap.v:240$147_Y - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$?:0:?$211 - connect \Y $techmap$auto$?:0:?$21.lcu.$or$+/techmap.v:240$150_Y - connect \B $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:240$149_Y - connect \A $auto$?:0:?$21.lcu.G [5] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$?:0:?$210 - connect \Y $techmap$auto$?:0:?$21.lcu.$or$+/techmap.v:240$147_Y - connect \B $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:240$146_Y - connect \A $auto$?:0:?$21.lcu.G [3] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$?:0:?$209 - connect \Y $auto$?:0:?$21.CO [1] - connect \B $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:240$143_Y - connect \A $auto$?:0:?$21.lcu.G [1] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$?:0:?$207 - connect \Y $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:248$173_Y - connect \B $auto$?:0:?$21.CO [5] - connect \A $auto$?:0:?$21.X [6] + wire width 9 $techmap$auto$?:0:?$24.$auto$?:0:?$110.Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$243_Y + wire width 4 $auto$?:0:?$113 + wire width 2 $auto$?:0:?$118 + wire $auto$?:0:?$121 + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$253_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:214.23-214.24" + attribute \force_downto 1 + wire width 9 $auto$?:0:?$18.lcu.G + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + wire $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$242_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$250_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$238_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$237_Y + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$110.lcu.$and$+/techmap.v:241$243_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.21-279.23" + attribute \force_downto 1 + wire width 9 $auto$?:0:?$18.BB + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + wire $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$236_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:274.23-274.25" + attribute \force_downto 1 + attribute \unused_bits "8" + wire width 9 $auto$?:0:?$18.CO + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$235_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$234_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:270.26-270.27" + attribute \force_downto 1 + wire width 9 $auto$?:0:?$18.Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:270.23-270.24" + attribute \force_downto 1 + wire width 9 $auto$?:0:?$18.X + attribute \src "everything.v:23.11-23.16|+/techmap.v:268.22-268.23" + attribute \force_downto 1 + wire width 9 $auto$?:0:?$18.B + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + wire $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$233_Y + wire width 4 $auto$?:0:?$129 + wire $auto$?:0:?$135 + wire width 2 $auto$?:0:?$137 + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$232_Y + wire width 2 $auto$?:0:?$153 + wire $auto$?:0:?$156 + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$231_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + wire $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$230_Y + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$110.lcu.$and$+/techmap.v:241$231_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$229_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$247_Y + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + cell $_AND_ $auto$?:0:?$365 + connect \A $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$110.lcu.$and$+/techmap.v:241$243_Y + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$110.CO [3] + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$110.CO [8] end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$?:0:?$206 - connect \Y $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:248$170_Y - connect \B $auto$?:0:?$21.CO [3] - connect \A $auto$?:0:?$21.X [4] + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$279 + connect \A $auto$?:0:?$18.B [8] + connect \Y $auto$?:0:?$18.BB [8] end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$?:0:?$205 - connect \Y $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:248$167_Y - connect \B $auto$?:0:?$21.CO [1] - connect \A $auto$?:0:?$21.X [2] + attribute \src "everything.v:27.9-27.22" + cell $_NOT_ $auto$?:0:?$123 + connect \A $auto$?:0:?$121 + connect \Y $0\ZF[0:0] end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$?:0:?$204 - connect \Y $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:248$164_Y - connect \B $auto$?:0:?$21.CO [3] - connect \A $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:241$151_Y + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_NOT_ $auto$?:0:?$143 + connect \A $auto$?:0:?$135 + connect \Y $procmux$8_CMP end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$?:0:?$201 - connect \Y $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:241$151_Y - connect \B $auto$?:0:?$21.X [4] - connect \A $auto$?:0:?$21.X [5] + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + cell $_AND_ $auto$?:0:?$372 + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$110.BB [7] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$110.BB [6] + connect \Y $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$110.lcu.$and$+/techmap.v:241$237_Y end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$?:0:?$200 - connect \Y $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:241$148_Y - connect \B $auto$?:0:?$21.X [2] - connect \A $auto$?:0:?$21.X [3] + attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" + cell $_NOT_ $auto$?:0:?$158 + connect \A $auto$?:0:?$156 + connect \Y $procmux$9_CMP end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$?:0:?$197 - connect \Y $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:240$155_Y - connect \B $auto$?:0:?$21.CO [1] - connect \A $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:241$148_Y + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + cell $_AND_ $auto$?:0:?$360 + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$110.BB [6] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$110.CO [5] + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$110.CO [6] end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$?:0:?$195 - connect \Y $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:240$149_Y - connect \B $auto$?:0:?$21.lcu.G [4] - connect \A $auto$?:0:?$21.X [5] + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + cell $_AND_ $auto$?:0:?$371 + connect \A $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$110.lcu.$and$+/techmap.v:241$231_Y + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$110.CO [1] + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$110.CO [3] end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$?:0:?$194 - connect \Y $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:240$146_Y - connect \B $auto$?:0:?$21.lcu.G [2] - connect \A $auto$?:0:?$21.X [3] + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$?:0:?$168 + connect \C \clk + connect \D $0\ZF[0:0] + connect \Q \ZF end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$?:0:?$193 - connect \Y $techmap$auto$?:0:?$21.lcu.$and$+/techmap.v:240$143_Y - connect \B $auto$?:0:?$21.CO [0] - connect \A $auto$?:0:?$21.X [1] + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + cell $_AND_ $auto$?:0:?$356 + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$110.BB [4] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$110.CO [3] + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$110.CO [4] end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$?:0:?$138 - connect \Y $auto$?:0:?$21.lcu.G [6] - connect \B \b [6] - connect \A \a [6] + attribute \src "everything.v:17.2-31.5" + cell $_DFFE_PP_ $auto$?:0:?$504 + connect \C \clk + connect \E $auto$?:0:?$32 + connect \D $auto$?:0:?$18.Y [8] + connect \Q \tmp [8] end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$?:0:?$137 - connect \Y $auto$?:0:?$21.lcu.G [5] - connect \B \b [5] - connect \A \a [5] + attribute \src 0'x + cell $_MUX_ $auto$?:0:?$189 + connect \A 1'0 + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$110.Y [8] + connect \S $auto$?:0:?$135 + connect \Y $auto$?:0:?$18.B [8] end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$?:0:?$136 - connect \Y $auto$?:0:?$21.lcu.G [4] - connect \B \b [4] - connect \A \a [4] + attribute \src 0'x + cell $_OR_ $auto$?:0:?$180 + connect \A $procmux$8_CMP + connect \B $procmux$9_CMP + connect \Y $auto$?:0:?$32 end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$?:0:?$135 - connect \Y $auto$?:0:?$21.lcu.G [3] - connect \B \b [3] - connect \A \a [3] + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$?:0:?$114 + connect \A $0\result[7:0] [0] + connect \B $0\result[7:0] [1] + connect \Y $auto$?:0:?$113 [0] end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$?:0:?$134 - connect \Y $auto$?:0:?$21.lcu.G [2] - connect \B \b [2] - connect \A \a [2] + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$?:0:?$115 + connect \A $0\result[7:0] [2] + connect \B $0\result[7:0] [3] + connect \Y $auto$?:0:?$113 [1] end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$?:0:?$133 - connect \Y $auto$?:0:?$21.lcu.G [1] - connect \B \b [1] - connect \A \a [1] + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$?:0:?$116 + connect \A $0\result[7:0] [4] + connect \B $0\result[7:0] [5] + connect \Y $auto$?:0:?$113 [2] end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$?:0:?$132 - connect \Y $auto$?:0:?$21.CO [0] - connect \B \b [0] - connect \A \a [0] + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$?:0:?$117 + connect \A $0\result[7:0] [6] + connect \B $0\SF[0:0] + connect \Y $auto$?:0:?$113 [3] end - attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$?:0:?$131 - connect \Y $auto$?:0:?$21.X [7] - connect \B \b [7] - connect \A \a [7] + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$?:0:?$119 + connect \A $auto$?:0:?$113 [0] + connect \B $auto$?:0:?$113 [1] + connect \Y $auto$?:0:?$118 [0] end - attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$?:0:?$130 - connect \Y $auto$?:0:?$21.X [6] - connect \B \b [6] - connect \A \a [6] + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$?:0:?$120 + connect \A $auto$?:0:?$113 [2] + connect \B $auto$?:0:?$113 [3] + connect \Y $auto$?:0:?$118 [1] end - attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$?:0:?$129 - connect \Y $auto$?:0:?$21.X [5] - connect \B \b [5] - connect \A \a [5] + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$?:0:?$122 + connect \A $auto$?:0:?$118 [0] + connect \B $auto$?:0:?$118 [1] + connect \Y $auto$?:0:?$121 end - attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$?:0:?$128 - connect \Y $auto$?:0:?$21.X [4] - connect \B \b [4] - connect \A \a [4] + attribute \src "+/techmap.v:289.13-289.25" + cell $_XOR_ $auto$?:0:?$287 + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$110.BB [7] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$110.CO [6] + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$110.Y [7] end - attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$?:0:?$127 - connect \Y $auto$?:0:?$21.X [3] - connect \B \b [3] - connect \A \a [3] + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$271 + connect \A \B [0] + connect \Y $auto$?:0:?$18.BB [0] end - attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$?:0:?$126 - connect \Y $auto$?:0:?$21.X [2] - connect \B \b [2] - connect \A \a [2] + attribute \src "+/techmap.v:289.13-289.25" + cell $_XOR_ $auto$?:0:?$285 + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$110.BB [5] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$110.CO [4] + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$110.Y [5] end - attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$?:0:?$125 - connect \Y $auto$?:0:?$21.X [1] - connect \B \b [1] - connect \A \a [1] + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + cell $_AND_ $auto$?:0:?$362 + connect \A $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$110.lcu.$and$+/techmap.v:241$234_Y + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$110.CO [3] + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$110.CO [5] end - attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$?:0:?$124 - connect \Y \y [0] - connect \B \b [0] - connect \A \a [0] + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:231.10-231.28" + cell $_OR_ $auto$?:0:?$354 + connect \A $auto$?:0:?$18.lcu.G [0] + connect \B $auto$?:0:?$18.X [0] + connect \Y $auto$?:0:?$18.CO [0] end - attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$?:0:?$122 - connect \Y \y [7] - connect \B $auto$?:0:?$21.CO [6] - connect \A $auto$?:0:?$21.X [7] + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + cell $_AND_ $auto$?:0:?$353 + connect \A $auto$?:0:?$18.X [1] + connect \B $auto$?:0:?$18.CO [0] + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$226_Y end - attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$?:0:?$121 - connect \Y \y [6] - connect \B $auto$?:0:?$21.CO [5] - connect \A $auto$?:0:?$21.X [6] + attribute \src "+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$320 + connect \A \B [3] + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$110.BB [3] end - attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$?:0:?$120 - connect \Y \y [5] - connect \B $auto$?:0:?$21.CO [4] - connect \A $auto$?:0:?$21.X [5] + attribute \src "+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$323 + connect \A \B [6] + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$110.BB [6] end - attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$?:0:?$119 - connect \Y \y [4] - connect \B $auto$?:0:?$21.CO [3] - connect \A $auto$?:0:?$21.X [4] + cell $_NOT_ $auto$?:0:?$496 + connect \A \operation [0] + connect \Y $auto$?:0:?$129 [0] end - attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$?:0:?$118 - connect \Y \y [3] - connect \B $auto$?:0:?$21.CO [2] - connect \A $auto$?:0:?$21.X [3] + attribute \src "+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$324 + connect \A \B [7] + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$110.BB [7] end - attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$?:0:?$117 - connect \Y \y [2] - connect \B $auto$?:0:?$21.CO [1] - connect \A $auto$?:0:?$21.X [2] + attribute \src "+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$322 + connect \A \B [5] + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$110.BB [5] end - attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$?:0:?$116 - connect \Y \y [1] - connect \B $auto$?:0:?$21.CO [0] - connect \A $auto$?:0:?$21.X [1] + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_OR_ $auto$?:0:?$141 + connect \A $auto$?:0:?$137 [0] + connect \B $auto$?:0:?$137 [1] + connect \Y $auto$?:0:?$135 end - connect $auto$?:0:?$21.X [0] \y [0] - connect $auto$?:0:?$21.lcu.G [0] $auto$?:0:?$21.CO [0] - connect \bb \b -end -attribute \src "everything.v:1.1-32.10" -module \alu - attribute \src "everything.v:15.12-15.15" - wire width 9 \tmp - attribute \src "everything.v:6.19-6.25" - wire width 8 output 5 \result - attribute \src "everything.v:5.14-5.23" - wire width 4 input 4 \operation - attribute \src "everything.v:2.8-2.11" - wire input 1 \clk - attribute \src "everything.v:8.13-8.15" - wire output 7 \ZF - attribute \src "everything.v:9.13-9.15" - wire output 8 \SF - attribute \src "everything.v:7.13-7.15" - wire output 6 \CF - attribute \src "everything.v:4.14-4.15" - wire width 8 input 3 \B - attribute \src "everything.v:3.14-3.15" - wire width 8 input 2 \A - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$238.lcu.$and$+/techmap.v:241$348_Y - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$238.lcu.$and$+/techmap.v:241$342_Y - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$238.lcu.$and$+/techmap.v:241$339_Y - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$238.lcu.$and$+/techmap.v:241$336_Y - attribute \src "+/techmap.v:270.26-270.27" - attribute \force_downto 1 - wire width 9 $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y - attribute \src "+/techmap.v:274.23-274.25" - attribute \force_downto 1 - wire width 9 $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO - attribute \src "+/techmap.v:279.21-279.23" - attribute \force_downto 1 - wire width 9 $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - wire $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$347_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - wire $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$341_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - wire $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$338_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - wire $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$335_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$361_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$358_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$355_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$352_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$348_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$342_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$339_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$336_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$349_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$346_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$343_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$340_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$337_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$334_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$331_Y - wire $procmux$9_CMP - wire $procmux$8_CMP - wire $auto$?:0:?$32 - wire $auto$?:0:?$268 - wire width 2 $auto$?:0:?$265 - wire width 2 $auto$?:0:?$249 - wire $auto$?:0:?$247 - wire width 4 $auto$?:0:?$241 - wire $auto$?:0:?$235 - wire width 2 $auto$?:0:?$232 - wire width 4 $auto$?:0:?$227 - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:214.23-214.24" - attribute \force_downto 1 - wire width 9 $auto$?:0:?$18.lcu.G - attribute \src "everything.v:23.11-23.16|+/techmap.v:270.26-270.27" - attribute \force_downto 1 - wire width 9 $auto$?:0:?$18.Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:270.23-270.24" - attribute \force_downto 1 - wire width 9 $auto$?:0:?$18.X - attribute \unused_bits "8" - attribute \src "everything.v:23.11-23.16|+/techmap.v:274.23-274.25" - attribute \force_downto 1 - wire width 9 $auto$?:0:?$18.CO - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.21-279.23" - attribute \force_downto 1 - wire width 9 $auto$?:0:?$18.BB - attribute \src "everything.v:23.11-23.16|+/techmap.v:268.22-268.23" - attribute \force_downto 1 - wire width 9 $auto$?:0:?$18.B - attribute \src "everything.v:17.2-31.5" - wire width 8 $0\result[7:0] - attribute \src "everything.v:17.2-31.5" - wire $0\ZF[0:0] - attribute \src "everything.v:17.2-31.5" - wire $0\SF[0:0] - attribute \src "everything.v:17.2-31.5" - wire $0\CF[0:0] - attribute \src "everything.v:17.2-31.5" - cell $_DFFE_PP_ $auto$?:0:?$504 - connect \Q \CF - connect \E $auto$?:0:?$32 - connect \D $0\CF[0:0] - connect \C \clk + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_OR_ $auto$?:0:?$138 + connect \A $auto$?:0:?$129 [0] + connect \B \operation [1] + connect \Y $auto$?:0:?$137 [0] end - cell $_NOT_ $auto$?:0:?$502 - connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [8] - connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [8] + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$272 + connect \A $auto$?:0:?$18.B [1] + connect \Y $auto$?:0:?$18.BB [1] end - cell $_NOT_ $auto$?:0:?$500 - connect \Y $auto$?:0:?$18.Y [0] - connect \A $auto$?:0:?$18.X [0] + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$?:0:?$144 + connect \A \tmp [0] + connect \B $auto$?:0:?$18.Y [0] + connect \S $auto$?:0:?$32 + connect \Y $0\result[7:0] [0] end - cell $_NOT_ $auto$?:0:?$496 - connect \Y $auto$?:0:?$241 [0] - connect \A \operation [0] + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$?:0:?$145 + connect \A \tmp [1] + connect \B $auto$?:0:?$18.Y [1] + connect \S $auto$?:0:?$32 + connect \Y $0\result[7:0] [1] end - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$?:0:?$481 - connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [6] - connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [5] - connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [6] + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$?:0:?$146 + connect \A \tmp [2] + connect \B $auto$?:0:?$18.Y [2] + connect \S $auto$?:0:?$32 + connect \Y $0\result[7:0] [2] end - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$?:0:?$480 - connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [4] - connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [3] - connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [4] + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$?:0:?$147 + connect \A \tmp [3] + connect \B $auto$?:0:?$18.Y [3] + connect \S $auto$?:0:?$32 + connect \Y $0\result[7:0] [3] end - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$?:0:?$479 - connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [2] - connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [1] - connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [2] + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$?:0:?$148 + connect \A \tmp [4] + connect \B $auto$?:0:?$18.Y [4] + connect \S $auto$?:0:?$32 + connect \Y $0\result[7:0] [4] end - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$?:0:?$478 - connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [5] - connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [3] - connect \A $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$238.lcu.$and$+/techmap.v:241$339_Y + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$?:0:?$149 + connect \A \tmp [5] + connect \B $auto$?:0:?$18.Y [5] + connect \S $auto$?:0:?$32 + connect \Y $0\result[7:0] [5] end - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$?:0:?$477 - connect \Y $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$238.lcu.$and$+/techmap.v:241$348_Y - connect \B $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$238.lcu.$and$+/techmap.v:241$339_Y - connect \A $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$238.lcu.$and$+/techmap.v:241$342_Y + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$?:0:?$150 + connect \A \tmp [6] + connect \B $auto$?:0:?$18.Y [6] + connect \S $auto$?:0:?$32 + connect \Y $0\result[7:0] [6] end - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$?:0:?$476 - connect \Y $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$238.lcu.$and$+/techmap.v:241$342_Y - connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [6] - connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [7] + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$?:0:?$151 + connect \A \tmp [7] + connect \B $auto$?:0:?$18.Y [7] + connect \S $auto$?:0:?$32 + connect \Y $0\SF[0:0] end - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$?:0:?$475 - connect \Y $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$238.lcu.$and$+/techmap.v:241$339_Y - connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [4] - connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [5] + attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" + cell $_OR_ $auto$?:0:?$154 + connect \A \operation [0] + connect \B \operation [1] + connect \Y $auto$?:0:?$153 [0] end - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$?:0:?$474 - connect \Y $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$238.lcu.$and$+/techmap.v:241$336_Y - connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [2] - connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [3] + attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" + cell $_OR_ $auto$?:0:?$155 + connect \A \operation [2] + connect \B \operation [3] + connect \Y $auto$?:0:?$137 [1] end - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$?:0:?$473 - connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [8] - connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [3] - connect \A $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$238.lcu.$and$+/techmap.v:241$348_Y + attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" + cell $_OR_ $auto$?:0:?$157 + connect \A $auto$?:0:?$153 [0] + connect \B $auto$?:0:?$137 [1] + connect \Y $auto$?:0:?$156 end - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$?:0:?$471 - connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [3] - connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [1] - connect \A $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$238.lcu.$and$+/techmap.v:241$336_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$273 + connect \A $auto$?:0:?$18.B [2] + connect \Y $auto$?:0:?$18.BB [2] end - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$?:0:?$467 - connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [1] - connect \B $auto$?:0:?$18.BB [0] - connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [1] + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$274 + connect \A $auto$?:0:?$18.B [3] + connect \Y $auto$?:0:?$18.BB [3] end - attribute \src "+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$?:0:?$464 - connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [7] - connect \A \B [7] + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$275 + connect \A $auto$?:0:?$18.B [4] + connect \Y $auto$?:0:?$18.BB [4] end - attribute \src "+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$?:0:?$463 - connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [6] - connect \A \B [6] + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$276 + connect \A $auto$?:0:?$18.B [5] + connect \Y $auto$?:0:?$18.BB [5] end - attribute \src "+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$?:0:?$462 - connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [5] - connect \A \B [5] + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$277 + connect \A $auto$?:0:?$18.B [6] + connect \Y $auto$?:0:?$18.BB [6] end - attribute \src "+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$?:0:?$461 - connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [4] - connect \A \B [4] + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$278 + connect \A $auto$?:0:?$18.B [7] + connect \Y $auto$?:0:?$18.BB [7] end - attribute \src "+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$?:0:?$460 - connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [3] - connect \A \B [3] + attribute \src "+/techmap.v:289.13-289.25" + cell $_XOR_ $auto$?:0:?$282 + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$110.BB [2] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$110.CO [1] + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$110.Y [2] end - attribute \src "+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$?:0:?$459 - connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [2] - connect \A \B [2] + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$?:0:?$170 + connect \C \clk + connect \D $0\result[7:0] [0] + connect \Q \tmp [0] end - attribute \src "+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$?:0:?$458 - connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [1] - connect \A \B [1] + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$?:0:?$171 + connect \C \clk + connect \D $0\result[7:0] [1] + connect \Q \tmp [1] end - attribute \src "+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$?:0:?$427 - connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [7] - connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [6] - connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [7] + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$?:0:?$172 + connect \C \clk + connect \D $0\result[7:0] [2] + connect \Q \tmp [2] end - attribute \src "+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$?:0:?$426 - connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [6] - connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [5] - connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [6] + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$?:0:?$173 + connect \C \clk + connect \D $0\result[7:0] [3] + connect \Q \tmp [3] end - attribute \src "+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$?:0:?$425 - connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [5] - connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [4] - connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [5] + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$?:0:?$174 + connect \C \clk + connect \D $0\result[7:0] [4] + connect \Q \tmp [4] end - attribute \src "+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$?:0:?$424 - connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [4] - connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [3] - connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [4] + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$?:0:?$175 + connect \C \clk + connect \D $0\result[7:0] [5] + connect \Q \tmp [5] end - attribute \src "+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$?:0:?$423 - connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [3] - connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [2] - connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [3] + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$?:0:?$176 + connect \C \clk + connect \D $0\result[7:0] [6] + connect \Q \tmp [6] end - attribute \src "+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$?:0:?$422 - connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [2] - connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [1] - connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [2] + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$?:0:?$177 + connect \C \clk + connect \D $0\SF[0:0] + connect \Q \tmp [7] end attribute \src "+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$?:0:?$421 - connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [1] + cell $_XOR_ $auto$?:0:?$281 + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$110.BB [1] connect \B $auto$?:0:?$18.BB [0] - connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [1] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" - cell $_OR_ $auto$?:0:?$418 - connect \Y $auto$?:0:?$18.CO [6] - connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$361_Y - connect \A $auto$?:0:?$18.lcu.G [6] + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$110.Y [1] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" - cell $_OR_ $auto$?:0:?$417 - connect \Y $auto$?:0:?$18.CO [4] - connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$358_Y - connect \A $auto$?:0:?$18.lcu.G [4] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" - cell $_OR_ $auto$?:0:?$416 - connect \Y $auto$?:0:?$18.CO [2] - connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$355_Y - connect \A $auto$?:0:?$18.lcu.G [2] + attribute \src 0'x + cell $_MUX_ $auto$?:0:?$182 + connect \A \B [1] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$110.Y [1] + connect \S $auto$?:0:?$135 + connect \Y $auto$?:0:?$18.B [1] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" - cell $_OR_ $auto$?:0:?$415 - connect \Y $auto$?:0:?$18.CO [5] - connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$352_Y - connect \A $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$338_Y + attribute \src 0'x + cell $_MUX_ $auto$?:0:?$183 + connect \A \B [2] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$110.Y [2] + connect \S $auto$?:0:?$135 + connect \Y $auto$?:0:?$18.B [2] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$?:0:?$414 - connect \Y $auto$?:0:?$18.CO [7] - connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$349_Y - connect \A $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$347_Y + attribute \src 0'x + cell $_MUX_ $auto$?:0:?$184 + connect \A \B [3] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$110.Y [3] + connect \S $auto$?:0:?$135 + connect \Y $auto$?:0:?$18.B [3] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$?:0:?$413 - connect \Y $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$347_Y - connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$346_Y - connect \A $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$341_Y + attribute \src 0'x + cell $_MUX_ $auto$?:0:?$185 + connect \A \B [4] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$110.Y [4] + connect \S $auto$?:0:?$135 + connect \Y $auto$?:0:?$18.B [4] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$?:0:?$412 - connect \Y $auto$?:0:?$18.CO [3] - connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$343_Y - connect \A $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$335_Y + attribute \src 0'x + cell $_MUX_ $auto$?:0:?$186 + connect \A \B [5] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$110.Y [5] + connect \S $auto$?:0:?$135 + connect \Y $auto$?:0:?$18.B [5] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$?:0:?$411 - connect \Y $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$341_Y - connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$340_Y - connect \A $auto$?:0:?$18.lcu.G [7] + attribute \src 0'x + cell $_MUX_ $auto$?:0:?$187 + connect \A \B [6] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$110.Y [6] + connect \S $auto$?:0:?$135 + connect \Y $auto$?:0:?$18.B [6] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$?:0:?$410 - connect \Y $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$338_Y - connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$337_Y - connect \A $auto$?:0:?$18.lcu.G [5] + attribute \src 0'x + cell $_MUX_ $auto$?:0:?$188 + connect \A \B [7] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$110.Y [7] + connect \S $auto$?:0:?$135 + connect \Y $auto$?:0:?$18.B [7] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$?:0:?$409 - connect \Y $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$335_Y - connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$334_Y - connect \A $auto$?:0:?$18.lcu.G [3] + attribute \src "+/techmap.v:289.13-289.25" + cell $_XOR_ $auto$?:0:?$283 + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$110.BB [3] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$110.CO [2] + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$110.Y [3] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$?:0:?$408 - connect \Y $auto$?:0:?$18.CO [1] - connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$331_Y - connect \A $auto$?:0:?$18.lcu.G [1] + attribute \src "+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$318 + connect \A \B [1] + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$110.BB [1] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:231.10-231.28" - cell $_OR_ $auto$?:0:?$407 - connect \Y $auto$?:0:?$18.CO [0] - connect \B $auto$?:0:?$18.X [0] - connect \A $auto$?:0:?$18.lcu.G [0] + attribute \src "+/techmap.v:289.13-289.25" + cell $_XOR_ $auto$?:0:?$286 + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$110.BB [6] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$110.CO [5] + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$110.Y [6] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$?:0:?$405 - connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$361_Y - connect \B $auto$?:0:?$18.CO [5] - connect \A $auto$?:0:?$18.X [6] + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + cell $_AND_ $auto$?:0:?$366 + connect \A $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$110.lcu.$and$+/techmap.v:241$237_Y + connect \B $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$110.lcu.$and$+/techmap.v:241$234_Y + connect \Y $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$110.lcu.$and$+/techmap.v:241$243_Y end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$?:0:?$404 - connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$358_Y - connect \B $auto$?:0:?$18.CO [3] - connect \A $auto$?:0:?$18.X [4] + attribute \src "+/techmap.v:289.13-289.25" + cell $_XOR_ $auto$?:0:?$284 + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$110.BB [4] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$110.CO [3] + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$110.Y [4] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$?:0:?$403 - connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$355_Y - connect \B $auto$?:0:?$18.CO [1] - connect \A $auto$?:0:?$18.X [2] + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + cell $_AND_ $auto$?:0:?$383 + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$110.BB [1] + connect \B $auto$?:0:?$18.BB [0] + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$110.CO [1] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$?:0:?$402 - connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$352_Y - connect \B $auto$?:0:?$18.CO [3] - connect \A $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$339_Y + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + cell $_AND_ $auto$?:0:?$378 + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$110.BB [3] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$110.BB [2] + connect \Y $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$110.lcu.$and$+/techmap.v:241$231_Y end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$?:0:?$401 - connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$348_Y - connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$339_Y - connect \A $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$342_Y + cell $_NOT_ $auto$?:0:?$500 + connect \A $auto$?:0:?$18.X [0] + connect \Y $auto$?:0:?$18.Y [0] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$?:0:?$400 - connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$342_Y - connect \B $auto$?:0:?$18.X [6] - connect \A $auto$?:0:?$18.X [7] + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" + cell $_XOR_ $auto$?:0:?$196 + connect \A $auto$?:0:?$18.X [1] + connect \B $auto$?:0:?$18.CO [0] + connect \Y $auto$?:0:?$18.Y [1] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$?:0:?$399 - connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$339_Y - connect \B $auto$?:0:?$18.X [4] - connect \A $auto$?:0:?$18.X [5] + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" + cell $_XOR_ $auto$?:0:?$197 + connect \A $auto$?:0:?$18.X [2] + connect \B $auto$?:0:?$18.CO [1] + connect \Y $auto$?:0:?$18.Y [2] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$?:0:?$398 - connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$336_Y - connect \B $auto$?:0:?$18.X [2] + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" + cell $_XOR_ $auto$?:0:?$198 connect \A $auto$?:0:?$18.X [3] + connect \B $auto$?:0:?$18.CO [2] + connect \Y $auto$?:0:?$18.Y [3] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$?:0:?$397 - connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$349_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" + cell $_XOR_ $auto$?:0:?$199 + connect \A $auto$?:0:?$18.X [4] connect \B $auto$?:0:?$18.CO [3] - connect \A $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$348_Y - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$?:0:?$396 - connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$346_Y - connect \B $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$338_Y - connect \A $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$342_Y - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$?:0:?$395 - connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$343_Y - connect \B $auto$?:0:?$18.CO [1] - connect \A $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$336_Y - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$?:0:?$394 - connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$340_Y - connect \B $auto$?:0:?$18.lcu.G [6] - connect \A $auto$?:0:?$18.X [7] + connect \Y $auto$?:0:?$18.Y [4] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$?:0:?$393 - connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$337_Y - connect \B $auto$?:0:?$18.lcu.G [4] + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" + cell $_XOR_ $auto$?:0:?$200 connect \A $auto$?:0:?$18.X [5] + connect \B $auto$?:0:?$18.CO [4] + connect \Y $auto$?:0:?$18.Y [5] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$?:0:?$392 - connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$334_Y - connect \B $auto$?:0:?$18.lcu.G [2] - connect \A $auto$?:0:?$18.X [3] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$?:0:?$391 - connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$331_Y - connect \B $auto$?:0:?$18.CO [0] - connect \A $auto$?:0:?$18.X [1] + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" + cell $_XOR_ $auto$?:0:?$201 + connect \A $auto$?:0:?$18.X [6] + connect \B $auto$?:0:?$18.CO [5] + connect \Y $auto$?:0:?$18.Y [6] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$?:0:?$384 - connect \Y $auto$?:0:?$18.BB [8] - connect \A $auto$?:0:?$18.B [8] + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" + cell $_XOR_ $auto$?:0:?$202 + connect \A $auto$?:0:?$18.X [7] + connect \B $auto$?:0:?$18.CO [6] + connect \Y $auto$?:0:?$18.Y [7] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$?:0:?$383 - connect \Y $auto$?:0:?$18.BB [7] - connect \A $auto$?:0:?$18.B [7] + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" + cell $_XOR_ $auto$?:0:?$203 + connect \A $auto$?:0:?$18.BB [8] + connect \B $auto$?:0:?$18.CO [7] + connect \Y $auto$?:0:?$18.Y [8] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$?:0:?$382 - connect \Y $auto$?:0:?$18.BB [6] - connect \A $auto$?:0:?$18.B [6] + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" + cell $_XOR_ $auto$?:0:?$205 + connect \A \A [0] + connect \B $auto$?:0:?$18.BB [0] + connect \Y $auto$?:0:?$18.X [0] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$?:0:?$381 - connect \Y $auto$?:0:?$18.BB [5] - connect \A $auto$?:0:?$18.B [5] + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" + cell $_XOR_ $auto$?:0:?$206 + connect \A \A [1] + connect \B $auto$?:0:?$18.BB [1] + connect \Y $auto$?:0:?$18.X [1] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$?:0:?$380 - connect \Y $auto$?:0:?$18.BB [4] - connect \A $auto$?:0:?$18.B [4] + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" + cell $_XOR_ $auto$?:0:?$207 + connect \A \A [2] + connect \B $auto$?:0:?$18.BB [2] + connect \Y $auto$?:0:?$18.X [2] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$?:0:?$379 - connect \Y $auto$?:0:?$18.BB [3] - connect \A $auto$?:0:?$18.B [3] + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" + cell $_XOR_ $auto$?:0:?$208 + connect \A \A [3] + connect \B $auto$?:0:?$18.BB [3] + connect \Y $auto$?:0:?$18.X [3] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$?:0:?$378 - connect \Y $auto$?:0:?$18.BB [2] - connect \A $auto$?:0:?$18.B [2] + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" + cell $_XOR_ $auto$?:0:?$209 + connect \A \A [4] + connect \B $auto$?:0:?$18.BB [4] + connect \Y $auto$?:0:?$18.X [4] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$?:0:?$377 - connect \Y $auto$?:0:?$18.BB [1] - connect \A $auto$?:0:?$18.B [1] + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" + cell $_XOR_ $auto$?:0:?$210 + connect \A \A [5] + connect \B $auto$?:0:?$18.BB [5] + connect \Y $auto$?:0:?$18.X [5] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$?:0:?$376 - connect \Y $auto$?:0:?$18.BB [0] - connect \A \B [0] + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" + cell $_XOR_ $auto$?:0:?$211 + connect \A \A [6] + connect \B $auto$?:0:?$18.BB [6] + connect \Y $auto$?:0:?$18.X [6] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$?:0:?$326 - connect \Y $auto$?:0:?$18.lcu.G [7] - connect \B $auto$?:0:?$18.BB [7] + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" + cell $_XOR_ $auto$?:0:?$212 connect \A \A [7] + connect \B $auto$?:0:?$18.BB [7] + connect \Y $auto$?:0:?$18.X [7] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$?:0:?$325 - connect \Y $auto$?:0:?$18.lcu.G [6] - connect \B $auto$?:0:?$18.BB [6] - connect \A \A [6] + cell $_AND_ $auto$?:0:?$214 + connect \A \A [0] + connect \B $auto$?:0:?$18.BB [0] + connect \Y $auto$?:0:?$18.lcu.G [0] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$?:0:?$324 - connect \Y $auto$?:0:?$18.lcu.G [5] - connect \B $auto$?:0:?$18.BB [5] - connect \A \A [5] + cell $_AND_ $auto$?:0:?$215 + connect \A \A [1] + connect \B $auto$?:0:?$18.BB [1] + connect \Y $auto$?:0:?$18.lcu.G [1] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$?:0:?$323 - connect \Y $auto$?:0:?$18.lcu.G [4] - connect \B $auto$?:0:?$18.BB [4] - connect \A \A [4] + cell $_AND_ $auto$?:0:?$216 + connect \A \A [2] + connect \B $auto$?:0:?$18.BB [2] + connect \Y $auto$?:0:?$18.lcu.G [2] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$?:0:?$322 - connect \Y $auto$?:0:?$18.lcu.G [3] - connect \B $auto$?:0:?$18.BB [3] + cell $_AND_ $auto$?:0:?$217 connect \A \A [3] + connect \B $auto$?:0:?$18.BB [3] + connect \Y $auto$?:0:?$18.lcu.G [3] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$?:0:?$321 - connect \Y $auto$?:0:?$18.lcu.G [2] - connect \B $auto$?:0:?$18.BB [2] - connect \A \A [2] + cell $_AND_ $auto$?:0:?$218 + connect \A \A [4] + connect \B $auto$?:0:?$18.BB [4] + connect \Y $auto$?:0:?$18.lcu.G [4] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$?:0:?$320 - connect \Y $auto$?:0:?$18.lcu.G [1] - connect \B $auto$?:0:?$18.BB [1] - connect \A \A [1] + cell $_AND_ $auto$?:0:?$219 + connect \A \A [5] + connect \B $auto$?:0:?$18.BB [5] + connect \Y $auto$?:0:?$18.lcu.G [5] end attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$?:0:?$319 - connect \Y $auto$?:0:?$18.lcu.G [0] - connect \B $auto$?:0:?$18.BB [0] - connect \A \A [0] + cell $_AND_ $auto$?:0:?$220 + connect \A \A [6] + connect \B $auto$?:0:?$18.BB [6] + connect \Y $auto$?:0:?$18.lcu.G [6] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$?:0:?$317 - connect \Y $auto$?:0:?$18.X [7] - connect \B $auto$?:0:?$18.BB [7] + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" + cell $_AND_ $auto$?:0:?$221 connect \A \A [7] + connect \B $auto$?:0:?$18.BB [7] + connect \Y $auto$?:0:?$18.lcu.G [7] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$?:0:?$316 - connect \Y $auto$?:0:?$18.X [6] - connect \B $auto$?:0:?$18.BB [6] - connect \A \A [6] + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + cell $_AND_ $auto$?:0:?$326 + connect \A $auto$?:0:?$18.X [4] + connect \B $auto$?:0:?$18.CO [3] + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$253_Y end - attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$?:0:?$315 - connect \Y $auto$?:0:?$18.X [5] - connect \B $auto$?:0:?$18.BB [5] - connect \A \A [5] + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" + cell $_OR_ $auto$?:0:?$327 + connect \A $auto$?:0:?$18.lcu.G [6] + connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$256_Y + connect \Y $auto$?:0:?$18.CO [6] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$?:0:?$314 - connect \Y $auto$?:0:?$18.X [4] - connect \B $auto$?:0:?$18.BB [4] - connect \A \A [4] + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" + cell $_OR_ $auto$?:0:?$328 + connect \A $auto$?:0:?$18.lcu.G [2] + connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$250_Y + connect \Y $auto$?:0:?$18.CO [2] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$?:0:?$313 - connect \Y $auto$?:0:?$18.X [3] - connect \B $auto$?:0:?$18.BB [3] - connect \A \A [3] + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + cell $_AND_ $auto$?:0:?$329 + connect \A $auto$?:0:?$18.X [2] + connect \B $auto$?:0:?$18.CO [1] + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$250_Y end - attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$?:0:?$312 - connect \Y $auto$?:0:?$18.X [2] - connect \B $auto$?:0:?$18.BB [2] - connect \A \A [2] + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + cell $_AND_ $auto$?:0:?$330 + connect \A $auto$?:0:?$18.X [6] + connect \B $auto$?:0:?$18.CO [5] + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$256_Y end - attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$?:0:?$311 - connect \Y $auto$?:0:?$18.X [1] - connect \B $auto$?:0:?$18.BB [1] - connect \A \A [1] + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" + cell $_OR_ $auto$?:0:?$331 + connect \A $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$233_Y + connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$247_Y + connect \Y $auto$?:0:?$18.CO [5] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$?:0:?$310 - connect \Y $auto$?:0:?$18.X [0] - connect \B $auto$?:0:?$18.BB [0] - connect \A \A [0] + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + cell $_AND_ $auto$?:0:?$332 + connect \A $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$234_Y + connect \B $auto$?:0:?$18.CO [3] + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$247_Y end - attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$?:0:?$308 - connect \Y $auto$?:0:?$18.Y [8] - connect \B $auto$?:0:?$18.CO [7] - connect \A $auto$?:0:?$18.BB [8] + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + cell $_AND_ $auto$?:0:?$359 + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$110.BB [2] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$110.CO [1] + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$110.CO [2] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$?:0:?$307 - connect \Y $auto$?:0:?$18.Y [7] - connect \B $auto$?:0:?$18.CO [6] - connect \A $auto$?:0:?$18.X [7] + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + cell $_OR_ $auto$?:0:?$334 + connect \A $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$242_Y + connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$244_Y + connect \Y $auto$?:0:?$18.CO [7] end - attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$?:0:?$306 - connect \Y $auto$?:0:?$18.Y [6] - connect \B $auto$?:0:?$18.CO [5] - connect \A $auto$?:0:?$18.X [6] + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + cell $_AND_ $auto$?:0:?$335 + connect \A $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$243_Y + connect \B $auto$?:0:?$18.CO [3] + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$244_Y end - attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$?:0:?$305 - connect \Y $auto$?:0:?$18.Y [5] - connect \B $auto$?:0:?$18.CO [4] - connect \A $auto$?:0:?$18.X [5] + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + cell $_AND_ $auto$?:0:?$336 + connect \A $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$237_Y + connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$234_Y + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$243_Y end - attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$?:0:?$304 - connect \Y $auto$?:0:?$18.Y [4] - connect \B $auto$?:0:?$18.CO [3] - connect \A $auto$?:0:?$18.X [4] + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + cell $_OR_ $auto$?:0:?$337 + connect \A $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$236_Y + connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$241_Y + connect \Y $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$242_Y end - attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$?:0:?$303 - connect \Y $auto$?:0:?$18.Y [3] - connect \B $auto$?:0:?$18.CO [2] - connect \A $auto$?:0:?$18.X [3] + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + cell $_AND_ $auto$?:0:?$338 + connect \A $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$237_Y + connect \B $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$233_Y + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$241_Y end - attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$?:0:?$302 - connect \Y $auto$?:0:?$18.Y [2] + cell $_NOT_ $auto$?:0:?$502 + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$110.CO [8] + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$110.Y [8] + end + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + cell $_OR_ $auto$?:0:?$340 + connect \A $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$230_Y + connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$238_Y + connect \Y $auto$?:0:?$18.CO [3] + end + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + cell $_AND_ $auto$?:0:?$341 + connect \A $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$231_Y connect \B $auto$?:0:?$18.CO [1] - connect \A $auto$?:0:?$18.X [2] + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$238_Y end - attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$?:0:?$301 - connect \Y $auto$?:0:?$18.Y [1] - connect \B $auto$?:0:?$18.CO [0] - connect \A $auto$?:0:?$18.X [1] + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + cell $_AND_ $auto$?:0:?$342 + connect \A $auto$?:0:?$18.X [7] + connect \B $auto$?:0:?$18.X [6] + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$237_Y end - attribute \src 0'x - cell $_MUX_ $auto$?:0:?$299 - connect \Y $auto$?:0:?$18.B [8] - connect \S $auto$?:0:?$247 - connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [8] - connect \A 1'0 + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + cell $_OR_ $auto$?:0:?$343 + connect \A $auto$?:0:?$18.lcu.G [7] + connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$235_Y + connect \Y $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$236_Y end - attribute \src 0'x - cell $_MUX_ $auto$?:0:?$298 - connect \Y $auto$?:0:?$18.B [7] - connect \S $auto$?:0:?$247 - connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [7] - connect \A \B [7] + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + cell $_AND_ $auto$?:0:?$344 + connect \A $auto$?:0:?$18.X [7] + connect \B $auto$?:0:?$18.lcu.G [6] + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$235_Y end - attribute \src 0'x - cell $_MUX_ $auto$?:0:?$297 - connect \Y $auto$?:0:?$18.B [6] - connect \S $auto$?:0:?$247 - connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [6] - connect \A \B [6] + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + cell $_AND_ $auto$?:0:?$345 + connect \A $auto$?:0:?$18.X [5] + connect \B $auto$?:0:?$18.X [4] + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$234_Y end - attribute \src 0'x - cell $_MUX_ $auto$?:0:?$296 - connect \Y $auto$?:0:?$18.B [5] - connect \S $auto$?:0:?$247 - connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [5] - connect \A \B [5] + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + cell $_OR_ $auto$?:0:?$346 + connect \A $auto$?:0:?$18.lcu.G [5] + connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$232_Y + connect \Y $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$233_Y + end + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + cell $_AND_ $auto$?:0:?$347 + connect \A $auto$?:0:?$18.X [5] + connect \B $auto$?:0:?$18.lcu.G [4] + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$232_Y + end + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + cell $_AND_ $auto$?:0:?$348 + connect \A $auto$?:0:?$18.X [3] + connect \B $auto$?:0:?$18.X [2] + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:241$231_Y + end + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + cell $_OR_ $auto$?:0:?$349 + connect \A $auto$?:0:?$18.lcu.G [3] + connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$229_Y + connect \Y $techmap$auto$?:0:?$18.lcu.$or$+/techmap.v:240$230_Y + end + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + cell $_AND_ $auto$?:0:?$350 + connect \A $auto$?:0:?$18.X [3] + connect \B $auto$?:0:?$18.lcu.G [2] + connect \Y $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$229_Y + end + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" + cell $_OR_ $auto$?:0:?$351 + connect \A $auto$?:0:?$18.lcu.G [4] + connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:248$253_Y + connect \Y $auto$?:0:?$18.CO [4] + end + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + cell $_OR_ $auto$?:0:?$352 + connect \A $auto$?:0:?$18.lcu.G [1] + connect \B $techmap$auto$?:0:?$18.lcu.$and$+/techmap.v:240$226_Y + connect \Y $auto$?:0:?$18.CO [1] end - attribute \src 0'x - cell $_MUX_ $auto$?:0:?$295 - connect \Y $auto$?:0:?$18.B [4] - connect \S $auto$?:0:?$247 - connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [4] + attribute \src "+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$321 connect \A \B [4] + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$110.BB [4] end - attribute \src 0'x - cell $_MUX_ $auto$?:0:?$294 - connect \Y $auto$?:0:?$18.B [3] - connect \S $auto$?:0:?$247 - connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [3] - connect \A \B [3] + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + cell $_AND_ $auto$?:0:?$375 + connect \A $techmap$auto$?:0:?$24.$auto$?:0:?$110.BB [5] + connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$110.BB [4] + connect \Y $techmap$techmap$auto$?:0:?$24.$auto$?:0:?$110.lcu.$and$+/techmap.v:241$234_Y end - attribute \src 0'x - cell $_MUX_ $auto$?:0:?$293 - connect \Y $auto$?:0:?$18.B [2] - connect \S $auto$?:0:?$247 - connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [2] + attribute \src "+/techmap.v:279.31-279.37" + cell $_NOT_ $auto$?:0:?$319 connect \A \B [2] + connect \Y $techmap$auto$?:0:?$24.$auto$?:0:?$110.BB [2] end - attribute \src 0'x - cell $_MUX_ $auto$?:0:?$292 - connect \Y $auto$?:0:?$18.B [1] - connect \S $auto$?:0:?$247 - connect \B $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [1] - connect \A \B [1] + connect $auto$?:0:?$153 [1] $auto$?:0:?$137 [1] + connect $auto$?:0:?$129 [3:1] \operation [3:1] + connect $auto$?:0:?$18.B [0] \B [0] + connect $auto$?:0:?$18.X [8] $auto$?:0:?$18.BB [8] + connect $auto$?:0:?$18.lcu.G [8] 1'0 + connect $techmap$auto$?:0:?$24.$auto$?:0:?$110.Y [0] \B [0] + connect { $techmap$auto$?:0:?$24.$auto$?:0:?$110.CO [7] $techmap$auto$?:0:?$24.$auto$?:0:?$110.CO [0] } { $techmap$auto$?:0:?$24.$auto$?:0:?$110.CO [8] $auto$?:0:?$18.BB [0] } + connect { $techmap$auto$?:0:?$24.$auto$?:0:?$110.BB [8] $techmap$auto$?:0:?$24.$auto$?:0:?$110.BB [0] } { 1'1 $auto$?:0:?$18.BB [0] } + connect $0\result[7:0] [7] $0\SF[0:0] + connect \SF \tmp [7] + connect \CF \tmp [8] + connect \result \tmp [7:0] +end +attribute \src "everything.v:34.1-40.10" +module \foo + attribute \src "everything.v:35.17-35.18" + wire width 8 input 1 \a + attribute \src "everything.v:35.32-35.33" + wire width 8 input 2 \b + attribute \src "everything.v:35.48-35.49" + wire width 8 output 3 \y + attribute \src "everything.v:37.16-37.18" + wire width 8 \bb + attribute \src "everything.v:39.16-39.22|+/techmap.v:270.23-270.24" + attribute \force_downto 1 + wire width 8 $auto$?:0:?$15.X + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:214.23-214.24" + attribute \force_downto 1 + attribute \unused_bits "7" + wire width 8 $auto$?:0:?$15.lcu.G + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:240$425_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:240$419_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:248$446_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:240$431_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:241$424_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:240$422_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:248$440_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:248$443_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + wire $techmap$auto$?:0:?$15.lcu.$or$+/techmap.v:240$423_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:274.23-274.25" + attribute \force_downto 1 + attribute \unused_bits "7" + wire width 8 $auto$?:0:?$15.CO + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:248$449_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:241$427_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + wire $techmap$auto$?:0:?$15.lcu.$or$+/techmap.v:240$426_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + cell $_AND_ $auto$?:0:?$488 + connect \A $auto$?:0:?$15.X [3] + connect \B $auto$?:0:?$15.X [2] + connect \Y $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:241$424_Y end - attribute \src "everything.v:17.2-31.5" - cell $_DFF_P_ $auto$?:0:?$289 - connect \Q \tmp [7] - connect \D $0\SF[0:0] - connect \C \clk + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + cell $_AND_ $auto$?:0:?$481 + connect \A $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:241$424_Y + connect \B $auto$?:0:?$15.CO [1] + connect \Y $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:240$431_Y end - attribute \src "everything.v:17.2-31.5" - cell $_DFF_P_ $auto$?:0:?$288 - connect \Q \tmp [6] - connect \D $0\result[7:0] [6] - connect \C \clk + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" + cell $_XOR_ $auto$?:0:?$407 + connect \A \a [7] + connect \B \b [7] + connect \Y $auto$?:0:?$15.X [7] end - attribute \src "everything.v:17.2-31.5" - cell $_DFF_P_ $auto$?:0:?$287 - connect \Q \tmp [5] - connect \D $0\result[7:0] [5] - connect \C \clk + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + cell $_AND_ $auto$?:0:?$485 + connect \A $auto$?:0:?$15.X [5] + connect \B $auto$?:0:?$15.X [4] + connect \Y $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:241$427_Y end - attribute \src "everything.v:17.2-31.5" - cell $_DFF_P_ $auto$?:0:?$286 - connect \Q \tmp [4] - connect \D $0\result[7:0] [4] - connect \C \clk + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + cell $_OR_ $auto$?:0:?$486 + connect \A $auto$?:0:?$15.lcu.G [5] + connect \B $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:240$425_Y + connect \Y $techmap$auto$?:0:?$15.lcu.$or$+/techmap.v:240$426_Y end - attribute \src "everything.v:17.2-31.5" - cell $_DFF_P_ $auto$?:0:?$285 - connect \Q \tmp [3] - connect \D $0\result[7:0] [3] - connect \C \clk + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + cell $_OR_ $auto$?:0:?$480 + connect \A $techmap$auto$?:0:?$15.lcu.$or$+/techmap.v:240$423_Y + connect \B $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:240$431_Y + connect \Y $auto$?:0:?$15.CO [3] end - attribute \src "everything.v:17.2-31.5" - cell $_DFF_P_ $auto$?:0:?$284 - connect \Q \tmp [2] - connect \D $0\result[7:0] [2] - connect \C \clk + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + cell $_AND_ $auto$?:0:?$493 + connect \A $auto$?:0:?$15.X [1] + connect \B $auto$?:0:?$15.CO [0] + connect \Y $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:240$419_Y end - attribute \src "everything.v:17.2-31.5" - cell $_DFF_P_ $auto$?:0:?$283 - connect \Q \tmp [1] - connect \D $0\result[7:0] [1] - connect \C \clk + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" + cell $_OR_ $auto$?:0:?$479 + connect \A $auto$?:0:?$15.lcu.G [6] + connect \B $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:248$449_Y + connect \Y $auto$?:0:?$15.CO [6] end - attribute \src "everything.v:17.2-31.5" - cell $_DFF_P_ $auto$?:0:?$282 - connect \Q \tmp [0] - connect \D $0\result[7:0] [0] - connect \C \clk + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + cell $_AND_ $auto$?:0:?$487 + connect \A $auto$?:0:?$15.X [5] + connect \B $auto$?:0:?$15.lcu.G [4] + connect \Y $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:240$425_Y end - attribute \src "everything.v:17.2-31.5" - cell $_DFF_P_ $auto$?:0:?$280 - connect \Q \ZF - connect \D $0\ZF[0:0] - connect \C \clk + attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" + cell $_XOR_ $auto$?:0:?$392 + connect \A $auto$?:0:?$15.X [1] + connect \B $auto$?:0:?$15.CO [0] + connect \Y \y [1] end - attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" - cell $_NOT_ $auto$?:0:?$270 - connect \Y $procmux$9_CMP - connect \A $auto$?:0:?$268 + attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" + cell $_XOR_ $auto$?:0:?$393 + connect \A $auto$?:0:?$15.X [2] + connect \B $auto$?:0:?$15.CO [1] + connect \Y \y [2] end - attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" - cell $_OR_ $auto$?:0:?$269 - connect \Y $auto$?:0:?$268 - connect \B $auto$?:0:?$249 [1] - connect \A $auto$?:0:?$265 [0] + attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" + cell $_XOR_ $auto$?:0:?$394 + connect \A $auto$?:0:?$15.X [3] + connect \B $auto$?:0:?$15.CO [2] + connect \Y \y [3] end - attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" - cell $_OR_ $auto$?:0:?$267 - connect \Y $auto$?:0:?$249 [1] - connect \B \operation [3] - connect \A \operation [2] + attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" + cell $_XOR_ $auto$?:0:?$395 + connect \A $auto$?:0:?$15.X [4] + connect \B $auto$?:0:?$15.CO [3] + connect \Y \y [4] end - attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" - cell $_OR_ $auto$?:0:?$266 - connect \Y $auto$?:0:?$265 [0] - connect \B \operation [1] - connect \A \operation [0] + attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" + cell $_XOR_ $auto$?:0:?$396 + connect \A $auto$?:0:?$15.X [5] + connect \B $auto$?:0:?$15.CO [4] + connect \Y \y [5] end - attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_MUX_ $auto$?:0:?$264 - connect \Y $0\CF[0:0] - connect \S $auto$?:0:?$32 - connect \B $auto$?:0:?$18.Y [8] - connect \A 1'x + attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" + cell $_XOR_ $auto$?:0:?$397 + connect \A $auto$?:0:?$15.X [6] + connect \B $auto$?:0:?$15.CO [5] + connect \Y \y [6] end - attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_MUX_ $auto$?:0:?$263 - connect \Y $0\SF[0:0] - connect \S $auto$?:0:?$32 - connect \B $auto$?:0:?$18.Y [7] - connect \A \tmp [7] + attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" + cell $_XOR_ $auto$?:0:?$398 + connect \A $auto$?:0:?$15.X [7] + connect \B $auto$?:0:?$15.CO [6] + connect \Y \y [7] end - attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_MUX_ $auto$?:0:?$262 - connect \Y $0\result[7:0] [6] - connect \S $auto$?:0:?$32 - connect \B $auto$?:0:?$18.Y [6] - connect \A \tmp [6] + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" + cell $_XOR_ $auto$?:0:?$400 + connect \A \a [0] + connect \B \b [0] + connect \Y \y [0] end - attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_MUX_ $auto$?:0:?$261 - connect \Y $0\result[7:0] [5] - connect \S $auto$?:0:?$32 - connect \B $auto$?:0:?$18.Y [5] - connect \A \tmp [5] + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" + cell $_XOR_ $auto$?:0:?$401 + connect \A \a [1] + connect \B \b [1] + connect \Y $auto$?:0:?$15.X [1] end - attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_MUX_ $auto$?:0:?$260 - connect \Y $0\result[7:0] [4] - connect \S $auto$?:0:?$32 - connect \B $auto$?:0:?$18.Y [4] - connect \A \tmp [4] + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" + cell $_XOR_ $auto$?:0:?$402 + connect \A \a [2] + connect \B \b [2] + connect \Y $auto$?:0:?$15.X [2] end - attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_MUX_ $auto$?:0:?$259 - connect \Y $0\result[7:0] [3] - connect \S $auto$?:0:?$32 - connect \B $auto$?:0:?$18.Y [3] - connect \A \tmp [3] + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" + cell $_XOR_ $auto$?:0:?$403 + connect \A \a [3] + connect \B \b [3] + connect \Y $auto$?:0:?$15.X [3] end - attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_MUX_ $auto$?:0:?$258 - connect \Y $0\result[7:0] [2] - connect \S $auto$?:0:?$32 - connect \B $auto$?:0:?$18.Y [2] - connect \A \tmp [2] + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" + cell $_XOR_ $auto$?:0:?$404 + connect \A \a [4] + connect \B \b [4] + connect \Y $auto$?:0:?$15.X [4] end - attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_MUX_ $auto$?:0:?$257 - connect \Y $0\result[7:0] [1] - connect \S $auto$?:0:?$32 - connect \B $auto$?:0:?$18.Y [1] - connect \A \tmp [1] + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" + cell $_XOR_ $auto$?:0:?$405 + connect \A \a [5] + connect \B \b [5] + connect \Y $auto$?:0:?$15.X [5] end - attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_MUX_ $auto$?:0:?$256 - connect \Y $0\result[7:0] [0] - connect \S $auto$?:0:?$32 - connect \B $auto$?:0:?$18.Y [0] - connect \A \tmp [0] + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" + cell $_XOR_ $auto$?:0:?$406 + connect \A \a [6] + connect \B \b [6] + connect \Y $auto$?:0:?$15.X [6] end - attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_NOT_ $auto$?:0:?$255 - connect \Y $procmux$8_CMP - connect \A $auto$?:0:?$247 + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" + cell $_AND_ $auto$?:0:?$408 + connect \A \a [0] + connect \B \b [0] + connect \Y $auto$?:0:?$15.CO [0] end - attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_OR_ $auto$?:0:?$253 - connect \Y $auto$?:0:?$247 - connect \B $auto$?:0:?$249 [1] - connect \A $auto$?:0:?$249 [0] + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" + cell $_AND_ $auto$?:0:?$409 + connect \A \a [1] + connect \B \b [1] + connect \Y $auto$?:0:?$15.lcu.G [1] end - attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_OR_ $auto$?:0:?$250 - connect \Y $auto$?:0:?$249 [0] - connect \B \operation [1] - connect \A $auto$?:0:?$241 [0] + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" + cell $_AND_ $auto$?:0:?$410 + connect \A \a [2] + connect \B \b [2] + connect \Y $auto$?:0:?$15.lcu.G [2] end - attribute \src "everything.v:27.9-27.22" - cell $_NOT_ $auto$?:0:?$237 - connect \Y $0\ZF[0:0] - connect \A $auto$?:0:?$235 + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" + cell $_AND_ $auto$?:0:?$411 + connect \A \a [3] + connect \B \b [3] + connect \Y $auto$?:0:?$15.lcu.G [3] end - attribute \src "everything.v:27.9-27.22" - cell $_OR_ $auto$?:0:?$236 - connect \Y $auto$?:0:?$235 - connect \B $auto$?:0:?$232 [1] - connect \A $auto$?:0:?$232 [0] + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" + cell $_AND_ $auto$?:0:?$412 + connect \A \a [4] + connect \B \b [4] + connect \Y $auto$?:0:?$15.lcu.G [4] end - attribute \src "everything.v:27.9-27.22" - cell $_OR_ $auto$?:0:?$234 - connect \Y $auto$?:0:?$232 [1] - connect \B $auto$?:0:?$227 [3] - connect \A $auto$?:0:?$227 [2] + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" + cell $_AND_ $auto$?:0:?$413 + connect \A \a [5] + connect \B \b [5] + connect \Y $auto$?:0:?$15.lcu.G [5] end - attribute \src "everything.v:27.9-27.22" - cell $_OR_ $auto$?:0:?$233 - connect \Y $auto$?:0:?$232 [0] - connect \B $auto$?:0:?$227 [1] - connect \A $auto$?:0:?$227 [0] + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" + cell $_AND_ $auto$?:0:?$414 + connect \A \a [6] + connect \B \b [6] + connect \Y $auto$?:0:?$15.lcu.G [6] end - attribute \src "everything.v:27.9-27.22" - cell $_OR_ $auto$?:0:?$231 - connect \Y $auto$?:0:?$227 [3] - connect \B $0\SF[0:0] - connect \A $0\result[7:0] [6] + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" + cell $_OR_ $auto$?:0:?$468 + connect \A $auto$?:0:?$15.lcu.G [2] + connect \B $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:248$443_Y + connect \Y $auto$?:0:?$15.CO [2] end - attribute \src "everything.v:27.9-27.22" - cell $_OR_ $auto$?:0:?$230 - connect \Y $auto$?:0:?$227 [2] - connect \B $0\result[7:0] [5] - connect \A $0\result[7:0] [4] + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + cell $_AND_ $auto$?:0:?$469 + connect \A $auto$?:0:?$15.X [2] + connect \B $auto$?:0:?$15.CO [1] + connect \Y $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:248$443_Y end - attribute \src "everything.v:27.9-27.22" - cell $_OR_ $auto$?:0:?$229 - connect \Y $auto$?:0:?$227 [1] - connect \B $0\result[7:0] [3] - connect \A $0\result[7:0] [2] + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + cell $_AND_ $auto$?:0:?$470 + connect \A $auto$?:0:?$15.X [4] + connect \B $auto$?:0:?$15.CO [3] + connect \Y $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:248$446_Y end - attribute \src "everything.v:27.9-27.22" - cell $_OR_ $auto$?:0:?$228 - connect \Y $auto$?:0:?$227 [0] - connect \B $0\result[7:0] [1] - connect \A $0\result[7:0] [0] + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" + cell $_OR_ $auto$?:0:?$471 + connect \A $techmap$auto$?:0:?$15.lcu.$or$+/techmap.v:240$426_Y + connect \B $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:248$440_Y + connect \Y $auto$?:0:?$15.CO [5] end - attribute \src 0'x - cell $_OR_ $auto$?:0:?$226 - connect \Y $auto$?:0:?$32 - connect \B $procmux$9_CMP - connect \A $procmux$8_CMP + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + cell $_AND_ $auto$?:0:?$472 + connect \A $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:241$427_Y + connect \B $auto$?:0:?$15.CO [3] + connect \Y $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:248$440_Y end - connect $0\result[7:0] [7] $0\SF[0:0] - connect $auto$?:0:?$18.B [0] \B [0] - connect $auto$?:0:?$18.X [8] $auto$?:0:?$18.BB [8] - connect $auto$?:0:?$18.lcu.G [8] 1'0 - connect $auto$?:0:?$241 [3:1] \operation [3:1] - connect $auto$?:0:?$265 [1] $auto$?:0:?$249 [1] - connect { $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [8] $techmap$auto$?:0:?$24.$auto$?:0:?$238.BB [0] } { 1'1 $auto$?:0:?$18.BB [0] } - connect { $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [7] $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [0] } { $techmap$auto$?:0:?$24.$auto$?:0:?$238.CO [8] $auto$?:0:?$18.BB [0] } - connect $techmap$auto$?:0:?$24.$auto$?:0:?$238.Y [0] \B [0] - connect \SF \tmp [7] - connect \result \tmp [7:0] - connect \tmp [8] \CF + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + cell $_AND_ $auto$?:0:?$473 + connect \A $auto$?:0:?$15.X [6] + connect \B $auto$?:0:?$15.CO [5] + connect \Y $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:248$449_Y + end + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + cell $_OR_ $auto$?:0:?$492 + connect \A $auto$?:0:?$15.lcu.G [1] + connect \B $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:240$419_Y + connect \Y $auto$?:0:?$15.CO [1] + end + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" + cell $_OR_ $auto$?:0:?$491 + connect \A $auto$?:0:?$15.lcu.G [4] + connect \B $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:248$446_Y + connect \Y $auto$?:0:?$15.CO [4] + end + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + cell $_AND_ $auto$?:0:?$490 + connect \A $auto$?:0:?$15.X [3] + connect \B $auto$?:0:?$15.lcu.G [2] + connect \Y $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:240$422_Y + end + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + cell $_OR_ $auto$?:0:?$489 + connect \A $auto$?:0:?$15.lcu.G [3] + connect \B $techmap$auto$?:0:?$15.lcu.$and$+/techmap.v:240$422_Y + connect \Y $techmap$auto$?:0:?$15.lcu.$or$+/techmap.v:240$423_Y + end + connect $auto$?:0:?$15.lcu.G [0] $auto$?:0:?$15.CO [0] + connect $auto$?:0:?$15.X [0] \y [0] + connect \bb \b end