altsyncram blocks should be abstracted

the altsyncram module used in ao68000 is only available on Altera. It would be preferable to have a custom memory module that instantiated the correct memory depended on the platform.

[alfikpl]

I agree. I plan to do some minor updates to the project in a month or two.

I recommend you do something like ...

module regram
(
input clock,
input [3:0] wea,

input [2:0] rs,
input [31:0] din,
output [31:0] dout

);

reg [31:0] mem_data[0:7];

always @(posedge clock)
begin

if (wea[0] === 1'b1) begin
    mem_data[rs][7:0] <= din[7:0];
end

if (wea[1] === 1'b1) begin
    mem_data[rs][15:8] <= din[15:8];
end

if (wea[2] === 1'b1) begin
    mem_data[rs][23:16] <= din[23:16];
end

if (wea[3] === 1'b1) begin
    mem_data[rs][31:24] <= din[31:24];
end

end

assign dout = mem_data[rs];

endmodule

and for the microcode you can do something like ...

module microcode
(
input clk, // bus clock
input [8:0] addr, // address in
output [31:0] data_out // data out
);

reg [8:0] romaddress;
reg [87:0] romdata;

// use clocked address to infer blockram
always @(negedge clk)
romaddress <= addr;

// if all goes well this rom will be implemented using blockram
always @(romaddress)
begin
case (romaddress)
0: romdata = 88'b0000000000000000000000000000000000000100000000000000000000000000000000000000000000000000;
1: romdata = 88'b0111111100000000000000000000000000000000000000000000000000000000000000000000000000000000;
2: romdata = 88'b1001111100000001011100000000000000000000000000000010100000000000000000000000000000000000;
3: romdata = 88'b0010111000000000000000001010100010010000000000100100000000000000000000110000000000000000;
4: romdata = 88'b0110111100000000000000010000000000000000000000000000000000000000000000000000000000000000;
5: romdata = 88'b0000000000000000000000000000000000000100000000000000000000000000000000000000000000000000;

      .... etc ..
      default: romdata = 88'b0000000000000000000000000000000000000100000000000000000000000000000000000000000000000000;
    endcase

end

assign data_out = romdata;

endmodule

Above code is not tested.

I also strongly recommend you take out the async reset code and make the reset pin synchronous with the clock to prevent nasty fanout issues.

[alfikpl]

Thank you for your suggestion. Making onchip RAM and ROM inferable is the proper thing to do. I believe that the multiplication module "lpm_mult" can also be infered by simply using "*".

Like I said, I plan to make the changes in a month or two. Right now I am busy working on some other project.

No worries. I thought it best to put the suggestions in here so they are not lost. i have struggled to get ao68000 working on xilinx. i see the first address select but never a second one.