projects/adrv9026:Add READMEs

Signed-off-by: Capota Bianca <[email protected]>

Author: BCapota

projects/adrv9026/README.md

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+# ADRV9026 HDL Project
+
+- Evaluation board product page: [EVAL-ADRV9026/ADRV9029](https://www.analog.com/eval-adrv9026)
+- System documentation: https://wiki.analog.com/resources/eval/user-guides/adrv9026/quickstart
+- HDL project documentation: https://analogdevicesinc.github.io/hdl/projects/adrv9026/index.html
+
+## Supported parts
+
+| Part name                                   | Description                                               |
+|---------------------------------------------|-----------------------------------------------------------|
+| [ADRV9026](https://www.analog.com/ADRV9026) | Integrated, Quad RF Transceiver with Observation Path     |
+| [ADRV9029](https://www.analog.com/ADRV9029) | Integrated, Quad RF Transceiver with Observation Path     |
+
+## Building the project
+
+Please enter the folder for the FPGA carrier you want to use and read the README.md.

projects/adrv9026/a10soc/README.md

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+# ADRV9026/A10SOC HDL Project
+
+## Building the project
+
+```
+cd projects/adrv9026/a10soc
+make
+```
+
+Corresponding device tree: [socfpga_arria10_socdk_adrv9025.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_adrv9025.dts)

projects/adrv9026/vcu118/README.md

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+# ADRV9026/VCU118 HDL Project
+
+## Building the project
+
+```
+cd projects/adrv9026/vcu118
+make
+```
+
+All of the RX/TX link modes can be found in the [ADRV9026 data sheet](https://www.analog.com/media/radioverse-adrv9026/adrv9026.pdf). We offer support for only a few of them.
+
+The overwritable parameters from the environment:
+
+- JESD_MODE - link layer encoder mode used;
+  - 8B10B - 8b10b link layer defined in JESD204B, uses ADI IP as Physical layer
+  - 64B66B - 64b66b link layer defined in JESD204C, uses Xilinx IP as Physical layer
+- [RX/TX]_LANE_RATE - lane rate of the [RX/TX] link (RX: MxFE to FPGA/TX: FPGA to MxFE)
+- [RX/TX]_NUM_LINKS - [RX/TX] number of links, which matches the number of MxFE devices
+- [RX/TX]_JESD_M - [RX/TX] number of converters per link
+- [RX/TX]_JESD_L - [RX/TX] number of lanes per link
+- [RX/TX]_JESD_S - [RX/TX] number of samples per converter per frame
+
+Corresponding device tree: [vcu118_adrv9025.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/microblaze/boot/dts/vcu118_adrv9025.dts)

projects/adrv9026/zcu102/README.md

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+# ADRV9026/ZCU102 HDL Project
+
+## Building the project
+
+```
+cd projects/adrv9026/zcu102
+make
+```
+
+All of the RX/TX link modes can be found in the [ADRV9026 data sheet](https://www.analog.com/media/radioverse-adrv9026/adrv9026.pdf). We offer support for only a few of them.
+
+The overwritable parameters from the environment:
+
+- JESD_MODE - link layer encoder mode used;
+  - 8B10B - 8b10b link layer defined in JESD204B, uses ADI IP as Physical layer
+  - 64B66B - 64b66b link layer defined in JESD204C, uses Xilinx IP as Physical layer
+- [RX/TX]_LANE_RATE - lane rate of the [RX/TX] link (RX: MxFE to FPGA/TX: FPGA to MxFE)
+- [RX/TX]_NUM_LINKS - [RX/TX] number of links, which matches the number of MxFE devices
+- [RX/TX]_JESD_M - [RX/TX] number of converters per link
+- [RX/TX]_JESD_L - [RX/TX] number of lanes per link
+- [RX/TX]_JESD_S - [RX/TX] number of samples per converter per frame
+
+Corresponding device tree: [zynqmp-zcu102-rev10-adrv9025.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9025.dts)