From 63696e56a519a73e3cf8aec7be40965ac8bc20b8 Mon Sep 17 00:00:00 2001 From: AndrDragomir Date: Thu, 21 Nov 2024 17:27:33 +0200 Subject: [PATCH] adrv9009: Add kcu105 support Signed-off-by: AndrDragomir --- docs/projects/adrv9009/index.rst | 59 ++-- projects/adrv9009/common/adrv9009_bd.tcl | 6 +- projects/adrv9009/kcu105/Makefile | 42 +++ projects/adrv9009/kcu105/system_bd.tcl | 54 ++++ projects/adrv9009/kcu105/system_constr.xdc | 99 ++++++ projects/adrv9009/kcu105/system_project.tcl | 49 +++ projects/adrv9009/kcu105/system_top.v | 327 ++++++++++++++++++++ 7 files changed, 612 insertions(+), 24 deletions(-) create mode 100644 projects/adrv9009/kcu105/Makefile create mode 100644 projects/adrv9009/kcu105/system_bd.tcl create mode 100644 projects/adrv9009/kcu105/system_constr.xdc create mode 100644 projects/adrv9009/kcu105/system_project.tcl create mode 100644 projects/adrv9009/kcu105/system_top.v diff --git a/docs/projects/adrv9009/index.rst b/docs/projects/adrv9009/index.rst index 9f415809348..53b7c1a468e 100644 --- a/docs/projects/adrv9009/index.rst +++ b/docs/projects/adrv9009/index.rst @@ -30,6 +30,9 @@ Supported carriers * - :adi:`ADRV9008/9 ` - :intel:`A10SoC ` - FMCA + * - + - :xilinx:`KCU105` + - FMC_HPC * - - :intel:`S10SoC ` - FMCA @@ -148,26 +151,26 @@ CPU/Memory interconnects addresses The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). -========================= ============ =========== -Instance Zynq ZynqMP -========================= ============ =========== -rx_adrv9009_tpl_core 0x44A0_0000 0x84A0_0000 -tx_adrv9009_tpl_core 0x44A0_4000 0x84A0_4000 -rx_os_adrv9009_tpl_core 0x44A0_8000 0x84A0_8000 -axi_adrv9009_rx_xcvr 0x44A6_0000 0x84A6_0000 -axi_adrv9009_tx_xcvr 0x44A8_0000 0x84A8_0000 -axi_adrv9009_rx_os_xcvr 0x44A5_0000 0x84A5_0000 -axi_adrv9009_tx_jesd 0x44A9_0000 0x84A9_0000 -axi_adrv9009_rx_jesd 0x44AA_0000 0x84AA_0000 -axi_adrv9009_rx_os_jesd 0x44AB_0000 0x84AB_0000 -axi_adrv9009_rx_dma 0x7C40_0000 0x9C40_0000 -axi_adrv9009_tx_dma 0x7C42_0000 0x9C42_0000 -axi_adrv9009_rx_os_dma 0x7C44_0000 0x9C44_0000 -adrv9009_data_offload 0x7c43_0000 0x9C43_0000 -axi_adrv9009_rx_clkgen 0x43C1_0000 0x83C1_0000 -axi_adrv9009_tx_clkgen 0x43C0_0000 0x83C0_0000 -axi_adrv9009_rx_os_clkgen 0x43C2_0000 0x83C2_0000 -========================= ============ =========== +========================= =============== =========== +Instance Zynq/Microblaze ZynqMP +========================= =============== =========== +rx_adrv9009_tpl_core 0x44A0_0000 0x84A0_0000 +tx_adrv9009_tpl_core 0x44A0_4000 0x84A0_4000 +rx_os_adrv9009_tpl_core 0x44A0_8000 0x84A0_8000 +axi_adrv9009_rx_xcvr 0x44A6_0000 0x84A6_0000 +axi_adrv9009_tx_xcvr 0x44A8_0000 0x84A8_0000 +axi_adrv9009_rx_os_xcvr 0x44A5_0000 0x84A5_0000 +axi_adrv9009_tx_jesd 0x44A9_0000 0x84A9_0000 +axi_adrv9009_rx_jesd 0x44AA_0000 0x84AA_0000 +axi_adrv9009_rx_os_jesd 0x44AB_0000 0x84AB_0000 +axi_adrv9009_rx_dma 0x7C40_0000 0x9C40_0000 +axi_adrv9009_tx_dma 0x7C42_0000 0x9C42_0000 +axi_adrv9009_rx_os_dma 0x7C44_0000 0x9C44_0000 +adrv9009_data_offload 0x7c43_0000 0x9C43_0000 +axi_adrv9009_rx_clkgen 0x43C1_0000 0x83C1_0000 +axi_adrv9009_tx_clkgen 0x43C0_0000 0x83C0_0000 +axi_adrv9009_rx_os_clkgen 0x43C2_0000 0x83C2_0000 +========================= =============== =========== SPI connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -261,6 +264,20 @@ axi_adrv9009_tx_dma 12 56 88 108 140 axi_adrv9009_rx_dma 13 57 89 109 141 ======================= === ========== =========== ============ ============= +Microblaze +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +======================= === ========== +Instance name HDL Microblaze +======================= === ========== +axi_adrv9009_rx_os_jesd 8 8 +axi_adrv9009_tx_jesd 7 7 +axi_adrv9009_rx_jesd 15 15 +axi_adrv9009_rx_os_dma 14 14 +axi_adrv9009_tx_dma 13 13 +axi_adrv9009_rx_dma 12 12 +======================= === ========== + Building the HDL project ------------------------------------------------------------------------------- @@ -290,7 +307,7 @@ configure this project, depending on the carrier used. +-------------------+------------------------------------------------------+ | Parameter | Default value of the parameters depending on carrier | +-------------------+------------------------------------------------------+ - | | A10SoC/S10SoC/ZC706/ZCU102 | + | | A10SoC/KCU105/S10SoC/ZC706/ZCU102 | +===================+======================================================+ | RX_JESD_M | 4 | +-------------------+------------------------------------------------------+ diff --git a/projects/adrv9009/common/adrv9009_bd.tcl b/projects/adrv9009/common/adrv9009_bd.tcl index 7bd8c6c0bbc..633eeed6e45 100644 --- a/projects/adrv9009/common/adrv9009_bd.tcl +++ b/projects/adrv9009/common/adrv9009_bd.tcl @@ -476,9 +476,9 @@ if {$CACHE_COHERENCY} { # interrupts -ad_cpu_interrupt ps-8 mb-8 axi_adrv9009_rx_os_jesd/irq -ad_cpu_interrupt ps-9 mb-7 axi_adrv9009_tx_jesd/irq +ad_cpu_interrupt ps-8 mb-8 axi_adrv9009_rx_os_jesd/irq +ad_cpu_interrupt ps-9 mb-7 axi_adrv9009_tx_jesd/irq ad_cpu_interrupt ps-10 mb-15 axi_adrv9009_rx_jesd/irq ad_cpu_interrupt ps-11 mb-14 axi_adrv9009_rx_os_dma/irq -ad_cpu_interrupt ps-12 mb-13- axi_adrv9009_tx_dma/irq +ad_cpu_interrupt ps-12 mb-13 axi_adrv9009_tx_dma/irq ad_cpu_interrupt ps-13 mb-12 axi_adrv9009_rx_dma/irq diff --git a/projects/adrv9009/kcu105/Makefile b/projects/adrv9009/kcu105/Makefile new file mode 100644 index 00000000000..b39f028ac26 --- /dev/null +++ b/projects/adrv9009/kcu105/Makefile @@ -0,0 +1,42 @@ +#################################################################################### +## Copyright (c) 2018 - 2025 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := adrv9009_kcu105 + +M_DEPS += ../common/adrv9009_bd.tcl +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/kcu105/kcu105_system_mig.tcl +M_DEPS += ../../common/kcu105/kcu105_system_lutram_constr.xdc +M_DEPS += ../../common/kcu105/kcu105_system_constr.xdc +M_DEPS += ../../common/kcu105/kcu105_system_bd.tcl +M_DEPS += ../../common/xilinx/data_offload_bd.tcl +M_DEPS += ../../common/xilinx/adi_fir_filter_constr.xdc +M_DEPS += ../../common/xilinx/adi_fir_filter_bd.tcl +M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl +M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl +M_DEPS += ../../../library/common/util_pulse_gen.v +M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_bus_mux.v + +LIB_DEPS += axi_clkgen +LIB_DEPS += axi_dmac +LIB_DEPS += axi_sysid +LIB_DEPS += data_offload +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac +LIB_DEPS += jesd204/axi_jesd204_rx +LIB_DEPS += jesd204/axi_jesd204_tx +LIB_DEPS += jesd204/jesd204_rx +LIB_DEPS += jesd204/jesd204_tx +LIB_DEPS += sysid_rom +LIB_DEPS += util_do_ram +LIB_DEPS += util_hbm +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 +LIB_DEPS += xilinx/axi_adxcvr +LIB_DEPS += xilinx/util_adxcvr + +include ../../scripts/project-xilinx.mk diff --git a/projects/adrv9009/kcu105/system_bd.tcl b/projects/adrv9009/kcu105/system_bd.tcl new file mode 100644 index 00000000000..df27be66ff9 --- /dev/null +++ b/projects/adrv9009/kcu105/system_bd.tcl @@ -0,0 +1,54 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +## Offload attributes +set dac_offload_type 0 ; ## BRAM +set dac_offload_size [expr 1024*1024] ; ## 2 MB +set plddr_offload_axi_data_width 0 + +source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl +source $ad_hdl_dir/projects/common/kcu105/kcu105_system_mig.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 + +set sys_cstring "RX:M=$ad_project_params(RX_JESD_M)\ +L=$ad_project_params(RX_JESD_L)\ +S=$ad_project_params(RX_JESD_S)\ +TX:M=$ad_project_params(TX_JESD_M)\ +L=$ad_project_params(TX_JESD_L)\ +S=$ad_project_params(TX_JESD_S)\ +RX_OS:M=$ad_project_params(RX_OS_JESD_M)\ +L=$ad_project_params(RX_OS_JESD_L)\ +S=$ad_project_params(RX_OS_JESD_S)\ +DAC_OFFLOAD:TYPE=$dac_offload_type\ +SIZE=$dac_offload_size" + +sysid_gen_sys_init_file $sys_cstring + +ad_mem_hp0_interconnect sys_cpu_clk sys_ps7/S_AXI_HP0 +ad_ip_parameter axi_ddr_cntrl CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ 200 + +source ../common/adrv9009_bd.tcl + +ad_ip_parameter axi_adrv9009_tx_dma CONFIG.DMA_DATA_WIDTH_SRC 128 +ad_ip_parameter axi_adrv9009_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 128 +ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.DMA_DATA_WIDTH_DEST 128 +ad_ip_parameter axi_adrv9009_rx_dma CONFIG.FIFO_SIZE 32 +ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.FIFO_SIZE 32 +ad_ip_parameter axi_adrv9009_tx_dma CONFIG.FIFO_SIZE 32 + +ad_ip_parameter util_adrv9009_xcvr CONFIG.QPLL_FBDIV 20 +ad_ip_parameter util_adrv9009_xcvr CONFIG.QPLL_REFCLK_DIV 1 +ad_ip_parameter util_adrv9009_xcvr CONFIG.CPLL_FBDIV 2 +ad_ip_parameter util_adrv9009_xcvr CONFIG.RX_CLK25_DIV 20 +ad_ip_parameter util_adrv9009_xcvr CONFIG.TX_CLK25_DIV 20 +ad_ip_parameter util_adrv9009_xcvr CONFIG.TX_OUT_DIV 1 +ad_ip_parameter util_adrv9009_xcvr CONFIG.CPLL_CFG0 0x67f8 +ad_ip_parameter util_adrv9009_xcvr CONFIG.CPLL_CFG1 0xa4ac +ad_ip_parameter util_adrv9009_xcvr CONFIG.CPLL_CFG2 0x0007 diff --git a/projects/adrv9009/kcu105/system_constr.xdc b/projects/adrv9009/kcu105/system_constr.xdc new file mode 100644 index 00000000000..356f46ffa49 --- /dev/null +++ b/projects/adrv9009/kcu105/system_constr.xdc @@ -0,0 +1,99 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +#adrv9009 + +set_property -dict {PACKAGE_PIN K6} [get_ports ref_clk0_p] ; ## D4 FMC_GBTCLK0_M2C_P MGTREFCLK0P_228 +set_property -dict {PACKAGE_PIN K5} [get_ports ref_clk0_n] ; ## D5 FMC_GBTCLK0_M2C_N MGTREFCLK0N_228 +set_property -dict {PACKAGE_PIN H6} [get_ports ref_clk1_p] ; ## B20 FMC_GBTCLK1_M2C_P MGTREFCLK1P_228 +set_property -dict {PACKAGE_PIN H5} [get_ports ref_clk1_n] ; ## B21 FMC_GBTCLK1_M2C_N MGTREFCLK1N_228 + +set_property -dict {PACKAGE_PIN D2} [get_ports rx_data_p[0]] ; ## A2 FMC_DP1_M2C_P MGTHRXP1_228 +set_property -dict {PACKAGE_PIN D1} [get_ports rx_data_n[0]] ; ## A3 FMC_DP1_M2C_N MGTHRXN1_228 +set_property -dict {PACKAGE_PIN B2} [get_ports rx_data_p[1]] ; ## A6 FMC_DP2_M2C_P MGTHRXP2_228 +set_property -dict {PACKAGE_PIN B1} [get_ports rx_data_n[1]] ; ## A7 FMC_DP2_M2C_N MGTHRXN2_228 +set_property -dict {PACKAGE_PIN E4} [get_ports rx_data_p[2]] ; ## C6 FMC_DP0_M2C_P MGTHRXP0_228 +set_property -dict {PACKAGE_PIN E3} [get_ports rx_data_n[2]] ; ## C7 FMC_DP0_M2C_N MGTHRXN0_228 +set_property -dict {PACKAGE_PIN A4} [get_ports rx_data_p[3]] ; ## A10 FMC_DP3_M2C_P MGTHRXP3_228 +set_property -dict {PACKAGE_PIN A3} [get_ports rx_data_n[3]] ; ## A11 FMC_DP3_M2C_N MGTHRXN3_228 +set_property -dict {PACKAGE_PIN D6} [get_ports tx_data_p[0]] ; ## A22 FMC_DP1_C2M_P MGTHTXP1_228 +set_property -dict {PACKAGE_PIN D5} [get_ports tx_data_n[0]] ; ## A23 FMC_DP1_C2M_N MGTHTXN1_228 +set_property -dict {PACKAGE_PIN C4} [get_ports tx_data_p[1]] ; ## A26 FMC_DP2_C2M_P MGTHTXP2_228 +set_property -dict {PACKAGE_PIN C3} [get_ports tx_data_n[1]] ; ## A27 FMC_DP2_C2M_N MGTHTXN2_228 +set_property -dict {PACKAGE_PIN F6} [get_ports tx_data_p[2]] ; ## C2 FMC_DP0_C2M_P MGTHTXP0_228 +set_property -dict {PACKAGE_PIN F5} [get_ports tx_data_n[2]] ; ## C3 FMC_DP0_C2M_N MGTHTXN0_228 +set_property -dict {PACKAGE_PIN B6} [get_ports tx_data_p[3]] ; ## A30 FMC_DP3_C2M_P MGTHTXP3_228 +set_property -dict {PACKAGE_PIN B5} [get_ports tx_data_n[3]] ; ## A31 FMC_DP3_C2M_N MGTHTXN3_228 + +set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVDS} [get_ports sysref_out_p] ; ## D8 FMC_LA01_CC_P IO_L11P_T1U_N8_GC_66 +set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVDS} [get_ports sysref_out_n] ; ## D9 FMC_LA01_CC_N IO_L11N_T1U_N9_GC_66 +set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports sysref_p] ; ## G6 FMC_LA00_CC_P IO_L13P_T2L_N0_GC_QBC_66 +set_property -dict {PACKAGE_PIN G11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports sysref_n] ; ## G7 FMC_LA00_CC_N IO_L13N_T2L_N1_GC_QBC_66 + +set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVDS} [get_ports rx_sync_p] ; ## G9 FPC_LA03_P IO_L23P_T3U_N8_66 +set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVDS} [get_ports rx_sync_n] ; ## G10 FPC_LA03_N IO_L23N_T3U_N9_66 +set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVDS} [get_ports rx_os_sync_p] ; ## G27 FMC_LA25_P IO_L18P_T2U_N10_AD2P_67 +set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVDS} [get_ports rx_os_sync_n] ; ## G28 FMC_LA25_N IO_L18N_T2U_N11_AD2N_67 +set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H7 FMC_LA02_P IO_L10P_T1U_N6_QBC_AD4P_66 +set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H8 FMC_LA02_N IO_L10N_T1U_N7_QBC_AD4N_66 +set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sync_1_p] ; ## H28 FMC_LA24_P IO_L20P_T3L_N2_AD1P_67 +set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sync_1_n] ; ## H29 FMC_LA24_N IO_L20N_T3L_N3_AD1N_67 + +set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports spi_csn_adrv9009] ; ## D14 FMC_LA09_P IO_L8P_T1L_N2_AD5P_66 +set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVCMOS18} [get_ports spi_csn_ad9528] ; ## D15 FMC_LA09_N IO_L8N_T1L_N3_AD5N_66 +set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## H13 FMC_LA07_P IO_L1P_T0L_N0_DBC_66 +set_property -dict {PACKAGE_PIN E8 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ; ## H14 FMC_LA07_N IO_L1N_T0L_N1_DBC_66 +set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18} [get_ports spi_miso] ; ## G12 FMC_LA08_P IO_L9P_T1L_N4_AD12P_66 + +set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS18} [get_ports ad9528_reset_b] ; ## D26 FMC_LA26_P IO_L22P_T3U_N6_DBC_AD0P_67 +set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVCMOS18} [get_ports ad9528_sysref_req] ; ## D27 FMC_LA26_N IO_L22N_T3U_N7_DBC_AD0N_67 + +set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS18} [get_ports adrv9009_tx1_enable] ; ## D17 FMC_LA13_P IO_L5P_T0U_N8_AD14P_66 +set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports adrv9009_rx1_enable] ; ## D18 FMC_LA13_N IO_L5N_T0U_N9_AD14N_66 +set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS18} [get_ports adrv9009_tx2_enable] ; ## C18 FMC_LA14_P IO_L4P_T0U_N6_DBC_AD7P_66 +set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS18} [get_ports adrv9009_rx2_enable] ; ## C19 FMC_LA14_N IO_L4N_T0U_N7_DBC_AD7N_66 + +set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports adrv9009_test] ; ## H16 FMC_LA11_P IO_L15P_T2L_N4_AD11P_66 +set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18} [get_ports adrv9009_reset_b] ; ## H10 FMC_LA04_P IO_L17P_T2U_N8_AD10P_66 +set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpint] ; ## H11 FMC_LA04_N IO_L17N_T2U_N9_AD10N_66 + +set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_00] ; ## H19 FMC_LA15_P IO_L3P_T0L_N4_AD15P_66 +set_property -dict {PACKAGE_PIN C8 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_01] ; ## H20 FMC_LA15_N IO_L3N_T0L_N5_AD15N_66 +set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_02] ; ## G18 FMC_LA16_P IO_L2P_T0L_N2_66 +set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_03] ; ## G19 FMC_LA16_N IO_L2N_T0L_N3_66 +set_property -dict {PACKAGE_PIN F23 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_04] ; ## H25 FMC_LA21_P IO_L21P_T3L_N4_AD8P_67 +set_property -dict {PACKAGE_PIN F24 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_05] ; ## H26 FMC_LA21_N IO_L21N_T3L_N5_AD8N_67 +set_property -dict {PACKAGE_PIN E22 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_06] ; ## C22 FMC_LA18_CC_P IO_L14P_T2L_N2_GC_67 +set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_07] ; ## C23 FMC_LA18_CC_N IO_L14N_T2L_N3_GC_67 +set_property -dict {PACKAGE_PIN F25 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_08] ; ## G25 FMC_LA22_N IO_L19N_T3L_N1_DBC_AD9N_67 +set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_09] ; ## H22 FMC_LA19_P IO_L16P_T2U_N6_QBC_AD3P_67 +set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_10] ; ## H23 FMC_LA19_N IO_L16N_T2U_N7_QBC_AD3N_67 +set_property -dict {PACKAGE_PIN B24 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_11] ; ## G21 FMC_LA20_P IO_L10P_T1U_N6_QBC_AD4P_67 +set_property -dict {PACKAGE_PIN A24 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_12] ; ## G22 FMC_LA20_N IO_L10N_T1U_N7_QBC_AD4N_67 +set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_13] ; ## G16 FMC_LA12_N IO_L6N_T0U_N11_AD6N_666 +set_property -dict {PACKAGE_PIN E10 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_14] ; ## G15 FMC_LA12_P IO_L6P_T0U_N10_AD6P_66 +set_property -dict {PACKAGE_PIN G24 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_15] ; ## G24 FMC_LA22_P IO_L19P_T3L_N0_DBC_AD9P_67 +set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_16] ; ## C11 FMC_LA06_N IO_L24N_T3U_N11_66 +set_property -dict {PACKAGE_PIN D13 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_17] ; ## C10 FMC_LA06_P IO_L24P_T3U_N10_66 +set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_18] ; ## H17 FMC_LA11_N IO_L15N_T2L_N5_AD11N_6 + +# clocks + +create_clock -name tx_ref_clk -period 4.00 [get_ports ref_clk0_p] +create_clock -name rx_ref_clk -period 4.00 [get_ports ref_clk1_p] + +# For transceiver output clocks use reference clock +# This will help autoderive the clocks correcly +set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[0]] +set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[1]] +set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[0]] +set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[1]] +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[2]] + +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[0]] +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[1]] +set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[0]] +set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[1]] +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[2]] diff --git a/projects/adrv9009/kcu105/system_project.tcl b/projects/adrv9009/kcu105/system_project.tcl new file mode 100644 index 00000000000..c4fe3ed3f22 --- /dev/null +++ b/projects/adrv9009/kcu105/system_project.tcl @@ -0,0 +1,49 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +# get_env_param retrieves parameter value from the environment if exists, +# other case use the default value +# +# Use over-writable parameters from the environment. +# +# e.g. +# make TX_JESD_M=4 TX_JESD_L=4 RX_JESD_M=4 RX_JESD_L=2 RX_OS_JESD_M=2 RX_OS_JESD_L=2 + +# Parameter description: +# [TX/RX/RX_OS]_JESD_M : Number of converters per link +# [TX/RX/RX_OS]_JESD_L : Number of lanes per link +# [TX/RX/RX_OS]_JESD_S : Number of samples per frame +# [TX/RX/RX_OS]_JESD_NP : Number of bits per sample + +adi_project adrv9009_kcu105 0 [list \ + TX_JESD_M [get_env_param TX_JESD_M 4 ] \ + TX_JESD_L [get_env_param TX_JESD_L 4 ] \ + TX_JESD_S [get_env_param TX_JESD_S 1 ] \ + RX_JESD_M [get_env_param RX_JESD_M 4 ] \ + RX_JESD_L [get_env_param RX_JESD_L 2 ] \ + RX_JESD_S [get_env_param RX_JESD_S 1 ] \ + RX_OS_JESD_M [get_env_param RX_OS_JESD_M 2 ] \ + RX_OS_JESD_L [get_env_param RX_OS_JESD_L 2 ] \ + RX_OS_JESD_S [get_env_param RX_OS_JESD_S 1 ] \ +] + +adi_project_files adrv9009_kcu105 [list \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/common/ad_bus_mux.v" \ + "$ad_hdl_dir/library/common/util_pulse_gen.v" \ + "$ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc" \ + "$ad_hdl_dir/projects/common/kcu105/kcu105_system_lutram_constr.xdc" ] + +## To improve timing of the BRAM buffers +set_property strategy Performance_RefinePlacement [get_runs impl_1] +set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE ExploreWithAggressiveHoldFix [get_runs impl_1] + +adi_project_run adrv9009_kcu105 diff --git a/projects/adrv9009/kcu105/system_top.v b/projects/adrv9009/kcu105/system_top.v new file mode 100644 index 00000000000..42972cc6b98 --- /dev/null +++ b/projects/adrv9009/kcu105/system_top.v @@ -0,0 +1,327 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + input sys_rst, + input sys_clk_p, + input sys_clk_n, + + input uart_sin, + output uart_sout, + + output ddr4_act_n, + output [16:0] ddr4_addr, + output [ 1:0] ddr4_ba, + output ddr4_bg, + output ddr4_ck_p, + output ddr4_ck_n, + output ddr4_cke, + output ddr4_cs_n, + inout [ 7:0] ddr4_dm_n, + inout [63:0] ddr4_dq, + inout [ 7:0] ddr4_dqs_p, + inout [ 7:0] ddr4_dqs_n, + output ddr4_odt, + output ddr4_reset_n, + + output mdio_mdc, + inout mdio_mdio, + input phy_clk_p, + input phy_clk_n, + output phy_rst_n, + input phy_rx_p, + input phy_rx_n, + output phy_tx_p, + output phy_tx_n, + + output fan_pwm, + + inout [16:0] gpio_bd, + + inout iic_scl, + inout iic_sda, + + input ref_clk0_p, + input ref_clk0_n, + input ref_clk1_p, + input ref_clk1_n, + input [ 3:0] rx_data_p, + input [ 3:0] rx_data_n, + output [ 3:0] tx_data_p, + output [ 3:0] tx_data_n, + output rx_sync_p, + output rx_sync_n, + output rx_os_sync_p, + output rx_os_sync_n, + input tx_sync_p, + input tx_sync_n, + input tx_sync_1_p, + input tx_sync_1_n, + input sysref_p, + input sysref_n, + + output sysref_out_p, + output sysref_out_n, + + output spi_csn_ad9528, + output spi_csn_adrv9009, + output spi_clk, + output spi_mosi, + input spi_miso, + + inout ad9528_reset_b, + inout ad9528_sysref_req, + inout adrv9009_tx1_enable, + inout adrv9009_tx2_enable, + inout adrv9009_rx1_enable, + inout adrv9009_rx2_enable, + inout adrv9009_test, + inout adrv9009_reset_b, + inout adrv9009_gpint, + + inout adrv9009_gpio_00, + inout adrv9009_gpio_01, + inout adrv9009_gpio_02, + inout adrv9009_gpio_03, + inout adrv9009_gpio_04, + inout adrv9009_gpio_05, + inout adrv9009_gpio_06, + inout adrv9009_gpio_07, + inout adrv9009_gpio_15, + inout adrv9009_gpio_08, + inout adrv9009_gpio_09, + inout adrv9009_gpio_10, + inout adrv9009_gpio_11, + inout adrv9009_gpio_12, + inout adrv9009_gpio_14, + inout adrv9009_gpio_13, + inout adrv9009_gpio_17, + inout adrv9009_gpio_16, + inout adrv9009_gpio_18 +); + + // internal signals + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + wire [ 2:0] spi_csn; + wire ref_clk0; + wire ref_clk1; + wire rx_sync; + wire rx_os_sync; + wire tx_sync; + wire sysref; + + assign gpio_i[63:60] = gpio_o[63:60]; + assign gpio_i[31:17] = gpio_o[31:17]; + + assign sysref_out = 0; + assign fan_pwm = 1'b1; + + // instantiations + + IBUFDS_GTE3 i_ibufds_rx_ref_clk ( + .CEB (1'd0), + .I (ref_clk0_p), + .IB (ref_clk0_n), + .O (ref_clk0), + .ODIV2 ()); + + IBUFDS_GTE3 i_ibufds_ref_clk1 ( + .CEB (1'd0), + .I (ref_clk1_p), + .IB (ref_clk1_n), + .O (ref_clk1), + .ODIV2 (ref_clk1_odiv2)); + + BUFG_GT i_bufg_ref_clk ( + .I (ref_clk1_odiv2), + .O (ref_clk1_bufg)); + + OBUFDS i_obufds_rx_sync ( + .I (rx_sync), + .O (rx_sync_p), + .OB (rx_sync_n)); + + OBUFDS i_obufds_rx_os_sync ( + .I (rx_os_sync), + .O (rx_os_sync_p), + .OB (rx_os_sync_n)); + + OBUFDS i_obufds_sysref_out ( + .I (sysref_out), + .O (sysref_out_p), + .OB (sysref_out_n)); + + IBUFDS i_ibufds_tx_sync ( + .I (tx_sync_p), + .IB (tx_sync_n), + .O (tx_sync)); + + IBUFDS i_ibufds_tx_sync_1 ( + .I (tx_sync_1_p), + .IB (tx_sync_1_n), + .O (tx_sync_1)); + + IBUFDS i_ibufds_sysref ( + .I (sysref_p), + .IB (sysref_n), + .O (sysref)); + + ad_iobuf #( + .DATA_WIDTH(28) + ) i_iobuf ( + .dio_t ({gpio_t[59:32]}), + .dio_i ({gpio_o[59:32]}), + .dio_o ({gpio_i[59:32]}), + .dio_p ({ ad9528_reset_b, // 59 + ad9528_sysref_req, // 58 + adrv9009_tx1_enable, // 57 + adrv9009_tx2_enable, // 56 + adrv9009_rx1_enable, // 55 + adrv9009_rx2_enable, // 54 + adrv9009_test, // 53 + adrv9009_reset_b, // 52 + adrv9009_gpint, // 51 + adrv9009_gpio_00, // 50 + adrv9009_gpio_01, // 49 + adrv9009_gpio_02, // 48 + adrv9009_gpio_03, // 47 + adrv9009_gpio_04, // 46 + adrv9009_gpio_05, // 45 + adrv9009_gpio_06, // 44 + adrv9009_gpio_07, // 43 + adrv9009_gpio_15, // 42 + adrv9009_gpio_08, // 41 + adrv9009_gpio_09, // 40 + adrv9009_gpio_10, // 39 + adrv9009_gpio_11, // 38 + adrv9009_gpio_12, // 37 + adrv9009_gpio_14, // 36 + adrv9009_gpio_13, // 35 + adrv9009_gpio_17, // 34 + adrv9009_gpio_16, // 33 + adrv9009_gpio_18})); // 32 + + ad_iobuf #( + .DATA_WIDTH(17) + ) i_iobuf_bd ( + .dio_t (gpio_t[16:0]), + .dio_i (gpio_o[16:0]), + .dio_o (gpio_i[16:0]), + .dio_p (gpio_bd)); + + assign spi_csn_ad9528 = spi_csn[0]; + assign spi_csn_adrv9009 = spi_csn[1]; + + system_wrapper i_system_wrapper ( + .c0_ddr4_act_n (ddr4_act_n), + .c0_ddr4_adr (ddr4_addr), + .c0_ddr4_ba (ddr4_ba), + .c0_ddr4_bg (ddr4_bg), + .c0_ddr4_ck_c (ddr4_ck_n), + .c0_ddr4_ck_t (ddr4_ck_p), + .c0_ddr4_cke (ddr4_cke), + .c0_ddr4_cs_n (ddr4_cs_n), + .c0_ddr4_dm_n (ddr4_dm_n), + .c0_ddr4_dq (ddr4_dq), + .c0_ddr4_dqs_c (ddr4_dqs_n), + .c0_ddr4_dqs_t (ddr4_dqs_p), + .c0_ddr4_odt (ddr4_odt), + .c0_ddr4_reset_n (ddr4_reset_n), + .gpio0_i (gpio_i[31: 0]), + .gpio0_o (gpio_o[31: 0]), + .gpio0_t (gpio_t[31: 0]), + .gpio1_i (gpio_i[63:32]), + .gpio1_o (gpio_o[63:32]), + .gpio1_t (gpio_t[63:32]), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .mdio_mdc (mdio_mdc), + .mdio_mdio_io (mdio_mdio), + .phy_clk_clk_n (phy_clk_n), + .phy_clk_clk_p (phy_clk_p), + .phy_rst_n (phy_rst_n), + .phy_sd (1'b1), + .sgmii_rxn (phy_rx_n), + .sgmii_rxp (phy_rx_p), + .sgmii_txn (phy_tx_n), + .sgmii_txp (phy_tx_p), + .sys_clk_clk_n (sys_clk_n), + .sys_clk_clk_p (sys_clk_p), + .sys_rst (sys_rst), + .uart_sin (uart_sin), + .uart_sout (uart_sout), + .adc_fir_filter_active (gpio_o[61]), + .dac_fir_filter_active (gpio_o[62]), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_data_2_n (rx_data_n[2]), + .rx_data_2_p (rx_data_p[2]), + .rx_data_3_n (rx_data_n[3]), + .rx_data_3_p (rx_data_p[3]), + .rx_ref_clk_0 (ref_clk1), + .rx_ref_clk_2 (ref_clk1), + .rx_sync_0 (rx_sync), + .rx_sync_2 (rx_os_sync), + .rx_sysref_0 (sysref), + .rx_sysref_2 (sysref), + .spi_clk_i (spi_clk), + .spi_clk_o (spi_clk), + .spi_csn_i (spi_csn), + .spi_csn_o (spi_csn), + .spi_sdi_i (spi_miso), + .spi_sdo_i (spi_mosi), + .spi_sdo_o (spi_mosi), + .tx_data_0_n (tx_data_n[0]), + .tx_data_0_p (tx_data_p[0]), + .tx_data_1_n (tx_data_n[1]), + .tx_data_1_p (tx_data_p[1]), + .tx_data_2_n (tx_data_n[2]), + .tx_data_2_p (tx_data_p[2]), + .tx_data_3_n (tx_data_n[3]), + .tx_data_3_p (tx_data_p[3]), + .tx_ref_clk_0 (ref_clk1), + .tx_sync_0 (tx_sync), + .tx_sysref_0 (sysref), + .ref_clk (ref_clk1_bufg)); + +endmodule