From e2e70d9804f7a796d9ca7ed28582fa3b56337646 Mon Sep 17 00:00:00 2001 From: Ionut Podgoreanu Date: Thu, 5 Dec 2024 16:27:43 +0200 Subject: [PATCH 1/2] adrv9026: Replace dacfifo with data_offload Signed-off-by: Ionut Podgoreanu --- projects/adrv9026/common/adrv9026_bd.tcl | 42 +++++++++++++----------- projects/adrv9026/vcu118/Makefile | 9 +++-- projects/adrv9026/vcu118/system_bd.tcl | 8 ++--- projects/adrv9026/vcu118/system_top.v | 3 +- projects/adrv9026/zcu102/Makefile | 9 +++-- projects/adrv9026/zcu102/system_bd.tcl | 10 +++--- projects/adrv9026/zcu102/system_top.v | 5 ++- 7 files changed, 45 insertions(+), 41 deletions(-) diff --git a/projects/adrv9026/common/adrv9026_bd.tcl b/projects/adrv9026/common/adrv9026_bd.tcl index d81f556827c..f43ec1b01be 100644 --- a/projects/adrv9026/common/adrv9026_bd.tcl +++ b/projects/adrv9026/common/adrv9026_bd.tcl @@ -32,7 +32,7 @@ set RX_SAMPLE_WIDTH 16 ; # N/NP set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 32 / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] ; # L * 32 / (M * N) -set dac_fifo_name axi_adrv9026_dacfifo +set dac_offload_name adrv9026_data_offload set dac_data_width [expr 32*$TX_NUM_OF_LANES] set dac_dma_data_width 128 @@ -47,10 +47,10 @@ if {$JESD_MODE == "8B10B"} { } source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl +source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl # adrv9026 -create_bd_port -dir I dac_fifo_bypass create_bd_port -dir I core_clk # dac peripherals @@ -90,7 +90,15 @@ ad_ip_parameter axi_adrv9026_tx_dma CONFIG.DMA_DATA_WIDTH_SRC 128 ad_ip_parameter axi_adrv9026_tx_dma CONFIG.FIFO_SIZE 32 ad_ip_parameter axi_adrv9026_tx_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY -ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width +ad_data_offload_create $dac_offload_name \ + 1 \ + $dac_offload_type \ + $dac_offload_size \ + $dac_dma_data_width \ + $dac_data_width + +ad_ip_parameter $dac_offload_name/i_data_offload CONFIG.SYNC_EXT_ADD_INTERNAL_CDC 0 +ad_connect $dac_offload_name/sync_ext GND # adc peripherals @@ -191,23 +199,16 @@ for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} { } ad_connect tx_adrv9026_tpl_core/dac_valid_0 util_adrv9026_tx_upack/fifo_rd_en -ad_connect core_clk axi_adrv9026_dacfifo/dac_clk -ad_connect core_clk_rstgen/peripheral_reset axi_adrv9026_dacfifo/dac_rst - -ad_connect util_adrv9026_tx_upack/s_axis_valid VCC -ad_connect util_adrv9026_tx_upack/s_axis_ready axi_adrv9026_dacfifo/dac_valid -ad_connect util_adrv9026_tx_upack/s_axis_data axi_adrv9026_dacfifo/dac_data - -ad_connect core_clk axi_adrv9026_dacfifo/dma_clk -ad_connect core_clk_rstgen/peripheral_reset axi_adrv9026_dacfifo/dma_rst -ad_connect core_clk axi_adrv9026_tx_dma/m_axis_aclk -ad_connect axi_adrv9026_dacfifo/dma_valid axi_adrv9026_tx_dma/m_axis_valid -ad_connect axi_adrv9026_dacfifo/dma_data axi_adrv9026_tx_dma/m_axis_data -ad_connect axi_adrv9026_dacfifo/dma_ready axi_adrv9026_tx_dma/m_axis_ready -ad_connect axi_adrv9026_dacfifo/dma_xfer_req axi_adrv9026_tx_dma/m_axis_xfer_req -ad_connect axi_adrv9026_dacfifo/dma_xfer_last axi_adrv9026_tx_dma/m_axis_last -ad_connect axi_adrv9026_dacfifo/dac_dunf tx_adrv9026_tpl_core/dac_dunf -ad_connect axi_adrv9026_dacfifo/bypass dac_fifo_bypass +ad_connect core_clk $dac_offload_name/m_axis_aclk +ad_connect core_clk_rstgen/peripheral_aresetn $dac_offload_name/m_axis_aresetn +ad_connect util_adrv9026_tx_upack/s_axis $dac_offload_name/m_axis + +ad_connect core_clk $dac_offload_name/s_axis_aclk +ad_connect core_clk_rstgen/peripheral_aresetn $dac_offload_name/s_axis_aresetn +ad_connect core_clk axi_adrv9026_tx_dma/m_axis_aclk +ad_connect $dac_offload_name/s_axis axi_adrv9026_tx_dma/m_axis +ad_connect $dac_offload_name/init_req axi_adrv9026_tx_dma/m_axis_xfer_req +ad_connect tx_adrv9026_tpl_core/dac_dunf util_adrv9026_tx_upack/fifo_rd_underflow ad_connect core_clk_rstgen/peripheral_aresetn axi_adrv9026_tx_dma/m_src_axi_aresetn # connections (adc) @@ -240,6 +241,7 @@ ad_cpu_interconnect 0x44A60000 axi_adrv9026_rx_xcvr ad_cpu_interconnect 0x44A80000 axi_adrv9026_tx_xcvr ad_cpu_interconnect 0x44A90000 axi_adrv9026_tx_jesd ad_cpu_interconnect 0x7c420000 axi_adrv9026_tx_dma +ad_cpu_interconnect 0x7c430000 $dac_offload_name ad_cpu_interconnect 0x44AA0000 axi_adrv9026_rx_jesd ad_cpu_interconnect 0x7c400000 axi_adrv9026_rx_dma diff --git a/projects/adrv9026/vcu118/Makefile b/projects/adrv9026/vcu118/Makefile index 635623623e8..76123e6f91b 100644 --- a/projects/adrv9026/vcu118/Makefile +++ b/projects/adrv9026/vcu118/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2018 - 2024 Analog Devices, Inc. +## Copyright (c) 2018 - 2025 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### @@ -10,12 +10,14 @@ M_DEPS += ../common/adrv9026_bd.tcl M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/vcu118/vcu118_system_constr.xdc M_DEPS += ../../common/vcu118/vcu118_system_bd.tcl -M_DEPS += ../../common/xilinx/dacfifo_bd.tcl +M_DEPS += ../../common/xilinx/data_offload_bd.tcl +M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl M_DEPS += ../../../library/common/ad_iobuf.v LIB_DEPS += axi_dmac LIB_DEPS += axi_sysid +LIB_DEPS += data_offload LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac LIB_DEPS += jesd204/axi_jesd204_rx @@ -23,7 +25,8 @@ LIB_DEPS += jesd204/axi_jesd204_tx LIB_DEPS += jesd204/jesd204_rx LIB_DEPS += jesd204/jesd204_tx LIB_DEPS += sysid_rom -LIB_DEPS += util_dacfifo +LIB_DEPS += util_do_ram +LIB_DEPS += util_hbm LIB_DEPS += util_pack/util_cpack2 LIB_DEPS += util_pack/util_upack2 LIB_DEPS += xilinx/axi_adxcvr diff --git a/projects/adrv9026/vcu118/system_bd.tcl b/projects/adrv9026/vcu118/system_bd.tcl index c257570bbe3..620f2b6a564 100644 --- a/projects/adrv9026/vcu118/system_bd.tcl +++ b/projects/adrv9026/vcu118/system_bd.tcl @@ -1,13 +1,13 @@ ############################################################################### -## Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### -## FIFO depth is 18Mb - 1M samples -set dac_fifo_address_width 17 +## Offload attributes +set dac_offload_type 0 ; ## BRAM +set dac_offload_size [expr 2*1024*1024] ; ## 2 MB source $ad_hdl_dir/projects/common/vcu118/vcu118_system_bd.tcl -source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl source $ad_hdl_dir/projects/scripts/adi_pd.tcl set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt; diff --git a/projects/adrv9026/vcu118/system_top.v b/projects/adrv9026/vcu118/system_top.v index b758bf37fc1..c81401e73ca 100644 --- a/projects/adrv9026/vcu118/system_top.v +++ b/projects/adrv9026/vcu118/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -303,7 +303,6 @@ module system_top ( .spi_sdo_i (spi_mosi), .spi_sdo_o (spi_mosi), - .dac_fifo_bypass(gpio_o[63]), .gpio0_i (gpio_i[31:0]), .gpio0_o (gpio_o[31:0]), .gpio0_t (gpio_t[31:0]), diff --git a/projects/adrv9026/zcu102/Makefile b/projects/adrv9026/zcu102/Makefile index dae7c572c96..cfb4dab493c 100644 --- a/projects/adrv9026/zcu102/Makefile +++ b/projects/adrv9026/zcu102/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2018 - 2024 Analog Devices, Inc. +## Copyright (c) 2018 - 2025 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### @@ -10,12 +10,14 @@ M_DEPS += ../common/adrv9026_bd.tcl M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl -M_DEPS += ../../common/xilinx/dacfifo_bd.tcl +M_DEPS += ../../common/xilinx/data_offload_bd.tcl +M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl M_DEPS += ../../../library/common/ad_iobuf.v LIB_DEPS += axi_dmac LIB_DEPS += axi_sysid +LIB_DEPS += data_offload LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac LIB_DEPS += jesd204/axi_jesd204_rx @@ -23,7 +25,8 @@ LIB_DEPS += jesd204/axi_jesd204_tx LIB_DEPS += jesd204/jesd204_rx LIB_DEPS += jesd204/jesd204_tx LIB_DEPS += sysid_rom -LIB_DEPS += util_dacfifo +LIB_DEPS += util_do_ram +LIB_DEPS += util_hbm LIB_DEPS += util_pack/util_cpack2 LIB_DEPS += util_pack/util_upack2 LIB_DEPS += xilinx/axi_adxcvr diff --git a/projects/adrv9026/zcu102/system_bd.tcl b/projects/adrv9026/zcu102/system_bd.tcl index 883180d07af..b28fa83226e 100644 --- a/projects/adrv9026/zcu102/system_bd.tcl +++ b/projects/adrv9026/zcu102/system_bd.tcl @@ -1,15 +1,13 @@ ############################################################################### -## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2023-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### -## FIFO depth is 18Mb - 1M samples -set dac_fifo_address_width 17 - -## NOTE: With this configuration the #36Kb BRAM utilization is at ~57% +## Offload attributes +set dac_offload_type 0 ; ## BRAM +set dac_offload_size [expr 2*1024*1024] ; ## 2 MB source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl -source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl source $ad_hdl_dir/projects/scripts/adi_pd.tcl #system ID diff --git a/projects/adrv9026/zcu102/system_top.v b/projects/adrv9026/zcu102/system_top.v index 4f58613a36f..e907879d83e 100644 --- a/projects/adrv9026/zcu102/system_top.v +++ b/projects/adrv9026/zcu102/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023-2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -221,7 +221,6 @@ module system_top ( assign spi_csn_ad9528 = spi_csn[1]; system_wrapper i_system_wrapper ( - .dac_fifo_bypass (gpio_o[69]), .gpio_i (gpio_i), .gpio_o (gpio_o), .gpio_t (gpio_t), @@ -257,4 +256,4 @@ module system_top ( .tx_sync_0 (tx_sync), .tx_sysref_0 (sysref)); -endmodule \ No newline at end of file +endmodule From 5406fa36b5a4b4e2281f9a7cece656bfa24d12ca Mon Sep 17 00:00:00 2001 From: Ionut Podgoreanu Date: Mon, 24 Mar 2025 14:21:25 +0200 Subject: [PATCH 2/2] docs: adrv9026: Update for Data Offload support Signed-off-by: Ionut Podgoreanu --- .../adrv9026/adrv9026_zcu102_jesd204b.svg | 2183 ++++++++++++++++- docs/projects/adrv9026/index.rst | 28 +- 2 files changed, 2196 insertions(+), 15 deletions(-) diff --git a/docs/projects/adrv9026/adrv9026_zcu102_jesd204b.svg b/docs/projects/adrv9026/adrv9026_zcu102_jesd204b.svg index aa85cc4ff8c..60534884d02 100644 --- a/docs/projects/adrv9026/adrv9026_zcu102_jesd204b.svg +++ b/docs/projects/adrv9026/adrv9026_zcu102_jesd204b.svg @@ -1,4 +1,2181 @@ - + - -
FMC CONNECTOR
XCVR
TX LaneRate = 10 Gbps
4x
10 Gbps
REFCLK0/1
RX JESD LINK
4x 32 bits @250MHz
RX JESD TPL
1x 128 bits @250 MHz
UTIL_CPACK
GlobalClock = LaneRate/40 = 250 MHz
SystemClk = 100MHz
AXI DMA
MEMORY INTERCONNECT
ZCU102
GLBCLK
SYSREF
Zynq
4x
10 Gbps
RX LaneRate = 10 Gbps
8x 16 bits @250MHz
1x 128 bits @250 MHz
AXI DMA
UTIL_UPACK
UTIL_DACFIFO
TX JESD TPL
TX JESD LINK
DmaClk = 250MHz
1x 128 bits @250 MHz
1x 128 bits @250 MHz
4x 32 bits @250MHz
1x 128 bits @250 MHz
8x 16 bits @250MHz
 \ No newline at end of file + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + FMC CONNECTOR + + + + + + + + + + + + + + + + + + + + XCVR + + + + + + + + + + + + + + + + + + TX LaneRate = 10 Gbps + + + + + + + + + + + + + + + + + + + 4x + + 10 Gbps + + + + + + + + + + + + + + + + + + + + + + + + REFCLK0/1 + + + + + + + + + + + + + + + + + + + + RX JESD LINK + + + + + + + + + + + + + + + + + + + + + 4x 32 bits @250MHz + + + + + + + + + + + + + + + + + + + + + RX JESD TPL + + + + + + + + + + + + + + + + + + + + + + 1x 128 bits @250 MHz + + + + + + + + + + + + + + + + + + + + + UTIL_CPACK + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GlobalClock = LaneRate/40 = 250 MHz + + + + + + + + + + + + + + + + + + + SystemClk = 100MHz + + + + + + + + + + + + + + + + + + + + + AXI DMA + + + + + + + + + + + + + + + + + + + + + + + + MEMORY INTERCONNECT + + + + + + + + + + + + + + + + + + + ZCU102 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GLBCLK + + + + + + + + + + + + + + + + + + + + + SYSREF + + + + + + + + + + + + + + + + + + Zynq + + + + + + + + + + + + + + + + + + + 4x + + 10 Gbps + + + + + + + + + + + + + + + + + + + + + RX LaneRate = 10 Gbps + + + + + + + + + + + + + + + + + + 8x 16 bits @250MHz + + + + + + + + + + + + + + + + + + + 1x 128 bits @250 MHz + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI DMA + + + + + + + + + + + + + + + + + UTIL_UPACK + + + + + + + + + + + + + + + + + + + + TX JESD TPL + + + + + + + + + + + + + + + + + TX JESD LINK + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + DmaClk = 250MHz + + + + + + + + + + + + + + + + + + + 1x 128 bits @250 MHz + + + + + + + + + + + + + + + + + + + 1x 128 bits @250 MHz + + + + + + + + + + + + + + + + + + 4x 32 bits @250MHz + + + + + + + + + + + + + + + + + + + 1x 128 bits @250 MHz + + + + + + + + + + + + + + + + + + 8x 16 bits @250MHz + + + + + + + + + DATA_OFFLOAD + 2MB + + diff --git a/docs/projects/adrv9026/index.rst b/docs/projects/adrv9026/index.rst index 8f12d3cfea1..55bba246f4a 100644 --- a/docs/projects/adrv9026/index.rst +++ b/docs/projects/adrv9026/index.rst @@ -119,18 +119,19 @@ CPU/Memory interconnects addresses The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). -==================== =============== =========== -Instance Zynq/Microblaze ZynqMP -==================== =============== =========== -rx_adrv9026_tpl_core 0x44A0_0000 0x84A0_0000 -tx_adrv9026_tpl_core 0x44A0_4000 0x84A0_4000 -axi_adrv9026_rx_xcvr 0x44A6_0000 0x84A6_0000 -axi_adrv9026_tx_xcvr 0x44A8_0000 0x84A8_0000 -axi_adrv9026_tx_jesd 0x44A9_0000 0x84A9_0000 -axi_adrv9026_rx_jesd 0x44AA_0000 0x84AA_0000 -axi_adrv9026_rx_dma 0x7C40_0000 0x9C40_0000 -axi_adrv9026_tx_dma 0x7C42_0000 0x9C42_0000 -==================== =============== =========== +===================== =============== =========== +Instance Zynq/Microblaze ZynqMP +===================== =============== =========== +rx_adrv9026_tpl_core 0x44A0_0000 0x84A0_0000 +tx_adrv9026_tpl_core 0x44A0_4000 0x84A0_4000 +axi_adrv9026_rx_xcvr 0x44A6_0000 0x84A6_0000 +axi_adrv9026_tx_xcvr 0x44A8_0000 0x84A8_0000 +axi_adrv9026_tx_jesd 0x44A9_0000 0x84A9_0000 +axi_adrv9026_rx_jesd 0x44AA_0000 0x84AA_0000 +axi_adrv9026_rx_dma 0x7C40_0000 0x9C40_0000 +axi_adrv9026_tx_dma 0x7C42_0000 0x9C42_0000 +adrv9026_data_offload 0x7C43_0000 0x9C43_0000 +===================== =============== =========== SPI connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -490,6 +491,9 @@ HDL related * - AXI_DMAC - :git-hdl:`library/axi_dmac` - :ref:`axi_dmac` + * - DATA_OFFLOAD + - :git-hdl:`library/data_offload` + - :ref:`data_offload` * - AXI_SYSID - :git-hdl:`library/axi_sysid` - :ref:`axi_sysid`