From b4f132f9730af8a30a37ae54b1939b650855f91b Mon Sep 17 00:00:00 2001 From: sarpadi Date: Mon, 31 Mar 2025 14:37:21 +0300 Subject: [PATCH] sidekiqz2: Remove project --- projects/sidekiqz2/Makefile | 24 ---- projects/sidekiqz2/Readme.md | 10 -- projects/sidekiqz2/system_bd.tcl | 13 --- projects/sidekiqz2/system_constr.xdc | 77 ------------- projects/sidekiqz2/system_project.tcl | 18 --- projects/sidekiqz2/system_top.v | 157 -------------------------- 6 files changed, 299 deletions(-) delete mode 100755 projects/sidekiqz2/Makefile delete mode 100755 projects/sidekiqz2/Readme.md delete mode 100755 projects/sidekiqz2/system_bd.tcl delete mode 100755 projects/sidekiqz2/system_constr.xdc delete mode 100755 projects/sidekiqz2/system_project.tcl delete mode 100755 projects/sidekiqz2/system_top.v diff --git a/projects/sidekiqz2/Makefile b/projects/sidekiqz2/Makefile deleted file mode 100755 index 17dd7ec34c7..00000000000 --- a/projects/sidekiqz2/Makefile +++ /dev/null @@ -1,24 +0,0 @@ -#################################################################################### -## Copyright (c) 2018 - 2024 Analog Devices, Inc. -### SPDX short identifier: BSD-1-Clause -## Auto-generated, do not modify! -#################################################################################### - -PROJECT_NAME := sidekiqz2 - -M_DEPS += ../pluto/system_bd.tcl -M_DEPS += ../common/xilinx/adi_fir_filter_constr.xdc -M_DEPS += ../common/xilinx/adi_fir_filter_bd.tcl -M_DEPS += ../../library/util_cdc/sync_bits.v -M_DEPS += ../../library/common/util_pulse_gen.v -M_DEPS += ../../library/common/ad_iobuf.v -M_DEPS += ../../library/common/ad_bus_mux.v -M_DEPS += ../../library/axi_tdd/scripts/axi_tdd.tcl - -LIB_DEPS += axi_ad9361 -LIB_DEPS += axi_dmac -LIB_DEPS += axi_tdd -LIB_DEPS += util_pack/util_cpack2 -LIB_DEPS += util_pack/util_upack2 - -include ../scripts/project-xilinx.mk diff --git a/projects/sidekiqz2/Readme.md b/projects/sidekiqz2/Readme.md deleted file mode 100755 index 66e12e17d26..00000000000 --- a/projects/sidekiqz2/Readme.md +++ /dev/null @@ -1,10 +0,0 @@ -# SIDEKIQ-Z2 HDL Project - -This project is a port of ADALM-PLUTO on Sidekiq-Z2 hardware - -Here are some pointers to help you: - * [Board Product Page](https://epiqsolutions.com/rf-transceiver/sidekiq-z2/) - * Parts : [RF Agile Transceiver](https://www.analog.com/ad9364) - * Project Doc: https://wiki.analog.com/university/tools/pluto - * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/reference_hdl - * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-transceiver/ad9361 diff --git a/projects/sidekiqz2/system_bd.tcl b/projects/sidekiqz2/system_bd.tcl deleted file mode 100755 index f6066de5644..00000000000 --- a/projects/sidekiqz2/system_bd.tcl +++ /dev/null @@ -1,13 +0,0 @@ -############################################################################### -## Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -# create board design -source ../pluto/system_bd.tcl - -ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_IO 19 - -set_property LEFT 18 [get_bd_ports /gpio_i] -set_property LEFT 18 [get_bd_ports /gpio_o] -set_property LEFT 18 [get_bd_ports /gpio_t] diff --git a/projects/sidekiqz2/system_constr.xdc b/projects/sidekiqz2/system_constr.xdc deleted file mode 100755 index 4fdeb0bcd55..00000000000 --- a/projects/sidekiqz2/system_constr.xdc +++ /dev/null @@ -1,77 +0,0 @@ -############################################################################### -## Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -# constraints -# ad9361 (SWAP == 0x1) - -set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVCMOS18 } [get_ports rx_clk_in] -set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS18 } [get_ports rx_frame_in] -set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[0]] -set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[1]] -set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[2]] -set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[3]] -set_property -dict {PACKAGE_PIN P13 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[4]] -set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[5]] -set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[6]] -set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[7]] -set_property -dict {PACKAGE_PIN P10 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[8]] -set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[9]] -set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[10]] -set_property -dict {PACKAGE_PIN P9 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[11]] - -set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports tx_clk_out] -set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports tx_frame_out] -set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports tx_data_out[0]] -set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports tx_data_out[1]] -set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports tx_data_out[2]] -set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports tx_data_out[3]] -set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports tx_data_out[4]] -set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports tx_data_out[5]] -set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports tx_data_out[6]] -set_property -dict {PACKAGE_PIN M12 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports tx_data_out[7]] -set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports tx_data_out[8]] -set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports tx_data_out[9]] -set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports tx_data_out[10]] -set_property -dict {PACKAGE_PIN M9 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports tx_data_out[11]] - -set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]] -set_property -dict {PACKAGE_PIN G11 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]] -set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVCMOS18} [get_ports gpio_status[2]] -set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS18} [get_ports gpio_status[3]] -set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS18} [get_ports gpio_status[4]] -set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVCMOS18} [get_ports gpio_status[5]] -set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports gpio_status[6]] -set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports gpio_status[7]] - -set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]] -set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]] -set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]] -set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]] - -set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc] - -set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS18} [get_ports enable] -set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports txnrx] - -set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports iic_scl] -set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports iic_sda] - -set_property -dict {PACKAGE_PIN P8 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports spi_csn] -set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports spi_clk] -set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports spi_mosi] -set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports spi_miso] - -set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18} [get_ports clk_out] - -create_clock -name rx_clk -period 16.27 [get_ports rx_clk_in] - -set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports pl_gpio[1]] -set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS18} [get_ports pl_gpio[2]] -set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS18} [get_ports pl_gpio[3]] -set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS18} [get_ports pl_gpio[4]] - -set_false_path -from [get_pins {i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/up_adc_gpio_out_int_reg[0]*/C}] -set_false_path -from [get_pins {i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/up_dac_gpio_out_int_reg[0]*/C}] - diff --git a/projects/sidekiqz2/system_project.tcl b/projects/sidekiqz2/system_project.tcl deleted file mode 100755 index 5373f8e171f..00000000000 --- a/projects/sidekiqz2/system_project.tcl +++ /dev/null @@ -1,18 +0,0 @@ -############################################################################### -## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -source ../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -adi_project_create sidekiqz2 0 {} "xc7z010clg225-1" - -adi_project_files sidekiqz2 [list \ - "system_top.v" \ - "system_constr.xdc" \ - "$ad_hdl_dir/library/common/ad_iobuf.v"] - -adi_project_run sidekiqz2 - diff --git a/projects/sidekiqz2/system_top.v b/projects/sidekiqz2/system_top.v deleted file mode 100755 index 279cb2c1ff3..00000000000 --- a/projects/sidekiqz2/system_top.v +++ /dev/null @@ -1,157 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - inout [14:0] ddr_addr, - inout [ 2:0] ddr_ba, - inout ddr_cas_n, - inout ddr_ck_n, - inout ddr_ck_p, - inout ddr_cke, - inout ddr_cs_n, - inout [ 1:0] ddr_dm, - inout [15:0] ddr_dq, - inout [ 1:0] ddr_dqs_n, - inout [ 1:0] ddr_dqs_p, - inout ddr_odt, - inout ddr_ras_n, - inout ddr_reset_n, - inout ddr_we_n, - - inout fixed_io_ddr_vrn, - inout fixed_io_ddr_vrp, - inout [31:0] fixed_io_mio, - inout fixed_io_ps_clk, - inout fixed_io_ps_porb, - inout fixed_io_ps_srstb, - - inout iic_scl, - inout iic_sda, - - input rx_clk_in, - input rx_frame_in, - input [11:0] rx_data_in, - output tx_clk_out, - output tx_frame_out, - output [11:0] tx_data_out, - - output enable, - output txnrx, - input clk_out, - - inout gpio_en_agc, - inout [ 3:0] gpio_ctl, - inout [ 7:0] gpio_status, - - inout [ 4:1] pl_gpio, - - output spi_csn, - output spi_clk, - output spi_mosi, - input spi_miso -); - - // internal signals - - wire [18:0] gpio_i; - wire [18:0] gpio_o; - wire [18:0] gpio_t; - - // instantiations - - ad_iobuf #( - .DATA_WIDTH(17) - ) i_iobuf ( - .dio_t (gpio_t[16:0]), - .dio_i (gpio_o[16:0]), - .dio_o (gpio_i[16:0]), - .dio_p ({ pl_gpio, // 16:13 - gpio_en_agc, // 12:12 - gpio_ctl, // 11: 8 - gpio_status})); // 7: 0 - - assign gpio_i[18:17] = gpio_o[18:17]; - - system_wrapper i_system_wrapper ( - .ddr_addr (ddr_addr), - .ddr_ba (ddr_ba), - .ddr_cas_n (ddr_cas_n), - .ddr_ck_n (ddr_ck_n), - .ddr_ck_p (ddr_ck_p), - .ddr_cke (ddr_cke), - .ddr_cs_n (ddr_cs_n), - .ddr_dm (ddr_dm), - .ddr_dq (ddr_dq), - .ddr_dqs_n (ddr_dqs_n), - .ddr_dqs_p (ddr_dqs_p), - .ddr_odt (ddr_odt), - .ddr_ras_n (ddr_ras_n), - .ddr_reset_n (ddr_reset_n), - .ddr_we_n (ddr_we_n), - .enable (enable), - .fixed_io_ddr_vrn (fixed_io_ddr_vrn), - .fixed_io_ddr_vrp (fixed_io_ddr_vrp), - .fixed_io_mio (fixed_io_mio), - .fixed_io_ps_clk (fixed_io_ps_clk), - .fixed_io_ps_porb (fixed_io_ps_porb), - .fixed_io_ps_srstb (fixed_io_ps_srstb), - .gpio_i (gpio_i), - .gpio_o (gpio_o), - .gpio_t (gpio_t), - .iic_main_scl_io (iic_scl), - .iic_main_sda_io (iic_sda), - .rx_clk_in (rx_clk_in), - .rx_data_in (rx_data_in), - .rx_frame_in (rx_frame_in), - .spi0_clk_i (1'b0), - .spi0_clk_o (spi_clk), - .spi0_csn_0_o (spi_csn), - .spi0_csn_1_o (), - .spi0_csn_2_o (), - .spi0_csn_i (1'b1), - .spi0_sdi_i (spi_miso), - .spi0_sdo_i (1'b0), - .spi0_sdo_o (spi_mosi), - .tx_clk_out (tx_clk_out), - .tx_data_out (tx_data_out), - .tx_frame_out (tx_frame_out), - .txnrx (txnrx), - .up_enable (gpio_o[17]), - .up_txnrx (gpio_o[18])); - -endmodule