From cad3dd5b68f85d9588d259ce51924c8ec39196ca Mon Sep 17 00:00:00 2001 From: Pop Ioan Daniel Date: Fri, 11 Jul 2025 12:21:35 +0300 Subject: [PATCH 1/3] library/axi_ada4355: Add BUFMRCE_EN parameter Signed-off-by: Pop Ioan Daniel --- library/axi_ada4355/axi_ada4355.v | 6 ++++-- library/axi_ada4355/axi_ada4355_if.v | 27 +++++++++++++++++++++------ 2 files changed, 25 insertions(+), 8 deletions(-) diff --git a/library/axi_ada4355/axi_ada4355.v b/library/axi_ada4355/axi_ada4355.v index fcb3805e352..a5f79d3278e 100644 --- a/library/axi_ada4355/axi_ada4355.v +++ b/library/axi_ada4355/axi_ada4355.v @@ -36,7 +36,8 @@ module axi_ada4355 #( parameter ID = 0, - parameter FPGA_TECHNOLOGY = 0 + parameter FPGA_TECHNOLOGY = 0, + parameter BUFMRCE_EN = 0 ) ( // ADC interface @@ -266,7 +267,8 @@ module axi_ada4355 #( axi_ada4355_if #( .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY), - .IODELAY_CTRL(1) + .IODELAY_CTRL(1), + .BUFMRCE_EN(BUFMRCE_EN) ) i_ada4355_interface ( .dco_n(dco_n), .dco_p(dco_p), diff --git a/library/axi_ada4355/axi_ada4355_if.v b/library/axi_ada4355/axi_ada4355_if.v index e2b1014af1d..b50f4d873da 100644 --- a/library/axi_ada4355/axi_ada4355_if.v +++ b/library/axi_ada4355/axi_ada4355_if.v @@ -41,7 +41,8 @@ module axi_ada4355_if #( parameter IODELAY_CTRL = 1, parameter DRP_WIDTH = 5, parameter NUM_LANES = 3, // 2 lanes of data, 1 frame - parameter FPGA_FAMILY = 1 + parameter FPGA_FAMILY = 1, + parameter BUFMRCE_EN = 0 ) ( // device interface @@ -148,21 +149,35 @@ module axi_ada4355_if #( .O(clk_in_s)); generate - if(FPGA_TECHNOLOGY == FPGA_FAMILY) begin + if(FPGA_TECHNOLOGY == FPGA_FAMILY) begin + if (BUFMRCE_EN == 0) begin + BUFIO i_clk_buf ( + .I(clk_in_s), + .O(adc_clk_in_fast)); + + assign adc_clk_in_fast_frame = adc_clk_in_fast; + BUFR #( + .BUFR_DIVIDE("4") + ) i_div_clk_buf ( + .CLR(1'b0), + .CE(1'b1), + .I(clk_in_s), + .O(adc_clk_div)); + + assign adc_clk_div_frame = adc_clk_div; + + end else begin BUFMRCE i_bufmrce ( .I(clk_in_s), .O(out_ibufmrce_clock), .CE(bufr_alignment)); - BUFIO i_clk_buf( .I(out_ibufmrce_clock), .O(adc_clk_in_fast)); - BUFIO i_clk_buf_frame( .I(out_ibufmrce_clock), .O(adc_clk_in_fast_frame)); - BUFR #( .BUFR_DIVIDE("4") ) i_div_clk_buf ( @@ -170,7 +185,6 @@ module axi_ada4355_if #( .CE(1'b1), .I(out_ibufmrce_clock), .O(adc_clk_div)); - BUFR #( .BUFR_DIVIDE("4") ) i_div_clk_buf_frame ( @@ -179,6 +193,7 @@ module axi_ada4355_if #( .I(out_ibufmrce_clock), .O(adc_clk_div_frame)); end + end endgenerate //serdes for data From 100e1f9914f007c004f363ef71f68f2b2fdbd6cc Mon Sep 17 00:00:00 2001 From: Pop Ioan Daniel Date: Fri, 11 Jul 2025 12:23:17 +0300 Subject: [PATCH 2/3] projects/ada4355: Add part with new xdc/Add BUFMRCE_EN parameter Update xdc constraints Loop back TRIG SMAs Add BUFMRCE_EN parameter Signed-off-by: Pop Ioan Daniel --- projects/ada4355_fmc/README.md | 1 + .../ada4355_fmc/common/ada4355_fmc_bd.tcl | 6 + projects/ada4355_fmc/zed/README.md | 39 ++- projects/ada4355_fmc/zed/system_bd.tcl | 5 +- projects/ada4355_fmc/zed/system_constr.xdc | 23 +- .../zed/system_constr_bufmrce_en.xdc | 41 +++ projects/ada4355_fmc/zed/system_project.tcl | 26 +- projects/ada4355_fmc/zed/system_top.v | 44 ++-- .../ada4355_fmc/zed/system_top_bufmrce_en.v | 248 ++++++++++++++++++ 9 files changed, 396 insertions(+), 37 deletions(-) create mode 100644 projects/ada4355_fmc/zed/system_constr_bufmrce_en.xdc create mode 100644 projects/ada4355_fmc/zed/system_top_bufmrce_en.v diff --git a/projects/ada4355_fmc/README.md b/projects/ada4355_fmc/README.md index 9daade6b2d1..4b19268ed05 100644 --- a/projects/ada4355_fmc/README.md +++ b/projects/ada4355_fmc/README.md @@ -3,6 +3,7 @@ - Evaluation board product page: [EVAL-ADA4355](https://www.analog.com/eval-ada4355.html) - System documentation: to be added - HDL project documentation: https://analogdevicesinc.github.io/hdl/projects/ada4355_fmc/index.html +- Evaluation board VADJ: 2.5V ## Supported parts diff --git a/projects/ada4355_fmc/common/ada4355_fmc_bd.tcl b/projects/ada4355_fmc/common/ada4355_fmc_bd.tcl index de574fb99dc..4a6d1117626 100644 --- a/projects/ada4355_fmc/common/ada4355_fmc_bd.tcl +++ b/projects/ada4355_fmc/common/ada4355_fmc_bd.tcl @@ -3,6 +3,11 @@ ### SPDX short identifier: ADIBSD ############################################################################### +# system level parameter + +set BUFMRCE_EN $ad_project_params(BUFMRCE_EN) +puts "build parameters: BUFMRCE_EN: $BUFMRCE_EN" + # ada4355 interface create_bd_port -dir I dco_p @@ -18,6 +23,7 @@ create_bd_port -dir I frame_n # axi_ada4355 ad_ip_instance axi_ada4355 axi_ada4355_adc +ad_ip_parameter axi_ada4355_adc CONFIG.BUFMRCE_EN $BUFMRCE_EN # dma for rx data diff --git a/projects/ada4355_fmc/zed/README.md b/projects/ada4355_fmc/zed/README.md index 38f2dd12e36..29a9c809d30 100644 --- a/projects/ada4355_fmc/zed/README.md +++ b/projects/ada4355_fmc/zed/README.md @@ -1,8 +1,39 @@ -# ADA4355 Zed HDL Project + -## Building the project +# ADA4355-FMC/ZED HDL Project + +- VADJ with which it was tested in hardware: 2.5V + +The parameters configurable through the `make` command, can be found below, as well as in the **system_project.tcl** file; it contains the default +configuration. ``` -cd projects/ada4355/zed +cd projects/ada4355_fmc/zed make -``` \ No newline at end of file +``` + +This project supports two evaluation boards, which are differentiated by how the frame clock signals are distributed. + +For the older evaluation board, the XDC constraints are not optimized for ISERDES, as the frame clock signals are located in a different I/O bank from the other related signals. To address this, a BUFMRCE buffer is used to distribute the frame clock to all ISERDES instances. + +The overwritable parameters from the environment: + +- BUFMRCE_EN - Specifies the evaluation board type + - 0 - newer evaluation board, with optimized constraints (default) + - 1 - older evaluation board, with non-optimized constraints + +### Example configurations + +#### BUFMRCE_EN disabled (default) + +This specific command is equivalent to running `make` only: + +``` +make BUFMRCE_EN=0 +``` + +#### BUFMRCE_EN enabled + +``` +make BUFMRCE_EN=1 +``` diff --git a/projects/ada4355_fmc/zed/system_bd.tcl b/projects/ada4355_fmc/zed/system_bd.tcl index 543d4e1b232..30dc85e68af 100644 --- a/projects/ada4355_fmc/zed/system_bd.tcl +++ b/projects/ada4355_fmc/zed/system_bd.tcl @@ -14,4 +14,7 @@ ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path" ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 -sysid_gen_sys_init_file +set BUFMRCE_EN $ad_project_params(BUFMRCE_EN) +set sys_cstring "BUFMRCE_EN" + +sysid_gen_sys_init_file $sys_cstring diff --git a/projects/ada4355_fmc/zed/system_constr.xdc b/projects/ada4355_fmc/zed/system_constr.xdc index fb7418258a5..b9d89f2c230 100644 --- a/projects/ada4355_fmc/zed/system_constr.xdc +++ b/projects/ada4355_fmc/zed/system_constr.xdc @@ -12,30 +12,31 @@ set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports d set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports d1a_p]; ## H10 FMC_LA04_P IO_L15P_T2_DQS_34 set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports d1a_n]; ## H11 FMC_LA04_N IO_L15N_T2_DQS_34 -set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports frame_p]; ## G2 FMC_CLK1_M2C_P IO_L12P_T1_MRCC_35 -set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports frame_n]; ## G3 FMC_CLK1_M2C_N IO_L12N_T1_MRCC_35 +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports frame_p]; ## G6 FMC_LA00_CC_P IO_L13P_T2_MRCC_34 +set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports frame_n]; ## G7 FMC_LA00_CC_N IO_L13N_T2_MRCC_34 -set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports fsel]; ## H25 FMC_LA21_P IO_L21P_T3_DQS_AD14P_35 +set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports freq_sel0]; ## H25 FMC_LA21_P IO_L21P_T3_DQS_AD14P_35 +set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports freq_sel1]; ## H26 FMC_LA21_N IO_L21N_T3_DQS_AD14N_35 set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS25} [get_ports gain_sel0]; ## G21 FMC_LA20_P IO_L22P_T3_AD7P_35 set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS25} [get_ports gain_sel1]; ## G22 FMC_LA20_N IO_L22N_T3_AD7N_35 -set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS25} [get_ports gain_sel2]; ## H29 FMC_LA24_N IO_L10N_T1_AD11N_35 -set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports gpio_1p8vd_en]; ## G16 FMC_LA12_N IO_L18N_T2_34 -set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25} [get_ports gpio_1p8va_en]; ## D23 FMC_LA23_P IO_L3P_T0_DQS_AD1P_35 +set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS25} [get_ports gain_sel2]; ## G24 FMC_LA22_P IO_L20P_T3_AD6P_35 +set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS25} [get_ports gain_sel3]; ## G25 FMC_LA22_N IO_L20N_T3_AD6N_35 +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports gpio_vld_en]; ## G16 FMC_LA12_N IO_L18N_T2_34 +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25} [get_ports gpio_test]; ## D23 FMC_LA23_P IO_L3P_T0_DQS_AD1P_35 +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports trig_fmc_in]; ## C14 FMC_LA10_P IO_L22P_T3_34 +set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports trig_fmc_out]; ## C15 FMC_LA10_N IO_L22N_T3_34 +set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS25} [get_ports apd_supp_en]; ## C18 FMC_LA14_P IO_L11P_T1_SRCC_34 set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports csb_apd_pot]; ## G12 FMC_LA08_P IO_L8P_T1_34 -set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports csb_ld_pot]; ## G15 FMC_LA12_P IO_L18P_T2_34 set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports sclk_pot]; ## D9 FMC_LA01_CC_N IO_L14N_T2_SRCC_34 set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports mosi_pot]; ## H14 FMC_LA07_N IO_L21N_T3_DQS_34 set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports miso_pot]; ## H13 FMC_LA07_P IO_L21P_T3_DQS_34 set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports ada4355_csn]; ## G13 FMC_LA08_N IO_L8N_T1_34 -set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ada4355_sclk]; ## D8 FMC_LA01_CC_P IO_L14P_T2_SRCC_34 +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ada4355_sclk]; ## D8 FMC_LA01_CC_P IO_L14P_T2_SRCC_34 set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ada4355_mosi]; ## H7 FMC_LA02_P IO_L20P_T3_34 set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ada4355_miso]; ## H8 FMC_LA02_N IO_L20N_T3_34 # clocks create_clock -period 2.000 -name dco_clk [get_ports dco_p] - -set_false_path -to [get_pins i_system_wrapper/system_i/axi_ada4355_adc/inst/i_ada4355_interface/bufr_alignment_reg/CLR] -set_false_path -to [get_pins i_system_wrapper/system_i/axi_ada4355_adc/inst/i_ada4355_interface/bufr_alignment_bufr_reg/PRE] diff --git a/projects/ada4355_fmc/zed/system_constr_bufmrce_en.xdc b/projects/ada4355_fmc/zed/system_constr_bufmrce_en.xdc new file mode 100644 index 00000000000..fb7418258a5 --- /dev/null +++ b/projects/ada4355_fmc/zed/system_constr_bufmrce_en.xdc @@ -0,0 +1,41 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports dco_p]; ## H4 FMC_CLK0_M2C_P IO_L12P_T1_MRCC_34 +set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports dco_n]; ## H5 FMC_CLK0_M2C_N IO_L12N_T1_MRCC_34 + +set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports d0a_p]; ## G9 FMC_LA03_P IO_L16P_T2_34 +set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports d0a_n]; ## G10 FMC_LA03_N IO_L16N_T2_34 + +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports d1a_p]; ## H10 FMC_LA04_P IO_L15P_T2_DQS_34 +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports d1a_n]; ## H11 FMC_LA04_N IO_L15N_T2_DQS_34 + +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports frame_p]; ## G2 FMC_CLK1_M2C_P IO_L12P_T1_MRCC_35 +set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports frame_n]; ## G3 FMC_CLK1_M2C_N IO_L12N_T1_MRCC_35 + +set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports fsel]; ## H25 FMC_LA21_P IO_L21P_T3_DQS_AD14P_35 +set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS25} [get_ports gain_sel0]; ## G21 FMC_LA20_P IO_L22P_T3_AD7P_35 +set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS25} [get_ports gain_sel1]; ## G22 FMC_LA20_N IO_L22N_T3_AD7N_35 +set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS25} [get_ports gain_sel2]; ## H29 FMC_LA24_N IO_L10N_T1_AD11N_35 +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports gpio_1p8vd_en]; ## G16 FMC_LA12_N IO_L18N_T2_34 +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25} [get_ports gpio_1p8va_en]; ## D23 FMC_LA23_P IO_L3P_T0_DQS_AD1P_35 + +set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports csb_apd_pot]; ## G12 FMC_LA08_P IO_L8P_T1_34 +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports csb_ld_pot]; ## G15 FMC_LA12_P IO_L18P_T2_34 +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports sclk_pot]; ## D9 FMC_LA01_CC_N IO_L14N_T2_SRCC_34 +set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports mosi_pot]; ## H14 FMC_LA07_N IO_L21N_T3_DQS_34 +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports miso_pot]; ## H13 FMC_LA07_P IO_L21P_T3_DQS_34 + +set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports ada4355_csn]; ## G13 FMC_LA08_N IO_L8N_T1_34 +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ada4355_sclk]; ## D8 FMC_LA01_CC_P IO_L14P_T2_SRCC_34 +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ada4355_mosi]; ## H7 FMC_LA02_P IO_L20P_T3_34 +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ada4355_miso]; ## H8 FMC_LA02_N IO_L20N_T3_34 + +# clocks + +create_clock -period 2.000 -name dco_clk [get_ports dco_p] + +set_false_path -to [get_pins i_system_wrapper/system_i/axi_ada4355_adc/inst/i_ada4355_interface/bufr_alignment_reg/CLR] +set_false_path -to [get_pins i_system_wrapper/system_i/axi_ada4355_adc/inst/i_ada4355_interface/bufr_alignment_bufr_reg/PRE] diff --git a/projects/ada4355_fmc/zed/system_project.tcl b/projects/ada4355_fmc/zed/system_project.tcl index e9651348e65..634c347bfb6 100644 --- a/projects/ada4355_fmc/zed/system_project.tcl +++ b/projects/ada4355_fmc/zed/system_project.tcl @@ -7,11 +7,29 @@ source ../../../scripts/adi_env.tcl source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl -adi_project ada4355_fmc_zed +# Parameter description +# BUFMRCE_EN - Enable BUFMRCE buffer + +set BUFMRCE_EN [get_env_param BUFMRCE_EN 0] + +adi_project ada4355_fmc_zed 0 [list \ + BUFMRCE_EN $BUFMRCE_EN ] + adi_project_files ada4355_fmc_zed [list \ "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \ - "system_constr.xdc" \ - "system_top.v" ] + "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ] + +switch $BUFMRCE_EN { + 0 { + adi_project_files ada4355_fmc_zed [list \ + "system_constr.xdc" \ + "system_top.v" ] + } + 1 { + adi_project_files ada4355_fmc_zed [list \ + "system_constr_bufmrce_en.xdc" \ + "system_top_bufmrce_en.v" ] + } +} adi_project_run ada4355_fmc_zed diff --git a/projects/ada4355_fmc/zed/system_top.v b/projects/ada4355_fmc/zed/system_top.v index 744286711c5..640ba21d2b9 100644 --- a/projects/ada4355_fmc/zed/system_top.v +++ b/projects/ada4355_fmc/zed/system_top.v @@ -99,11 +99,16 @@ module system_top ( inout gain_sel0, inout gain_sel1, - input gain_sel2, + inout gain_sel2, + inout gain_sel3, - inout fsel, - inout gpio_1p8vd_en, - input gpio_1p8va_en, + inout freq_sel0, + inout freq_sel1, + inout gpio_vld_en, + inout gpio_test, + inout trig_fmc_in, + inout trig_fmc_out, + inout apd_supp_en, // ADC SPI @@ -115,7 +120,6 @@ module system_top ( input miso_pot, output sclk_pot, output mosi_pot, - output csb_ld_pot, output csb_apd_pot ); @@ -132,10 +136,8 @@ module system_top ( wire [ 1:0] iic_mux_sda_o_s; wire iic_mux_sda_t_s; - assign gpio_i[36] = gain_sel2; - assign gpio_i[37] = gpio_1p8va_en; - - assign gpio_i[63:38] = gpio_o[63:38]; + assign gpio_i[63:43] = gpio_o[63:43]; + assign trig_fmc_out = trig_fmc_in; ad_iobuf #( .DATA_WIDTH(32) @@ -146,13 +148,20 @@ module system_top ( .dio_p({gpio_bd[31:0]})); ad_iobuf #( - .DATA_WIDTH(4) + .DATA_WIDTH(11) ) i_iobuf_ada4355_gpio ( - .dio_t(gpio_t[35:32]), - .dio_i(gpio_o[35:32]), - .dio_o(gpio_i[35:32]), - .dio_p({gpio_1p8vd_en, - fsel, + .dio_t(gpio_t[42:32]), + .dio_i(gpio_o[42:32]), + .dio_o(gpio_i[42:32]), + .dio_p({apd_supp_en, + trig_fmc_out, + trig_fmc_in, + freq_sel1, + gain_sel3, + gpio_test, + gain_sel2, + gpio_vld_en, + freq_sel0, gain_sel1, gain_sel0})); @@ -228,8 +237,8 @@ module system_top ( .spi0_sdo_o (ada4355_mosi), .spi1_clk_i (1'b0), .spi1_clk_o (sclk_pot), - .spi1_csn_0_o ( csb_apd_pot), - .spi1_csn_1_o (csb_ld_pot), + .spi1_csn_0_o (csb_apd_pot), + .spi1_csn_1_o (), .spi1_csn_2_o (), .spi1_csn_i (1'b1), .spi1_sdi_i (miso_pot), @@ -244,4 +253,5 @@ module system_top ( .frame_p(frame_p), .frame_n(frame_n), .sync_n (1'b1)); + endmodule diff --git a/projects/ada4355_fmc/zed/system_top_bufmrce_en.v b/projects/ada4355_fmc/zed/system_top_bufmrce_en.v new file mode 100644 index 00000000000..9e5f5cfbe40 --- /dev/null +++ b/projects/ada4355_fmc/zed/system_top_bufmrce_en.v @@ -0,0 +1,248 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [31:0] gpio_bd, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, + + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, + + output spdif, + + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, + + input otg_vbusoc, + + // FMC connector + // LVDS data interace + + input dco_p, + input dco_n, + input d0a_p, + input d0a_n, + input d1a_p, + input d1a_n, + input frame_p, + input frame_n, + + // GPIOs + + inout gain_sel0, + inout gain_sel1, + input gain_sel2, + + inout fsel, + inout gpio_1p8vd_en, + input gpio_1p8va_en, + + // ADC SPI + + input ada4355_miso, + output ada4355_sclk, + output ada4355_csn, + output ada4355_mosi, + + input miso_pot, + output sclk_pot, + output mosi_pot, + output csb_ld_pot, + output csb_apd_pot +); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] iic_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire iic_mux_sda_t_s; + + assign gpio_i[36] = gain_sel2; + assign gpio_i[37] = gpio_1p8va_en; + + assign gpio_i[63:38] = gpio_o[63:38]; + + ad_iobuf #( + .DATA_WIDTH(32) + ) i_gpio_bd ( + .dio_t({gpio_t[31:0]}), + .dio_i({gpio_o[31:0]}), + .dio_o({gpio_i[31:0]}), + .dio_p({gpio_bd[31:0]})); + + ad_iobuf #( + .DATA_WIDTH(4) + ) i_iobuf_ada4355_gpio ( + .dio_t(gpio_t[35:32]), + .dio_i(gpio_o[35:32]), + .dio_o(gpio_i[35:32]), + .dio_p({gpio_1p8vd_en, + fsel, + gain_sel1, + gain_sel0})); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iobuf_iic_scl ( + .dio_t ({iic_mux_scl_t_s,iic_mux_scl_t_s}), + .dio_i (iic_mux_scl_o_s), + .dio_o (iic_mux_scl_i_s), + .dio_p (iic_mux_scl)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iobuf_iic_sda ( + .dio_t ({iic_mux_sda_t_s,iic_mux_sda_t_s}), + .dio_i (iic_mux_sda_o_s), + .dio_o (iic_mux_sda_i_s), + .dio_p (iic_mux_sda)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_i (iic_mux_scl_i_s), + .iic_mux_scl_o (iic_mux_scl_o_s), + .iic_mux_scl_t (iic_mux_scl_t_s), + .iic_mux_sda_i (iic_mux_sda_i_s), + .iic_mux_sda_o (iic_mux_sda_o_s), + .iic_mux_sda_t (iic_mux_sda_t_s), + .otg_vbusoc (otg_vbusoc), + .spdif (spdif), + .spi0_clk_i (1'b0), + .spi0_clk_o (ada4355_sclk), + .spi0_csn_0_o (ada4355_csn), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (ada4355_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (ada4355_mosi), + .spi1_clk_i (1'b0), + .spi1_clk_o (sclk_pot), + .spi1_csn_0_o ( csb_apd_pot), + .spi1_csn_1_o (csb_ld_pot), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (miso_pot), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (mosi_pot), + .dco_p (dco_p), + .dco_n (dco_n), + .d0a_p (d0a_p), + .d0a_n (d0a_n), + .d1a_p (d1a_p), + .d1a_n (d1a_n), + .frame_p(frame_p), + .frame_n(frame_n), + .sync_n (1'b1)); + +endmodule From 00460085c25e6e8f42c06128afca5c60ead23b28 Mon Sep 17 00:00:00 2001 From: Pop Ioan Daniel Date: Fri, 11 Jul 2025 12:28:04 +0300 Subject: [PATCH 3/3] docs/ada4355: Update documentation Signed-off-by: Pop Ioan Daniel --- docs/library/axi_ada4355/index.rst | 5 ++ docs/projects/ada4355_fmc/index.rst | 102 ++++++++++++++++++++++++++-- 2 files changed, 103 insertions(+), 4 deletions(-) diff --git a/docs/library/axi_ada4355/index.rst b/docs/library/axi_ada4355/index.rst index aa883bee8db..bf96f0bed2c 100644 --- a/docs/library/axi_ada4355/index.rst +++ b/docs/library/axi_ada4355/index.rst @@ -48,6 +48,9 @@ Configuration Parameters - Core ID should be unique for each IP in the system * - FPGA_TECHNOLOGY - Used to select between FPGA devices, auto set in project. + * - BUFMRCE_EN + - Used to select between evaluation boards that are differentiated + by how the frame clock signals are distributed. Interface -------------------------------------------------------------------------------- @@ -83,6 +86,8 @@ Interface - Received data output * - adc_dovf - Data overflow. Must be connected to the DMA + * - up_adc_pn_err + - Error monitoring * - s_axi - Standard AXI Slave Memory Map interface diff --git a/docs/projects/ada4355_fmc/index.rst b/docs/projects/ada4355_fmc/index.rst index 0e2876aa490..ae11f6f23ef 100644 --- a/docs/projects/ada4355_fmc/index.rst +++ b/docs/projects/ada4355_fmc/index.rst @@ -66,6 +66,32 @@ The data path and clock domains are depicted in the below diagram: :align: center :alt: ADA4355_FMC/ZedBoard block diagram +Configuration modes +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The BUFMRCE_EN configuration parameter defines the type of evaluation board +used, which are differentiated by how the frame clock signals are distributed. +For the older evaluation board, the XDC constraints are not optimized for +ISERDES, as the frame clock signals are located in a different I/O bank from +the other related signals. To address this, a BUFMRCE buffer is used to +distribute the frame clock to all ISERDES instances. + +By default it is set to 0. Depending on the type of evaluation board, some +hardware modifications need to be done on the board and/or ``make`` command: + +In case of the Eval-Board with optimized xdc: + +.. shell:: bash + + $make BUFMRCE_EN=0 + +In case of the Eval-Board with non optimized xdc: + +.. shell:: bash + + $make BUFMRCE_EN=1 + + CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -121,19 +147,55 @@ The Software GPIO number is calculated as follows: - (from FPGA view) - - Zynq-7000 - * - gpio_1p8va_en + * - apd_supp_en ** + - INOUT + - 42 + - 96 + * - trig_fmc_out ** + - INOUT + - 41 + - 95 + * - trig_fmc_in ** + - INOUT + - 40 + - 94 + * - freq_sel1 ** + - INOUT + - 39 + - 93 + * - gain_sel3 ** + - INOUT + - 38 + - 92 + * - gpio_test ** + - INOUT + - 37 + - 91 + * - gpio_1p8va_en * - IN - 37 - 91 - * - gain_sel2 + * - gain_sel2 ** + - INOUT + - 36 + - 90 + * - gain_sel2 * - IN - 36 - 90 - * - gpio_1p8vd_en + * - gpio_vld_en ** - INOUT - 35 - 89 - * - fsel + * - gpio_1p8vd_en * + - INOUT + - 35 + - 89 + * - freq_sel0 ** + - INOUT + - 34 + - 88 + * - fsel * - INOUT - 34 - 88 @@ -146,6 +208,12 @@ The Software GPIO number is calculated as follows: - 32 - 86 +.. admonition:: Legend + :class: note + + - ``*`` instantiated only for BUFMRCE_EN=1 + - ``**`` instantiated only for BUFMRCE_EN=0 + Interrupts ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -188,13 +256,39 @@ If you want to build the sources, ADI makes them available on the `clone `__ the HDL repository. +Examples on how to build the project: + **Linux/Cygwin/WSL** +Example for building with the default configuration: + .. shell:: $cd hdl/projects/ada4355_fmc/zed $make +Example for building with parameters: + +.. shell:: + + $cd hdl/projects/ada4355_fmc/zed + $make BUFMRCE_EN=0 + +Default values of the ``make`` parameters for ADA4355-FMC: + +- BUFMRCE_EN: 0 + +The result of the build, if parameters were used, will be in a folder named +by the configuration used. + +If the following command was run + +``make BUFMRCE_EN=0`` + +then the folder name will be: ``BUFMRCEEN0``. + +Check `Configuration modes`_ for more details. + A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. 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