ADA4355 HDL updates

docs/library/axi_ada4355/index.rst

@@ -48,6 +48,9 @@ Configuration Parameters
      - Core ID should be unique for each IP in the system
    * - FPGA_TECHNOLOGY
      - Used to select between FPGA devices, auto set in project.
+   * - BUFMRCE_EN
+     - Used to select between evaluation boards that are differentiated
+       by how the frame clock signals are distributed.
 
 Interface
 --------------------------------------------------------------------------------
@@ -83,6 +86,8 @@ Interface
      - Received data output
    * - adc_dovf
      - Data overflow. Must be connected to the DMA
+   * - up_adc_pn_err
+     - Error monitoring
    * - s_axi
      - Standard AXI Slave Memory Map interface
 

docs/projects/ada4355_fmc/index.rst

@@ -66,6 +66,32 @@ The data path and clock domains are depicted in the below diagram:
    :align: center
    :alt: ADA4355_FMC/ZedBoard block diagram
 
+Configuration modes
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The BUFMRCE_EN configuration parameter defines the type of evaluation board
+used, which are differentiated by how the frame clock signals are distributed.
+For the older evaluation board, the XDC constraints are not optimized for
+ISERDES, as the frame clock signals are located in a different I/O bank from
+the other related signals. To address this, a BUFMRCE buffer is used to
+distribute the frame clock to all ISERDES instances.
+
+By default it is set to 0. Depending on the type of evaluation board, some
+hardware modifications need to be done on the board and/or ``make`` command:
+
+In case of the Eval-Board with optimized xdc:
+
+.. shell:: bash
+
+   $make BUFMRCE_EN=0
+
+In case of the Eval-Board with non optimized xdc:
+
+.. shell:: bash
+
+   $make BUFMRCE_EN=1
+
+
 CPU/Memory interconnects addresses
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -121,19 +147,55 @@ The Software GPIO number is calculated as follows:
      - (from FPGA view)
      -
      - Zynq-7000
-   * - gpio_1p8va_en
+   * - apd_supp_en **
+     - INOUT
+     - 42
+     - 96
+   * - trig_fmc_out **
+     - INOUT
+     - 41
+     - 95
+   * - trig_fmc_in **
+     - INOUT
+     - 40
+     - 94
+   * - freq_sel1 **
+     - INOUT
+     - 39
+     - 93
+   * - gain_sel3 **
+     - INOUT
+     - 38
+     - 92
+   * - gpio_test **
+     - INOUT
+     - 37
+     - 91
+   * - gpio_1p8va_en *
      - IN
      - 37
      - 91
-   * - gain_sel2
+   * - gain_sel2 **
+     - INOUT
+     - 36
+     - 90
+   * - gain_sel2 *
      - IN
      - 36
      - 90
-   * - gpio_1p8vd_en
+   * - gpio_vld_en **
      - INOUT
      - 35
      - 89
-   * - fsel
+   * - gpio_1p8vd_en *
+     - INOUT
+     - 35
+     - 89
+   * - freq_sel0 **
+     - INOUT
+     - 34
+     - 88
+   * - fsel *
      - INOUT
      - 34
      - 88
@@ -146,6 +208,12 @@ The Software GPIO number is calculated as follows:
      - 32
      - 86
 
+.. admonition:: Legend
+   :class: note
+
+   - ``*`` instantiated only for BUFMRCE_EN=1
+   - ``**`` instantiated only for BUFMRCE_EN=0
+
 Interrupts
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -188,13 +256,39 @@ If you want to build the sources, ADI makes them available on the
 `clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__
 the HDL repository.
 
+Examples on how to build the project:
+
 **Linux/Cygwin/WSL**
 
+Example for building with the default configuration:
+
 .. shell::
 
    $cd hdl/projects/ada4355_fmc/zed
    $make
 
+Example for building with parameters:
+
+.. shell::
+
+   $cd hdl/projects/ada4355_fmc/zed
+   $make BUFMRCE_EN=0
+
+Default values of the ``make`` parameters for ADA4355-FMC:
+
+- BUFMRCE_EN: 0
+
+The result of the build, if parameters were used, will be in a folder named
+by the configuration used.
+
+If the following command was run
+
+``make BUFMRCE_EN=0``
+
+then the folder name will be: ``BUFMRCEEN0``.
+
+Check `Configuration modes`_ for more details.
+
 A more comprehensive build guide can be found in the :ref:`build_hdl` user guide.
 
 Resources

library/axi_ada4355/axi_ada4355.v

@@ -36,7 +36,8 @@
 module axi_ada4355 #(
 
   parameter   ID = 0,
-  parameter   FPGA_TECHNOLOGY = 0
+  parameter   FPGA_TECHNOLOGY = 0,
+  parameter   BUFMRCE_EN = 0
 ) (
 
   // ADC interface
@@ -266,7 +267,8 @@ module axi_ada4355 #(
 
   axi_ada4355_if #(
     .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
-    .IODELAY_CTRL(1)
+    .IODELAY_CTRL(1),
+    .BUFMRCE_EN(BUFMRCE_EN)
   ) i_ada4355_interface (
     .dco_n(dco_n),
     .dco_p(dco_p),

library/axi_ada4355/axi_ada4355_if.v

@@ -41,7 +41,8 @@ module axi_ada4355_if #(
   parameter IODELAY_CTRL = 1,
   parameter DRP_WIDTH = 5,
   parameter NUM_LANES = 3,  // 2 lanes of data, 1 frame
-  parameter FPGA_FAMILY = 1
+  parameter FPGA_FAMILY = 1,
+  parameter BUFMRCE_EN = 0
 ) (
 
   // device interface
@@ -148,29 +149,42 @@ module axi_ada4355_if #(
     .O(clk_in_s));
 
   generate
-    if(FPGA_TECHNOLOGY == FPGA_FAMILY) begin
+  if(FPGA_TECHNOLOGY == FPGA_FAMILY) begin
+    if (BUFMRCE_EN == 0) begin
+      BUFIO i_clk_buf (
+        .I(clk_in_s),
+        .O(adc_clk_in_fast));
+
+    assign adc_clk_in_fast_frame = adc_clk_in_fast;
 
+      BUFR #(
+        .BUFR_DIVIDE("4")
+      ) i_div_clk_buf (
+        .CLR(1'b0),
+        .CE(1'b1),
+        .I(clk_in_s),
+        .O(adc_clk_div));
+
+    assign adc_clk_div_frame = adc_clk_div;
+
+    end else begin
       BUFMRCE i_bufmrce (
         .I(clk_in_s),
         .O(out_ibufmrce_clock),
         .CE(bufr_alignment));
-
       BUFIO i_clk_buf(
         .I(out_ibufmrce_clock),
         .O(adc_clk_in_fast));
-
       BUFIO i_clk_buf_frame(
         .I(out_ibufmrce_clock),
         .O(adc_clk_in_fast_frame));
-
       BUFR #(
         .BUFR_DIVIDE("4")
       ) i_div_clk_buf (
         .CLR(bufr_alignment_bufr),
         .CE(1'b1),
         .I(out_ibufmrce_clock),
         .O(adc_clk_div));
-
       BUFR #(
         .BUFR_DIVIDE("4")
       ) i_div_clk_buf_frame (
@@ -179,6 +193,7 @@ module axi_ada4355_if #(
         .I(out_ibufmrce_clock),
         .O(adc_clk_div_frame));
     end
+  end
   endgenerate
 
   //serdes for data

projects/ada4355_fmc/README.md

@@ -3,6 +3,7 @@
 - Evaluation board product page: [EVAL-ADA4355](https://www.analog.com/eval-ada4355.html)
 - System documentation: to be added
 - HDL project documentation: https://analogdevicesinc.github.io/hdl/projects/ada4355_fmc/index.html
+- Evaluation board VADJ: 2.5V
 
 ## Supported parts
 

projects/ada4355_fmc/common/ada4355_fmc_bd.tcl

@@ -3,6 +3,11 @@
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
+# system level parameter
+
+set BUFMRCE_EN $ad_project_params(BUFMRCE_EN)
+puts "build parameters: BUFMRCE_EN: $BUFMRCE_EN"
+
 # ada4355 interface
 
 create_bd_port -dir I dco_p
@@ -18,6 +23,7 @@ create_bd_port -dir I frame_n
 # axi_ada4355
 
 ad_ip_instance axi_ada4355 axi_ada4355_adc
+ad_ip_parameter axi_ada4355_adc CONFIG.BUFMRCE_EN $BUFMRCE_EN
 
 # dma for rx data
 

projects/ada4355_fmc/zed/README.md

@@ -1,8 +1,39 @@
-# ADA4355 Zed HDL Project
+<!-- no_dts, no_no_os -->
 
-## Building the project
+# ADA4355-FMC/ZED HDL Project
+
+- VADJ with which it was tested in hardware: 2.5V
+
+The parameters configurable through the `make` command, can be found below, as well as in the **system_project.tcl** file; it contains the default
+configuration.
 
 ```
-cd projects/ada4355/zed
+cd projects/ada4355_fmc/zed
 make
-```
+```
+
+This project supports two evaluation boards, which are differentiated by how the frame clock signals are distributed.
+
+For the older evaluation board, the XDC constraints are not optimized for ISERDES, as the frame clock signals are located in a different I/O bank from the other related signals. To address this, a BUFMRCE buffer is used to distribute the frame clock to all ISERDES instances.
+
+The overwritable parameters from the environment:
+
+- BUFMRCE_EN - Specifies the evaluation board type
+  - 0 - newer evaluation board, with optimized constraints (default)
+  - 1 - older evaluation board, with non-optimized constraints
+
+### Example configurations
+
+#### BUFMRCE_EN disabled (default)
+
+This specific command is equivalent to running `make` only:
+
+```
+make BUFMRCE_EN=0
+```
+
+#### BUFMRCE_EN enabled
+
+```
+make BUFMRCE_EN=1
+```

projects/ada4355_fmc/zed/system_bd.tcl

@@ -14,4 +14,7 @@ ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
 ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path"
 ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
 
-sysid_gen_sys_init_file
+set BUFMRCE_EN $ad_project_params(BUFMRCE_EN)
+set sys_cstring "BUFMRCE_EN"
+
+sysid_gen_sys_init_file $sys_cstring

projects/ada4355_fmc/zed/system_constr.xdc

@@ -12,30 +12,31 @@ set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports d
 set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports d1a_p];  ## H10 FMC_LA04_P IO_L15P_T2_DQS_34
 set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports d1a_n];  ## H11 FMC_LA04_N IO_L15N_T2_DQS_34
 
-set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports frame_p]; ## G2  FMC_CLK1_M2C_P IO_L12P_T1_MRCC_35
-set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports frame_n]; ## G3 FMC_CLK1_M2C_N IO_L12N_T1_MRCC_35
+set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports frame_p]; ## G6 FMC_LA00_CC_P IO_L13P_T2_MRCC_34
+set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports frame_n]; ## G7 FMC_LA00_CC_N IO_L13N_T2_MRCC_34
 
-set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports fsel];          ## H25 FMC_LA21_P IO_L21P_T3_DQS_AD14P_35
+set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports freq_sel0];     ## H25 FMC_LA21_P IO_L21P_T3_DQS_AD14P_35
+set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports freq_sel1];     ## H26 FMC_LA21_N IO_L21N_T3_DQS_AD14N_35
 set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS25} [get_ports gain_sel0];     ## G21 FMC_LA20_P IO_L22P_T3_AD7P_35
 set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS25} [get_ports gain_sel1];     ## G22 FMC_LA20_N IO_L22N_T3_AD7N_35
-set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS25} [get_ports gain_sel2];     ## H29 FMC_LA24_N IO_L10N_T1_AD11N_35
-set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports gpio_1p8vd_en]; ## G16 FMC_LA12_N IO_L18N_T2_34
-set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25} [get_ports gpio_1p8va_en]; ## D23 FMC_LA23_P IO_L3P_T0_DQS_AD1P_35
+set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS25} [get_ports gain_sel2];     ## G24 FMC_LA22_P IO_L20P_T3_AD6P_35
+set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS25} [get_ports gain_sel3];     ## G25 FMC_LA22_N IO_L20N_T3_AD6N_35
+set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports gpio_vld_en];   ## G16 FMC_LA12_N IO_L18N_T2_34
+set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25} [get_ports gpio_test];     ## D23 FMC_LA23_P IO_L3P_T0_DQS_AD1P_35
+set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports trig_fmc_in];   ## C14 FMC_LA10_P IO_L22P_T3_34
+set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports trig_fmc_out];  ## C15 FMC_LA10_N IO_L22N_T3_34
+set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS25} [get_ports apd_supp_en];   ## C18 FMC_LA14_P IO_L11P_T1_SRCC_34
 
 set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports csb_apd_pot];   ## G12 FMC_LA08_P IO_L8P_T1_34
-set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports csb_ld_pot];    ## G15 FMC_LA12_P IO_L18P_T2_34
 set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports sclk_pot];      ## D9 FMC_LA01_CC_N IO_L14N_T2_SRCC_34
 set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports mosi_pot];      ## H14 FMC_LA07_N IO_L21N_T3_DQS_34
 set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports miso_pot];      ## H13 FMC_LA07_P IO_L21P_T3_DQS_34
 
 set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports ada4355_csn];   ## G13 FMC_LA08_N IO_L8N_T1_34
-set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ada4355_sclk];  ## D8  FMC_LA01_CC_P IO_L14P_T2_SRCC_34
+set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ada4355_sclk];  ## D8 FMC_LA01_CC_P IO_L14P_T2_SRCC_34
 set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ada4355_mosi];  ## H7 FMC_LA02_P IO_L20P_T3_34
 set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ada4355_miso];  ## H8 FMC_LA02_N IO_L20N_T3_34
 
 # clocks
 
 create_clock -period 2.000 -name dco_clk [get_ports dco_p]
-
-set_false_path -to [get_pins i_system_wrapper/system_i/axi_ada4355_adc/inst/i_ada4355_interface/bufr_alignment_reg/CLR]
-set_false_path -to [get_pins i_system_wrapper/system_i/axi_ada4355_adc/inst/i_ada4355_interface/bufr_alignment_bufr_reg/PRE]