From d5cb8cd0165893e8fac42a075b1885a398ef2f99 Mon Sep 17 00:00:00 2001 From: Capota Bianca Date: Wed, 2 Jul 2025 17:27:12 +0300 Subject: [PATCH 1/2] projects/cn0561:Add VADJ and VIO in READMEs --- projects/cn0561/README.md | 2 ++ projects/cn0561/coraz7s/README.md | 4 ++++ projects/cn0561/de10nano/README.md | 4 ++++ projects/cn0561/zed/README.md | 4 ++++ 4 files changed, 14 insertions(+) diff --git a/projects/cn0561/README.md b/projects/cn0561/README.md index 932bb53d10..703ce846af 100644 --- a/projects/cn0561/README.md +++ b/projects/cn0561/README.md @@ -3,6 +3,8 @@ - Evaluation board product page: TO BE ADDED - System documentation: TO BE ADDED - HDL project documentation: https://analogdevicesinc.github.io/hdl/projects/cn0561/index.html +- Evaluation board VADJ for FMC connector: 1.8V +- Evaluation board VIO for ARDUINO connector: 3.3V ## Supported parts diff --git a/projects/cn0561/coraz7s/README.md b/projects/cn0561/coraz7s/README.md index e61c8a702a..8425572c2f 100644 --- a/projects/cn0561/coraz7s/README.md +++ b/projects/cn0561/coraz7s/README.md @@ -1,5 +1,9 @@ + + # CN0561/CORAZ7S HDL Project +- VIO with which it was tested in hardware: 3.3V + ## Building the project ``` diff --git a/projects/cn0561/de10nano/README.md b/projects/cn0561/de10nano/README.md index dabd1f7cbc..26c59d8e39 100644 --- a/projects/cn0561/de10nano/README.md +++ b/projects/cn0561/de10nano/README.md @@ -1,5 +1,9 @@ + + # CN0561/DE10NANO HDL Project +- VIO with which it was tested in hardware: 3.3V + ## Building the project ``` diff --git a/projects/cn0561/zed/README.md b/projects/cn0561/zed/README.md index c08350bef4..eb37da9cf5 100644 --- a/projects/cn0561/zed/README.md +++ b/projects/cn0561/zed/README.md @@ -1,5 +1,9 @@ + + # CN0561/ZED HDL Project +- VADJ with which it was tested in hardware: 1.8V + ## Building the project ``` From 94b69766d1b0aae013eb8273d4bb1d288b200c9b Mon Sep 17 00:00:00 2001 From: Capota Bianca Date: Thu, 3 Jul 2025 14:29:04 +0300 Subject: [PATCH 2/2] projects/cn0561:Update VADJ value in constraints for ZED --- projects/cn0561/zed/system_constr.xdc | 139 +++++++++++++++++++++---- projects/cn0561/zed/system_project.tcl | 5 +- 2 files changed, 119 insertions(+), 25 deletions(-) diff --git a/projects/cn0561/zed/system_constr.xdc b/projects/cn0561/zed/system_constr.xdc index 0f7d44310d..eebe5eb203 100644 --- a/projects/cn0561/zed/system_constr.xdc +++ b/projects/cn0561/zed/system_constr.xdc @@ -1,33 +1,128 @@ ############################################################################### -## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2022-2023, 2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### # cn0561 SPI configuration interface -set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports cn0561_spi_sdi]; ## FMC_LPC_LA03_P -set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports cn0561_spi_sdo]; ## FMC_LPC_LA04_N -set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports cn0561_spi_sclk]; ## FMC_LPC_LA01_P_CC -set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports cn0561_spi_cs]; ## FMC_LPC_LA05_P +set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS18} [get_ports cn0561_spi_sdi]; ## FMC_LPC_LA03_P +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS18} [get_ports cn0561_spi_sdo]; ## FMC_LPC_LA04_N +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS18} [get_ports cn0561_spi_sclk]; ## FMC_LPC_LA01_P_CC +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS18} [get_ports cn0561_spi_cs]; ## FMC_LPC_LA05_P # cn0561 data interface -set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports cn0561_dclk]; ## FMC_LPC_CLK0_M2C_P -set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports cn0561_din[0]]; ## FMC_LPC_LA00_N_CC -set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports cn0561_din[1]]; ## FMC_LPC_LA06_N -set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports cn0561_din[2]]; ## FMC_LPC_LA02_P -set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports cn0561_din[3]]; ## FMC_LPC_LA02_N -set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports cn0561_odr]; ## FMC_LPC_LA00_P_CC +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports cn0561_dclk]; ## FMC_LPC_CLK0_M2C_P +set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports cn0561_din[0]]; ## FMC_LPC_LA00_N_CC +set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports cn0561_din[1]]; ## FMC_LPC_LA06_N +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports cn0561_din[2]]; ## FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports cn0561_din[3]]; ## FMC_LPC_LA02_N +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS18} [get_ports cn0561_odr]; ## FMC_LPC_LA00_P_CC # cn0561 GPIO lines -set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports cn0561_resetn]; ## FMC_LPC_LA16_P -set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports cn0561_pdn]; ## FMC_LPC_LA07_P -set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports cn0561_mode]; ## FMC_LPC_LA04_P -set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports cn0561_gpio0]; ## FMC_LPC_LA10_P -set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports cn0561_gpio1]; ## FMC_LPC_LA10_N -set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25} [get_ports cn0561_gpio2]; ## FMC_LPC_LA11_P -set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports cn0561_gpio4]; ## FMC_LPC_LA12_P -set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports cn0561_gpio5]; ## FMC_LPC_LA12_N -set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports cn0561_gpio6]; ## FMC_LPC_LA13_P -set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports cn0561_gpio7]; ## FMC_LPC_LA13_N -set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports cn0561_pinbspi]; ## FMC_LPC_LA06_P +set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS18} [get_ports cn0561_resetn]; ## FMC_LPC_LA16_P +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS18} [get_ports cn0561_pdn]; ## FMC_LPC_LA07_P +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS18} [get_ports cn0561_mode]; ## FMC_LPC_LA04_P +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS18} [get_ports cn0561_gpio0]; ## FMC_LPC_LA10_P +set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS18} [get_ports cn0561_gpio1]; ## FMC_LPC_LA10_N +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS18} [get_ports cn0561_gpio2]; ## FMC_LPC_LA11_P +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS18} [get_ports cn0561_gpio4]; ## FMC_LPC_LA12_P +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS18} [get_ports cn0561_gpio5]; ## FMC_LPC_LA12_N +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS18} [get_ports cn0561_gpio6]; ## FMC_LPC_LA13_P +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS18} [get_ports cn0561_gpio7]; ## FMC_LPC_LA13_N +set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS18} [get_ports cn0561_pinbspi]; ## FMC_LPC_LA06_P + +# Zedboard common xdc +# set IOSTANDARD according to VADJ 1.8V + +# hdmi + +set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS18} [get_ports hdmi_out_clk] +set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_vsync] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_hsync] +set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data_e] +set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[0]] +set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[1]] +set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[2]] +set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[3]] +set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[4]] +set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[5]] +set_property -dict {PACKAGE_PIN AA16 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[6]] +set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[7]] +set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[8]] +set_property -dict {PACKAGE_PIN Y15 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[9]] +set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[10]] +set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[11]] +set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[12]] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[13]] +set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[14]] +set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[15]] + +# spdif + +set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS18} [get_ports spdif] + +# i2s + +set_property -dict {PACKAGE_PIN AB2 IOSTANDARD LVCMOS18} [get_ports i2s_mclk] +set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVCMOS18} [get_ports i2s_bclk] +set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS18} [get_ports i2s_lrclk] +set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS18} [get_ports i2s_sdata_out] +set_property -dict {PACKAGE_PIN AA7 IOSTANDARD LVCMOS18} [get_ports i2s_sdata_in] + +# iic + +set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS18} [get_ports iic_scl] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS18} [get_ports iic_sda] +set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_mux_scl[1]] +set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_mux_sda[1]] +set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_mux_scl[0]] +set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_mux_sda[0]] + +# otg + +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18} [get_ports otg_vbusoc] + +# gpio (switches, leds and such) + +set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]] ; ## BTNC +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS18} [get_ports gpio_bd[1]] ; ## BTND +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]] ; ## BTNL +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]] ; ## BTNR +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS18} [get_ports gpio_bd[4]] ; ## BTNU +set_property -dict {PACKAGE_PIN U10 IOSTANDARD LVCMOS18} [get_ports gpio_bd[5]] ; ## OLED-DC +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS18} [get_ports gpio_bd[6]] ; ## OLED-RES +set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS18} [get_ports gpio_bd[7]] ; ## OLED-SCLK +set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS18} [get_ports gpio_bd[8]] ; ## OLED-SDIN +set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS18} [get_ports gpio_bd[9]] ; ## OLED-VBAT +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS18} [get_ports gpio_bd[10]] ; ## OLED-VDD + +set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS18} [get_ports gpio_bd[11]] ; ## SW0 +set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS18} [get_ports gpio_bd[12]] ; ## SW1 +set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS18} [get_ports gpio_bd[13]] ; ## SW2 +set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS18} [get_ports gpio_bd[14]] ; ## SW3 +set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS18} [get_ports gpio_bd[15]] ; ## SW4 +set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVCMOS18} [get_ports gpio_bd[16]] ; ## SW5 +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS18} [get_ports gpio_bd[17]] ; ## SW6 +set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS18} [get_ports gpio_bd[18]] ; ## SW7 + +set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS18} [get_ports gpio_bd[19]] ; ## LD0 +set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS18} [get_ports gpio_bd[20]] ; ## LD1 +set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS18} [get_ports gpio_bd[21]] ; ## LD2 +set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS18} [get_ports gpio_bd[22]] ; ## LD3 +set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS18} [get_ports gpio_bd[23]] ; ## LD4 +set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS18} [get_ports gpio_bd[24]] ; ## LD5 +set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS18} [get_ports gpio_bd[25]] ; ## LD6 +set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS18} [get_ports gpio_bd[26]] ; ## LD7 + +set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS18} [get_ports gpio_bd[27]] ; ## XADC-GIO0 +set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS18} [get_ports gpio_bd[28]] ; ## XADC-GIO1 +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports gpio_bd[29]] ; ## XADC-GIO2 +set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS18} [get_ports gpio_bd[30]] ; ## XADC-GIO3 + +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports gpio_bd[31]] ; ## OTG-RESETN + +# Define SPI clock + +create_clock -name spi0_clk -period 40 [get_pins -hier */EMIOSPI0SCLKO] +create_clock -name spi1_clk -period 40 [get_pins -hier */EMIOSPI1SCLKO] diff --git a/projects/cn0561/zed/system_project.tcl b/projects/cn0561/zed/system_project.tcl index fdbdae5d7b..d06fcaf616 100755 --- a/projects/cn0561/zed/system_project.tcl +++ b/projects/cn0561/zed/system_project.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2022-2023, 2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -12,7 +12,6 @@ adi_project cn0561_zed adi_project_files cn0561_zed [list \ "$ad_hdl_dir/library/common/ad_iobuf.v" \ "system_top.v" \ - "system_constr.xdc" \ - "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"] + "system_constr.xdc" ] adi_project_run cn0561_zed