dac_fmc_ebz: vcu118/zc706/zcu102: Replace dacfifo with data_offload

docs/projects/dac_fmc_ebz/index.rst

@@ -69,10 +69,10 @@ DMA source
 
 In cases of high sample rates where the required data rate exceeds the PS-PL
 interface's available throughput, the data is transmitted in a loop from a
-local buffer (:git-hdl:`dac_fifo <projects/dac_fmc_ebz/common/dac_fmc_ebz_bd.tcl#L57>`)
-which is loaded once with the DMA from the PS DDR.
+local buffer (:git-hdl:`data_offload <library/data_offload>`) which is loaded
+once with the DMA data from the PS DDR.
 
-For lower sample rates, the :git-hdl:`DAC FIFO <library/util_dacfifo>`
+For lower sample rates, the :git-hdl:`data_offload <library/data_offload>`
 can be placed in bypass mode, in which case the DMA must stream the data
 from the PS memory.
 
@@ -310,6 +310,7 @@ dac_jesd204_xcvr                     0x44A6_0000      0x84A6_0000
 dac_jesd204_transport                0x44A0_4000      0x84A0_4000
 dac_jesd204_link                     0x44A9_0000      0x84A9_0000
 dac_dma                              0x7C42_0000      0x9C42_0000
+dac_data_offload                     0x7C43_0000      0x9C43_0000
 ===================================  ===============  ===========
 
 =================================== ===========
@@ -372,7 +373,7 @@ GPIOs
 +=================+=================+========+=======+===============+===============+===============+
 | pmod_gpio[3:0]* | INOUT           | 51-48  | ---   | 128-125       | 51-48         | ---           |
 +-----------------+-----------------+--------+-------+---------------+---------------+---------------+
-| dac_fifo_bypass | OUTPUT          | 40     | 40    | 117           | 40            | 8             |
+| dac_fifo_bypass | OUTPUT          | ---    | 40    | ---           | ---           | 8             |
 +-----------------+-----------------+--------+-------+---------------+---------------+---------------+
 | dac_ctrl[4]     | INOUT           | 25     | ---   | 102           | 25            | ---           |
 +-----------------+-----------------+--------+-------+---------------+---------------+---------------+
@@ -536,9 +537,9 @@ HDL related
    * - SYSID_ROM
      - :git-hdl:`library/sysid_rom`
      - :ref:`axi_sysid`
-   * - UTIL_DACFIFO
-     - :git-hdl:`library/util_dacfifo`
-     - ---
+   * - DATA_OFFLOAD
+     - :git-hdl:`library/data_offload`
+     - :ref:`data_offload`
    * - UTIL_UPACK2
      - :git-hdl:`library/util_pack/util_upack2`
      - :ref:`util_cpack2`

projects/dac_fmc_ebz/common/dac_fmc_ebz_bd.tcl

@@ -4,6 +4,7 @@
 ###############################################################################
 
 source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
+source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl
 
 set JESD_M    $ad_project_params(JESD_M)
 set JESD_L    $ad_project_params(JESD_L)
@@ -16,11 +17,9 @@ set SAMPLE_WIDTH $ad_project_params(JESD_NP)
 
 set DAC_DATA_WIDTH [expr $NUM_OF_LANES * 32]
 set SAMPLES_PER_CHANNEL [expr $DAC_DATA_WIDTH / $NUM_OF_CONVERTERS / $SAMPLE_WIDTH]
-
 set MAX_NUM_OF_LANES 8
-# Top level ports
 
-create_bd_port -dir I dac_fifo_bypass
+set dac_offload_name dac_data_offload
 
 # dac peripherals
 
@@ -55,10 +54,15 @@ ad_ip_instance axi_dmac dac_dma [list \
   CACHE_COHERENT $CACHE_COHERENCY \
 ]
 
-ad_dacfifo_create axi_dac_fifo \
-                  $DAC_DATA_WIDTH \
-                  $dac_dma_data_width \
-                  $dac_fifo_address_width
+ad_data_offload_create $dac_offload_name \
+                       1 \
+                       $dac_offload_type \
+                       $dac_offload_size \
+                       $dac_dma_data_width \
+                       $DAC_DATA_WIDTH
+
+ad_ip_parameter $dac_offload_name/i_data_offload CONFIG.SYNC_EXT_ADD_INTERNAL_CDC 0
+ad_connect $dac_offload_name/sync_ext GND
 
 # shared transceiver core
 
@@ -106,28 +110,24 @@ for {set i 0} {$i < $NUM_OF_CONVERTERS} {incr i} {
   ad_connect dac_jesd204_transport/dac_enable_$i  dac_upack/enable_$i
 }
 
-ad_connect util_dac_jesd204_xcvr/tx_out_clk_0 axi_dac_fifo/dac_clk
-ad_connect dac_jesd204_link_rstgen/peripheral_reset axi_dac_fifo/dac_rst
-ad_connect dac_upack/s_axis_valid VCC
-ad_connect dac_upack/s_axis_ready axi_dac_fifo/dac_valid
-ad_connect dac_upack/s_axis_data axi_dac_fifo/dac_data
-ad_connect dac_jesd204_transport/dac_dunf axi_dac_fifo/dac_dunf
-ad_connect sys_cpu_clk axi_dac_fifo/dma_clk
-ad_connect sys_cpu_reset axi_dac_fifo/dma_rst
+ad_connect util_dac_jesd204_xcvr/tx_out_clk_0 $dac_offload_name/m_axis_aclk
+ad_connect dac_jesd204_link_rstgen/peripheral_aresetn $dac_offload_name/m_axis_aresetn
+ad_connect dac_upack/s_axis $dac_offload_name/m_axis
+ad_connect dac_jesd204_transport/dac_dunf dac_upack/fifo_rd_underflow
+ad_connect sys_cpu_clk $dac_offload_name/s_axis_aclk
+ad_connect sys_cpu_resetn $dac_offload_name/s_axis_aresetn
 ad_connect sys_cpu_clk dac_dma/m_axis_aclk
 ad_connect sys_cpu_resetn dac_dma/m_src_axi_aresetn
-ad_connect axi_dac_fifo/dma_xfer_req dac_dma/m_axis_xfer_req
-ad_connect axi_dac_fifo/dma_ready dac_dma/m_axis_ready
-ad_connect axi_dac_fifo/dma_data dac_dma/m_axis_data
-ad_connect axi_dac_fifo/dma_valid dac_dma/m_axis_valid
-ad_connect axi_dac_fifo/dma_xfer_last dac_dma/m_axis_last
+ad_connect $dac_offload_name/init_req dac_dma/m_axis_xfer_req
+ad_connect $dac_offload_name/s_axis dac_dma/m_axis
 
 # interconnect (cpu)
 
 ad_cpu_interconnect 0x44A60000 dac_jesd204_xcvr
 ad_cpu_interconnect 0x44A04000 dac_jesd204_transport
 ad_cpu_interconnect 0x44A90000 dac_jesd204_link
 ad_cpu_interconnect 0x7c420000 dac_dma
+ad_cpu_interconnect 0x7c430000 $dac_offload_name
 
 # interconnect (mem/dac)
 
@@ -143,6 +143,3 @@ if {$CACHE_COHERENCY} {
 
 ad_cpu_interrupt ps-10 mb-15 dac_jesd204_link/irq
 ad_cpu_interrupt ps-12 mb-13 dac_dma/irq
-
-ad_connect axi_dac_fifo/bypass dac_fifo_bypass
-

projects/dac_fmc_ebz/vcu118/Makefile

@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+## Copyright (c) 2018 - 2025 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################
@@ -9,19 +9,22 @@ PROJECT_NAME := dac_fmc_ebz_vcu118
 M_DEPS += ../common/dac_fmc_ebz_bd.tcl
 M_DEPS += ../common/config.tcl
 M_DEPS += ../../scripts/adi_pd.tcl
-M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
 M_DEPS += ../../common/vcu118/vcu118_system_constr.xdc
 M_DEPS += ../../common/vcu118/vcu118_system_bd.tcl
+M_DEPS += ../../common/xilinx/data_offload_bd.tcl
+M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
 M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 
 LIB_DEPS += axi_dmac
 LIB_DEPS += axi_sysid
+LIB_DEPS += data_offload
 LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
 LIB_DEPS += jesd204/axi_jesd204_tx
 LIB_DEPS += jesd204/jesd204_tx
 LIB_DEPS += sysid_rom
-LIB_DEPS += util_dacfifo
+LIB_DEPS += util_do_ram
+LIB_DEPS += util_hbm
 LIB_DEPS += util_pack/util_upack2
 LIB_DEPS += xilinx/axi_adxcvr
 LIB_DEPS += xilinx/util_adxcvr

projects/dac_fmc_ebz/vcu118/system_bd.tcl

@@ -1,12 +1,13 @@
 ###############################################################################
-## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2022-2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
-set dac_fifo_address_width 14
+## Offload attributes
+set dac_offload_type 0                ; ## BRAM
+set dac_offload_size [expr 256*1024]  ; ## 256 kB
 
 source $ad_hdl_dir/projects/common/vcu118/vcu118_system_bd.tcl
-source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
 source ../common/dac_fmc_ebz_bd.tcl
 source $ad_hdl_dir/projects/scripts/adi_pd.tcl
 
@@ -25,7 +26,8 @@ LINKS=$ad_project_params(NUM_LINKS)\
 DEVICE_CODE=$ad_project_params(DEVICE_CODE)\
 DAC_DEVICE=$ADI_DAC_DEVICE\
 DAC_MODE=$ADI_DAC_MODE\
-DAC_FIFO_ADDR_WIDTH=$dac_fifo_address_width"
+DAC_OFFLOAD:TYPE=$dac_offload_type\
+SIZE=$dac_offload_size"
 
 sysid_gen_sys_init_file $sys_cstring
 

projects/dac_fmc_ebz/vcu118/system_top.v

@@ -173,8 +173,6 @@ module system_top #(
   *        3  H14   FMC_TXEN_1   NC
   */
 
-  assign dac_fifo_bypass = gpio_o[40];
-
   /* Board GPIOS. Buttons, LEDs, etc... */
   ad_iobuf #(
     .DATA_WIDTH(17)
@@ -251,7 +249,6 @@ module system_top #(
     .tx_sync_0 (tx_sync),
     .tx_sysref_0 (tx_sysref),
     .uart_sin (uart_sin),
-    .uart_sout (uart_sout),
-    .dac_fifo_bypass (dac_fifo_bypass));
+    .uart_sout (uart_sout));
 
 endmodule

projects/dac_fmc_ebz/zc706/Makefile

@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+## Copyright (c) 2018 - 2025 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################
@@ -11,7 +11,8 @@ M_DEPS += ../common/config.tcl
 M_DEPS += ../../scripts/adi_pd.tcl
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
-M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
+M_DEPS += ../../common/xilinx/data_offload_bd.tcl
+M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
 M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 
@@ -20,11 +21,13 @@ LIB_DEPS += axi_dmac
 LIB_DEPS += axi_hdmi_tx
 LIB_DEPS += axi_spdif_tx
 LIB_DEPS += axi_sysid
+LIB_DEPS += data_offload
 LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
 LIB_DEPS += jesd204/axi_jesd204_tx
 LIB_DEPS += jesd204/jesd204_tx
 LIB_DEPS += sysid_rom
-LIB_DEPS += util_dacfifo
+LIB_DEPS += util_do_ram
+LIB_DEPS += util_hbm
 LIB_DEPS += util_pack/util_upack2
 LIB_DEPS += xilinx/axi_adxcvr
 LIB_DEPS += xilinx/util_adxcvr

projects/dac_fmc_ebz/zc706/system_bd.tcl

@@ -1,12 +1,13 @@
 ###############################################################################
-## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2019-2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
-set dac_fifo_address_width 14
+## Offload attributes
+set dac_offload_type 0                ; ## BRAM
+set dac_offload_size [expr 256*1024]  ; ## 256 kB
 
 source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
-source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
 source ../common/dac_fmc_ebz_bd.tcl
 source $ad_hdl_dir/projects/scripts/adi_pd.tcl
 
@@ -25,7 +26,8 @@ LINKS=$ad_project_params(NUM_LINKS)\
 DEVICE_CODE=$ad_project_params(DEVICE_CODE)\
 DAC_DEVICE=$ADI_DAC_DEVICE\
 DAC_MODE=$ADI_DAC_MODE\
-DAC_FIFO_ADDR_WIDTH=$dac_fifo_address_width"
+DAC_OFFLOAD:TYPE=$dac_offload_type\
+SIZE=$dac_offload_size"
 
 sysid_gen_sys_init_file $sys_cstring
 

projects/dac_fmc_ebz/zc706/system_top.v

@@ -173,8 +173,6 @@ module system_top #(
   *        4  D15   NC           NC
   */
 
-  assign dac_fifo_bypass = gpio_o[40];
-
   /* PMOD GPIOs 48-51 */
   ad_iobuf #(
     .DATA_WIDTH(4)
@@ -273,7 +271,6 @@ module system_top #(
     .tx_ref_clk_0 (tx_ref_clk),
     .tx_ref_clk_4 (tx_ref_clk),
     .tx_sync_0 (tx_sync[NUM_LINKS-1:0]),
-    .tx_sysref_0 (tx_sysref),
-    .dac_fifo_bypass (dac_fifo_bypass));
+    .tx_sysref_0 (tx_sysref));
 
 endmodule

projects/dac_fmc_ebz/zcu102/Makefile

@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+## Copyright (c) 2018 - 2025 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################
@@ -11,17 +11,20 @@ M_DEPS += ../common/config.tcl
 M_DEPS += ../../scripts/adi_pd.tcl
 M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
 M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
-M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
+M_DEPS += ../../common/xilinx/data_offload_bd.tcl
+M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
 M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 
 LIB_DEPS += axi_dmac
 LIB_DEPS += axi_sysid
+LIB_DEPS += data_offload
 LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
 LIB_DEPS += jesd204/axi_jesd204_tx
 LIB_DEPS += jesd204/jesd204_tx
 LIB_DEPS += sysid_rom
-LIB_DEPS += util_dacfifo
+LIB_DEPS += util_do_ram
+LIB_DEPS += util_hbm
 LIB_DEPS += util_pack/util_upack2
 LIB_DEPS += xilinx/axi_adxcvr
 LIB_DEPS += xilinx/util_adxcvr

projects/dac_fmc_ebz/zcu102/system_bd.tcl

@@ -3,11 +3,12 @@
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
-set dac_fifo_address_width 13
+## Offload attributes
+set dac_offload_type 0                ; ## BRAM
+set dac_offload_size [expr 256*1024]  ; ## 256 kB
 
 source $ad_hdl_dir/projects/scripts/adi_pd.tcl
 source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
-source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
 source ../common/dac_fmc_ebz_bd.tcl
 source $ad_hdl_dir/projects/scripts/adi_pd.tcl
 
@@ -51,6 +52,7 @@ LINKS=$ad_project_params(NUM_LINKS)\
 DEVICE_CODE=$ADI_DEVICE_CODE\
 DAC_DEVICE=$ADI_DAC_DEVICE\
 DAC_MODE=$ADI_DAC_MODE\
-DAC_FIFO_ADDR_WIDTH=$dac_fifo_address_width"
+DAC_OFFLOAD:TYPE=$dac_offload_type\
+SIZE=$dac_offload_size"
 
 sysid_gen_sys_init_file $sys_cstring

projects/dac_fmc_ebz/zcu102/system_top.v

@@ -179,8 +179,6 @@ module system_top #(
   *        3  H14   FMC_TXEN_1   NC
   */
 
-  assign dac_fifo_bypass = gpio_o[40];
-
   /* PMOD GPIOs 48-51 */
   ad_iobuf #(
     .DATA_WIDTH(4)
@@ -205,7 +203,6 @@ module system_top #(
   system_wrapper i_system_wrapper (
     .gpio_i (gpio_i),
     .gpio_o (gpio_o),
-    .dac_fifo_bypass(dac_fifo_bypass),
     .spi0_csn (spi0_csn),
     .spi0_miso (spi_miso),
     .spi0_mosi (spi_mosi),