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39 | 39 | #define ADI_AXI_REG_RSTN_MMCM_RSTN BIT(1)
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40 | 40 | #define ADI_AXI_REG_RSTN_RSTN BIT(0)
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41 | 41 |
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| 42 | +#define ADI_AXI_ADC_REG_CONFIG 0x000c |
| 43 | +#define ADI_AXI_ADC_REG_CONFIG_CMOS_OR_LVDS_N BIT(7) |
| 44 | + |
42 | 45 | #define ADI_AXI_ADC_REG_CTRL 0x0044
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43 | 46 | #define ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK BIT(1)
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44 | 47 |
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@@ -233,6 +236,25 @@ static int axi_adc_chan_disable(struct iio_backend *back, unsigned int chan)
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233 | 236 | ADI_AXI_REG_CHAN_CTRL_ENABLE);
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234 | 237 | }
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235 | 238 |
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| 239 | +static int axi_adc_interface_type_get(struct iio_backend *back, |
| 240 | + enum iio_backend_interface_type *type) |
| 241 | +{ |
| 242 | + struct adi_axi_adc_state *st = iio_backend_get_priv(back); |
| 243 | + unsigned int val; |
| 244 | + int ret; |
| 245 | + |
| 246 | + ret = regmap_read(st->regmap, ADI_AXI_ADC_REG_CONFIG, &val); |
| 247 | + if (ret) |
| 248 | + return ret; |
| 249 | + |
| 250 | + if (val & ADI_AXI_ADC_REG_CONFIG_CMOS_OR_LVDS_N) |
| 251 | + *type = IIO_BACKEND_INTERFACE_CMOS; |
| 252 | + else |
| 253 | + *type = IIO_BACKEND_INTERFACE_LVDS; |
| 254 | + |
| 255 | + return 0; |
| 256 | +} |
| 257 | + |
236 | 258 | static struct iio_buffer *axi_adc_request_buffer(struct iio_backend *back,
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237 | 259 | struct iio_dev *indio_dev)
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238 | 260 | {
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@@ -269,6 +291,7 @@ static const struct iio_backend_ops adi_axi_adc_generic = {
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269 | 291 | .iodelay_set = axi_adc_iodelays_set,
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270 | 292 | .test_pattern_set = axi_adc_test_pattern_set,
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271 | 293 | .chan_status = axi_adc_chan_status,
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| 294 | + .interface_type_get = axi_adc_interface_type_get, |
272 | 295 | };
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273 | 296 |
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274 | 297 | static int adi_axi_adc_probe(struct platform_device *pdev)
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