How to replace capacitor by port in HFSS 3D Layout, run simulation, export S parameter and create circuit schematic

[amichel0205]

Here the goal is to provide two scripts and their associated toml file(for script input) to be used for a worfklow to:

1. Use an HFSS 3D Layout project as input with a list of capacitors
2. Create a new project where capacitor from the list will be replace by port
3. Run simulation of the new project
4. Export S parameter from the solved project
5. Create a schematic with S parameter
6. Connect capacitors from the list in circuit schematic to S parameter block relevant pins

First: script and toml file to achieve capacitor by port replacement are provide below:

Toml file "Convert_cap_to_port.toml" must be placed in PersonalLib.
In listcap provide property "Name" of capacitors to replace by port:

[path]
# Path of the aedb directory of the project to replace capacitors by port
edbfilein = "C:\\temp\\SVP_V1_1_TX.aedb"

[rlc]
# list of capacitor  Name to convert to port
listcap = ["C375", "C376", "C379", "C380", "C373", "C374"]

[aedt]
# Version of AEDT, edb to be used "2023.2" for 2023R2, "2024.1" for 2024R1
version = "2025.2"
# true to run analysis. Once simulation completed  S parameter is exported 
# Requested original project to have a setup defined.
runanalysis = true

With this toml file the project with capacitors is named SVP_V1_1_TX and located in C:/Temp
A new project SVP_V1_1_TX_RLCtoP will be created in C:/Temp where Capacitor C375, C376, C379, C380, C373, C374 will be replace by ports.
If runanalisys is false script stopped after project creation.
If runanalysis is true the new created project is simulated and S parameter named SVP_V1_1_TX.snp is created
Original project with capacitor must have a setup such the setup is reused in new created project. If not simulation and export S parameter step is skipped even if runanalysis is true.

import os
from pyedb import Edb
from ansys.aedt.core import Hfss3dLayout
from ansys.aedt.core import Circuit
from ansys.aedt.core import Desktop
import toml

aedttmp = Desktop(non_graphical=True)
personallib = aedttmp.personallib
print(personallib)
aedttmp.close_desktop()

print("This toml file will be used to specify inputs : ", os.path.join(personallib,"Convert_cap_to_port.toml"))

# Setting of toml configuration file used to set a dictionary
res = toml.load(os.path.join(personallib,"Convert_cap_to_port.toml"))

# Path of the aedb directory to convert
edb_file_in = res['path']['edbfilein']
# list of capacitor to convert to port
list_cap = res['rlc']['listcap']
# Version of AEDT, edb to be used "2024.2" for 2024R2, "2025.2" for 2025R2 and so on
version = res['aedt']['version']
run_analysis = res['aedt']['runanalysis']

list_of_cap_val = []

file_path, extension = os.path.splitext(edb_file_in)

edb_file_out = f"{file_path}_RLCtoP.aedb"
aedt_filepath = f"{file_path}_RLCtoP.aedt"
circuit_filepath = f"{file_path}_RLCtoP_sch.aedt"


edb = Edb(edbpath=edb_file_in, version=version, grpc=True)

for ref_des in list_cap:
    print(ref_des)
    list_of_cap_val.append((edb.components.capacitors[ref_des].rlc_values, ref_des))
    if not edb.components.deactivate_rlc_component(component=ref_des, create_circuit_port=True):
        edb.logger.warning(f"Failed converting capacitor {ref_des} into port")
edb.save_as(edb_file_out)
edb.close()

h3d = Hfss3dLayout(projectname=edb_file_out, specified_version=version, non_graphical=False)

if run_analysis:
    if len(h3d.setups) != 0:
        setup = h3d.setups[0]
        # run analysis
        h3d.analyze_setup(name=setup.name)
        print("analysis done")
        file_path, extension = os.path.splitext(aedt_filepath)
        touchstone_path = f"{file_path}.s{len(h3d.port_list)}p"
        # Export S parameter file
        h3d.export_touchstone(setup_name=setup.name, sweep_name=h3d.get_sweeps(setup.name)[0],
                              file_name=touchstone_path,
                              gamma_impedance_comments=False)
    else:
        print("No setup exists, simulation can't run, however project will be saved")

h3d.save_project()
h3d.desktop_class.release_desktop(close_projects=False, close_on_exit=False)

Let say that simulation of the new created project was done and an S parameter named was exported SVP_V1_1_TX_RLCtoP.s18p. The second will be to create a schematic with S parameter and capacitors.

Second: script and toml file to create schematic:

Toml file "Create_Ciruit_from_Sparameter.toml" must be placed in PersonalLib.

[path]
# Path of the aedb directory of original project with capacitors
edbfilein = "C:\\temp\\SVP_V1_1_TX.aedb"
# Path to the S parameter file
sparameterfile = "C:\\temp\\SVP_V1_1_TX_RLCtoP.s18p"

[rlc]
# list of capacitor to convert to port
listcap = ["C375", "C376", "C379", "C380", "C373", "C374"]


[aedt]
# Version of AEDT, edb to be used "2023.2" for 2023R2, "2024.1" for 2024R1
version = "2025.2"

With this toml file, below script will:

• Get value of capacitors from "listcap" in original project named SVP_V1_1_TX located in C:/Temp
• Create a circuit design named SVP_V1_1_TX_RLCtoP_sch.aedt located in C:/Temp
• Import S parameter in circuit schematic and connect ports and capacitors

import os
from pyedb import Edb
from ansys.aedt.core import Circuit
from ansys.aedt.core import Desktop
import toml

aedttmp = Desktop(non_graphical=True)
personallib = aedttmp.personallib
print(personallib)
aedttmp.close_desktop()

print("This toml file will be used to create circuit from S parameter ",
      os.path.join(personallib,"Create_Ciruit_from_Sparameter.toml"))

# Setting of toml configuration file used to set a dictionary
res = toml.load(os.path.join(personallib,"Create_Ciruit_from_Sparameter.toml"))

# Path of the aedb directory to convert
edb_file_in = res['path']['edbfilein']
# Path to the S parameter file
touchstone_path = res['path']['sparameterfile']
# list of capacitor to convert to port
list_cap = res['rlc']['listcap']
# Version of AEDT, edb to be used "2024.2" for 2024R2, "2025.2" for 2025R2 and so on
version = res['aedt']['version']

list_of_cap_val = []

file_path, extension = os.path.splitext(touchstone_path)
circuit_filepath = f"{file_path}_RLCtoP_sch.aedt"


# Get properties of capacitor from original aedt project
edb = Edb(edbpath=edb_file_in, version=version, grpc=True)
for ref_des in list_cap:
    list_of_cap_val.append((edb.components.capacitors[ref_des].rlc_values, ref_des))
edb.close()

# Create Schematic
circuit = Circuit(specified_version=version, projectname=circuit_filepath, non_graphical=False, designname="circuit",
                  new_desktop_session=True)
circuit.modeler.schematic_units = "mil"
circuit_comp = circuit.modeler.components.create_touchstone_component(touchstone_path, location=[0.0, 0.0],
                                                                      show_bitmap=False)
# connect nport sparameter and port, components
shift_x_position_port = 1500
shift_x_position_cap = 500
for pin in circuit_comp.pins:
    component = next((x for x in list_cap if x == pin.name), None)
    if component:
        for cap_name in list_of_cap_val:
            if cap_name[1] == pin.name:
                print(cap_name[1], cap_name[0][2])
                if pin.location[0] < 0.0:
                    position_x_cap = pin.location[0] - shift_x_position_cap
                    position_x_gnd = pin.location[0] - shift_x_position_port
                    pin_index_l = 1
                    pin_index_r = 0
                    gnd_angle = 270
                    shift_x_gnd = 100
                else:
                    position_x_cap = pin.location[0] + shift_x_position_cap
                    position_x_gnd = pin.location[0] + shift_x_position_port
                    angle = 180
                    pin_index_l = 0
                    pin_index_r = 1
                    gnd_angle = 90
                    shift_x_gnd = -100

                c1 = circuit.modeler.schematic.create_capacitor(value=cap_name[0][2], name=cap_name[1],
                                                                location=[position_x_cap, pin.location[1]])
                pin.connect_to_component(c1.pins[pin_index_l], use_wire=True)
                gnd = circuit.modeler.components.create_gnd(location=[position_x_gnd, pin.location[1]], angle=gnd_angle)
                points = [[(gnd.pins[0].location[0]+shift_x_gnd), pin.location[1]], c1.pins[pin_index_r].location]
                circuit.modeler.components.create_wire(points=points)

    else:
        if pin.location[0] < 0.0:
            position_x = pin.location[0] - shift_x_position_port
            angle = 90
        else:
            position_x = pin.location[0] + shift_x_position_port
            angle = 180
        i_port = circuit.modeler.components.create_interface_port(
            name=pin.name,
            location=[position_x, pin.location[1]],
            angle=angle)
        pin.connect_to_component(i_port.pins[0], use_wire=True)

circuit.save_project()
circuit.release_desktop(close_projects=False, close_desktop=False)

User will have to add the simulation setup in the circuit project.

You use it as it is or add your own piece of code.

Below you can see screenshot of:

1. Original HFSS 3D Layout project
2. New created project with capacitors replace by port
3. Circuit project

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