Commit 768106a
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Bumps [third-party/verilator/master](https://github.com/verilator/verilator) from `fbb195e` to `eb40c24`.
- [Commits](verilator/verilator@fbb195e...eb40c24)
---
updated-dependencies:
- dependency-name: third-party/verilator/master
dependency-version: eb40c24b78769dee47c8f08db3b41dfb346ccce7
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <[email protected]>
Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com>
1 parent 838f192 commit 768106a
1 file changed
+1
-1
lines changed- src/V3EmitCImp.cpp+1-1
- src/V3Expand.cpp+5
- src/V3Slice.cpp+1
- src/V3Timing.cpp+4
- src/verilog.y+1-1
- test_regress/t/t_always_chg_first.py
- test_regress/t/t_always_chg_first.v
- test_regress/t/t_array_sel_wide.py
- test_regress/t/t_array_sel_wide.v
- test_regress/t/t_benchmark_mux4k.py
- test_regress/t/t_benchmark_mux4k.v
- test_regress/t/t_benchmark_mux4k_onecpu.py+1-1
- test_regress/t/t_benchmark_sim.py
- test_regress/t/t_clk_gated_1.py
- test_regress/t/t_clk_gated_1.v
- test_regress/t/t_clocking_bad2.out+4-4
- test_regress/t/t_comb_do_not_convert_to.py
- test_regress/t/t_comb_do_not_convert_to.v
- test_regress/t/t_delay_1step.py+18
- test_regress/t/t_delay_1step.v+20
- test_regress/t/t_display_format_wide_decimal.out
- test_regress/t/t_display_format_wide_decimal.py+1-1
- test_regress/t/t_display_format_wide_decimal.v+1-1
- test_regress/t/t_do_while_continue_bad.out+1-1
- test_regress/t/t_do_while_continue_bad.py
- test_regress/t/t_do_while_continue_bad.v
- test_regress/t/t_do_while_jumps.py
- test_regress/t/t_do_while_jumps.v
- test_regress/t/t_driver_timeout.py
- test_regress/t/t_dump_dfg.py+1-1
- test_regress/t/t_flag_expand_limit.py+1-1
- test_regress/t/t_flag_expand_limit.v+18-1
- test_regress/t/t_flag_output_groups.py
- test_regress/t/t_flag_output_groups.v
- test_regress/t/t_gen_duplicated_blocks_bad.out+4-4
- test_regress/t/t_gen_duplicated_blocks_bad.py
- test_regress/t/t_gen_duplicated_blocks_bad.v
- test_regress/t/t_hier_block.v+18
- test_regress/t/t_hier_block_sc_trace_fst.out+5.7k-5.6k
- test_regress/t/t_hier_block_sc_trace_vcd.out+5.7k-5.7k
- test_regress/t/t_hier_block_trace_fst.out+5.7k-5.6k
- test_regress/t/t_hier_block_trace_saif.out+1.1k
- test_regress/t/t_hier_block_trace_vcd.out+5.7k-5.7k
- test_regress/t/t_mem.v+4
- test_regress/t/t_mem_big_bad.out+4-4
- test_regress/t/t_mem_big_bad.py
- test_regress/t/t_mem_big_bad.v
- test_regress/t/t_opt_dedupe_clk_gate.py
- test_regress/t/t_opt_dedupe_clk_gate.v
- test_regress/t/t_opt_dedupe_clk_gate_off.py+1-1
- test_regress/t/t_opt_dedupe_seq_logic.py
- test_regress/t/t_opt_dedupe_seq_logic.v
- test_regress/t/t_opt_table_fsm.py
- test_regress/t/t_opt_table_fsm.v
- test_regress/t/t_param_default_2.py
- test_regress/t/t_param_default_2.v
- test_regress/t/t_scope_cxx_equal_to.py-1
- test_regress/t/t_scope_cxx_equal_to.v
- test_regress/t/t_string_convert2.py
- test_regress/t/t_string_convert2.v
- test_regress/t/t_trace_jumps_do_while_saif.py+1-1
- test_regress/t/t_upd_nonsequential.py
- test_regress/t/t_upd_nonsequential.v
- test_regress/t/t_var_rsvd_port.v+1
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