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jamesmunnstmplt
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add pmc, efc modules from @jamesmunns's work
Sourced from [0]; /vendor/asamx7x-hal. [0] jamesmunns/same70-experiments@a6d1fe1
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hal/src/efc.rs

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//! Flash block configuration
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use crate::target_device::EFC;
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use crate::pmc::PmcError;
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pub struct Efc {
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pub(crate) periph: EFC,
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}
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impl Efc {
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pub fn new(periph: EFC) -> Self {
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periph.eefc_wpmr.modify(|_r, w| {
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w.wpkey().passwd();
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w.wpen().clear_bit();
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w
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});
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Self { periph }
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}
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pub fn set_wait_states(&mut self, fws: FlashWaitStates) {
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let fws_bits = fws as u8;
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self.periph
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.eefc_fmr
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.modify(|_r, w| unsafe { w.fws().bits(fws_bits) });
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}
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}
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/// The number of flash wait states for a read operation.
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///
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/// Note: The number of cycles a read takes is 1 + FWS.
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#[derive(Debug, PartialEq, Copy, Clone)]
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#[repr(u8)]
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pub enum FlashWaitStates {
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Zero,
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One,
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Two,
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Three,
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Four,
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Five,
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Six,
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}
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impl FlashWaitStates {
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/// Calculate the lowest possible number of flash wait states from a given
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/// peripheral clock frequency in MHz.
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///
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/// The max PCLK frequency supported is 150MHz. This is *not* the CPU frequency,
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/// which may go up to 300MHz.
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///
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/// Note: This is probably only valid at VDDIO = 3.0V
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pub fn from_pclk_mhz(freq: u8) -> Result<Self, PmcError> {
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// Reference: Table 58-51 Embedded Flash Wait States for Worst-Case Conditions
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let fws = match freq {
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0..=23 => Self::Zero,
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24..=46 => Self::One,
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47..=69 => Self::Two,
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70..=92 => Self::Three,
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93..=115 => Self::Four,
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116..=138 => Self::Five,
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139..=150 => Self::Six,
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_ => return Err(PmcError::InvalidConfiguration),
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};
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Ok(fws)
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}
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}

hal/src/lib.rs

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@@ -145,3 +145,7 @@ pub use atsamv71q21b as target_device;
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pub mod serial;
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#[cfg(feature = "rev-b")]
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pub mod watchdog;
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#[cfg(feature = "rev-b")]
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pub mod pmc;
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#[cfg(feature = "rev-b")]
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pub mod efc;

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