picchio/gpu_native_ptx.inc at main · benmaster82/picchio · GitHub

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"//\n"
"// Generated by NVIDIA NVVM Compiler\n"
"//\n"
"// Compiler Build ID: CL-35059454\n"
"// Cuda compilation tools, release 12.6, V12.6.85\n"
"// Based on NVVM 7.0.1\n"
"//\n"
"\n"
".version 8.5\n"
".target sm_75\n"
".address_size 64\n"
"\n"
"\t// .globl\tpicchio_router_f32\n"
"// _ZZ18picchio_router_f32E2sm has been demoted\n"
"// _ZZ17picchio_dense_f16E2sm has been demoted\n"
"\n"
".visible .entry picchio_router_f32(\n"
"\t.param .u64 picchio_router_f32_param_0,\n"
"\t.param .u64 picchio_router_f32_param_1,\n"
"\t.param .u64 picchio_router_f32_param_2,\n"
"\t.param .u64 picchio_router_f32_param_3,\n"
"\t.param .u32 picchio_router_f32_param_4,\n"
"\t.param .u32 picchio_router_f32_param_5\n"
")\n"
"{\n"
"\t.reg .pred \t%p<9>;\n"
"\t.reg .f32 \t%f<19>;\n"
"\t.reg .b32 \t%r<15>;\n"
"\t.reg .b64 \t%rd<28>;\n"
"\t// demoted variable\n"
"\t.shared .align 4 .b8 _ZZ18picchio_router_f32E2sm[1024];\n"
"\n"
"\tld.param.u64 \t%rd6, [picchio_router_f32_param_0];\n"
"\tld.param.u64 \t%rd7, [picchio_router_f32_param_1];\n"
"\tld.param.u64 \t%rd8, [picchio_router_f32_param_2];\n"
"\tld.param.u64 \t%rd9, [picchio_router_f32_param_3];\n"
"\tld.param.u32 \t%r10, [picchio_router_f32_param_4];\n"
"\tld.param.u32 \t%r9, [picchio_router_f32_param_5];\n"
"\tmov.u32 \t%r1, %ctaid.x;\n"
"\tsetp.ge.s32 \t%p1, %r1, %r10;\n"
"\t@%p1 bra \t$L__BB0_13;\n"
"\n"
"\tcvt.s64.s32 \t%rd1, %r1;\n"
"\tmov.u32 \t%r2, %tid.x;\n"
"\tsetp.lt.s32 \t%p2, %r2, %r9;\n"
"\t@%p2 bra \t$L__BB0_3;\n"
"\tbra.uni \t$L__BB0_2;\n"
"\n"
"$L__BB0_3:\n"
"\tmov.u32 \t%r3, %ntid.x;\n"
"\tcvta.to.global.u64 \t%rd2, %rd6;\n"
"\tcvta.to.global.u64 \t%rd3, %rd8;\n"
"\tcvt.s64.s32 \t%rd10, %r9;\n"
"\tmul.lo.s64 \t%rd4, %rd10, %rd1;\n"
"\tmov.f32 \t%f17, 0f00000000;\n"
"\tmov.u32 \t%r13, %r2;\n"
"\n"
"$L__BB0_4:\n"
"\tcvt.s64.s32 \t%rd11, %r13;\n"
"\tmul.wide.s32 \t%rd12, %r13, 4;\n"
"\tadd.s64 \t%rd13, %rd3, %rd12;\n"
"\tadd.s64 \t%rd14, %rd4, %rd11;\n"
"\tshl.b64 \t%rd15, %rd14, 2;\n"
"\tadd.s64 \t%rd16, %rd2, %rd15;\n"
"\tld.global.nc.f32 \t%f9, [%rd16];\n"
"\tld.global.nc.f32 \t%f10, [%rd13];\n"
"\tfma.rn.f32 \t%f17, %f10, %f9, %f17;\n"
"\tadd.s32 \t%r13, %r13, %r3;\n"
"\tsetp.lt.s32 \t%p3, %r13, %r9;\n"
"\t@%p3 bra \t$L__BB0_4;\n"
"\tbra.uni \t$L__BB0_5;\n"
"\n"
"$L__BB0_2:\n"
"\tmov.f32 \t%f17, 0f00000000;\n"
"\n"
"$L__BB0_5:\n"
"\tmul.wide.u32 \t%rd17, %r2, 4;\n"
"\tmov.u64 \t%rd18, _ZZ18picchio_router_f32E2sm;\n"
"\tadd.s64 \t%rd5, %rd18, %rd17;\n"
"\tst.shared.f32 \t[%rd5], %f17;\n"
"\tbar.sync \t0;\n"
"\tmov.u32 \t%r11, %ntid.x;\n"
"\tshr.u32 \t%r14, %r11, 1;\n"
"\tsetp.eq.s32 \t%p4, %r14, 0;\n"
"\t@%p4 bra \t$L__BB0_9;\n"
"\n"
"$L__BB0_6:\n"
"\tsetp.ge.u32 \t%p5, %r2, %r14;\n"
"\t@%p5 bra \t$L__BB0_8;\n"
"\n"
"\tadd.s32 \t%r12, %r14, %r2;\n"
"\tmul.wide.u32 \t%rd19, %r12, 4;\n"
"\tadd.s64 \t%rd21, %rd18, %rd19;\n"
"\tld.shared.f32 \t%f11, [%rd5];\n"
"\tld.shared.f32 \t%f12, [%rd21];\n"
"\tadd.f32 \t%f13, %f12, %f11;\n"
"\tst.shared.f32 \t[%rd5], %f13;\n"
"\n"
"$L__BB0_8:\n"
"\tbar.sync \t0;\n"
"\tshr.u32 \t%r14, %r14, 1;\n"
"\tsetp.ne.s32 \t%p6, %r14, 0;\n"
"\t@%p6 bra \t$L__BB0_6;\n"
"\n"
"$L__BB0_9:\n"
"\tsetp.ne.s32 \t%p7, %r2, 0;\n"
"\t@%p7 bra \t$L__BB0_13;\n"
"\n"
"\tld.shared.f32 \t%f4, [_ZZ18picchio_router_f32E2sm];\n"
"\tsetp.eq.s64 \t%p8, %rd7, 0;\n"
"\tmov.f32 \t%f18, 0f00000000;\n"
"\t@%p8 bra \t$L__BB0_12;\n"
"\n"
"\tcvta.to.global.u64 \t%rd22, %rd7;\n"
"\tshl.b64 \t%rd23, %rd1, 2;\n"
"\tadd.s64 \t%rd24, %rd22, %rd23;\n"
"\tld.global.nc.f32 \t%f18, [%rd24];\n"
"\n"
"$L__BB0_12:\n"
"\tcvta.to.global.u64 \t%rd25, %rd9;\n"
"\tshl.b64 \t%rd26, %rd1, 2;\n"
"\tadd.s64 \t%rd27, %rd25, %rd26;\n"
"\tadd.f32 \t%f15, %f4, %f18;\n"
"\tst.global.f32 \t[%rd27], %f15;\n"
"\n"
"$L__BB0_13:\n"
"\tret;\n"
"\n"
"}\n"
"\t// .globl\tpicchio_dense_f16\n"
".visible .entry picchio_dense_f16(\n"
"\t.param .u64 picchio_dense_f16_param_0,\n"
"\t.param .u64 picchio_dense_f16_param_1,\n"
"\t.param .u64 picchio_dense_f16_param_2,\n"
"\t.param .u32 picchio_dense_f16_param_3,\n"
"\t.param .u32 picchio_dense_f16_param_4\n"
")\n"
"{\n"
"\t.reg .pred \t%p<8>;\n"
"\t.reg .b16 \t%rs<2>;\n"
"\t.reg .f32 \t%f<14>;\n"
"\t.reg .b32 \t%r<15>;\n"
"\t.reg .b64 \t%rd<24>;\n"
"\t// demoted variable\n"
"\t.shared .align 4 .b8 _ZZ17picchio_dense_f16E2sm[1024];\n"
"\n"
"\tld.param.u64 \t%rd6, [picchio_dense_f16_param_0];\n"
"\tld.param.u64 \t%rd7, [picchio_dense_f16_param_1];\n"
"\tld.param.u64 \t%rd8, [picchio_dense_f16_param_2];\n"
"\tld.param.u32 \t%r10, [picchio_dense_f16_param_3];\n"
"\tld.param.u32 \t%r9, [picchio_dense_f16_param_4];\n"
"\tmov.u32 \t%r1, %ctaid.x;\n"
"\tsetp.ge.s32 \t%p1, %r1, %r10;\n"
"\t@%p1 bra \t$L__BB1_11;\n"
"\n"
"\tcvt.s64.s32 \t%rd1, %r1;\n"
"\tmov.u32 \t%r2, %tid.x;\n"
"\tsetp.lt.s32 \t%p2, %r2, %r9;\n"
"\t@%p2 bra \t$L__BB1_3;\n"
"\tbra.uni \t$L__BB1_2;\n"
"\n"
"$L__BB1_3:\n"
"\tmov.u32 \t%r3, %ntid.x;\n"
"\tcvta.to.global.u64 \t%rd2, %rd6;\n"
"\tcvta.to.global.u64 \t%rd3, %rd7;\n"
"\tcvt.s64.s32 \t%rd9, %r9;\n"
"\tmul.lo.s64 \t%rd4, %rd9, %rd1;\n"
"\tmov.f32 \t%f13, 0f00000000;\n"
"\tmov.u32 \t%r13, %r2;\n"
"\n"
"$L__BB1_4:\n"
"\tcvt.s64.s32 \t%rd10, %r13;\n"
"\tmul.wide.s32 \t%rd11, %r13, 4;\n"
"\tadd.s64 \t%rd12, %rd3, %rd11;\n"
"\tld.global.nc.f32 \t%f7, [%rd12];\n"
"\tadd.s64 \t%rd13, %rd4, %rd10;\n"
"\tshl.b64 \t%rd14, %rd13, 1;\n"
"\tadd.s64 \t%rd15, %rd2, %rd14;\n"
"\tld.global.nc.u16 \t%rs1, [%rd15];\n"
"\t// begin inline asm\n"
"\t{  cvt.f32.f16 %f6, %rs1;}\n"
"\n"
"\t// end inline asm\n"
"\tfma.rn.f32 \t%f13, %f7, %f6, %f13;\n"
"\tadd.s32 \t%r13, %r13, %r3;\n"
"\tsetp.lt.s32 \t%p3, %r13, %r9;\n"
"\t@%p3 bra \t$L__BB1_4;\n"
"\tbra.uni \t$L__BB1_5;\n"
"\n"
"$L__BB1_2:\n"
"\tmov.f32 \t%f13, 0f00000000;\n"
"\n"
"$L__BB1_5:\n"
"\tmul.wide.u32 \t%rd16, %r2, 4;\n"
"\tmov.u64 \t%rd17, _ZZ17picchio_dense_f16E2sm;\n"
"\tadd.s64 \t%rd5, %rd17, %rd16;\n"
"\tst.shared.f32 \t[%rd5], %f13;\n"
"\tbar.sync \t0;\n"
"\tmov.u32 \t%r11, %ntid.x;\n"
"\tshr.u32 \t%r14, %r11, 1;\n"
"\tsetp.eq.s32 \t%p4, %r14, 0;\n"
"\t@%p4 bra \t$L__BB1_9;\n"
"\n"
"$L__BB1_6:\n"
"\tsetp.ge.u32 \t%p5, %r2, %r14;\n"
"\t@%p5 bra \t$L__BB1_8;\n"
"\n"
"\tadd.s32 \t%r12, %r14, %r2;\n"
"\tmul.wide.u32 \t%rd18, %r12, 4;\n"
"\tadd.s64 \t%rd20, %rd17, %rd18;\n"
"\tld.shared.f32 \t%f8, [%rd5];\n"
"\tld.shared.f32 \t%f9, [%rd20];\n"
"\tadd.f32 \t%f10, %f9, %f8;\n"
"\tst.shared.f32 \t[%rd5], %f10;\n"
"\n"
"$L__BB1_8:\n"
"\tbar.sync \t0;\n"
"\tshr.u32 \t%r14, %r14, 1;\n"
"\tsetp.ne.s32 \t%p6, %r14, 0;\n"
"\t@%p6 bra \t$L__BB1_6;\n"
"\n"
"$L__BB1_9:\n"
"\tsetp.ne.s32 \t%p7, %r2, 0;\n"
"\t@%p7 bra \t$L__BB1_11;\n"
"\n"
"\tld.shared.f32 \t%f11, [_ZZ17picchio_dense_f16E2sm];\n"
"\tcvta.to.global.u64 \t%rd21, %rd8;\n"
"\tshl.b64 \t%rd22, %rd1, 2;\n"
"\tadd.s64 \t%rd23, %rd21, %rd22;\n"
"\tst.global.f32 \t[%rd23], %f11;\n"
"\n"
"$L__BB1_11:\n"
"\tret;\n"
"\n"
"}\n"
"\n"