M1 ultra 128GB issus

[honeyxiaoding]

no dflash, Qwen3.6-27B-bf16, ~10.7 tok/s
with dflash, Draft Model:Qwen3.6-27B-DFlash, Draft Quantization:bf16, ~7tok/s

no dflash, Qwen3.6-35B-A3B-bf16 ~53 tok/s
with dflash, Draft Model:Qwen3.6-35B-A3B-DFlash, Draft Quantization:bf16, ~12tok/s

[bstnxbt]

Thanks for the numbers. I am going to keep this open as a perf/config issue, but I need one more round with exact commands/artifacts before treating it as a runtime bug.

Important distinction: the current optimized DFlash path for the large Qwen3.6 models is not bf16 draft. The registry defaults large drafts to w4, and Qwen3.6-35B-A3B also has a target policy default for split-SDPA. A bf16 draft run is a useful A/B, but it is much heavier and can be slower than baseline.

Please retest with the canonical benchmark command shape, for example:

dflash benchmark \
  --model mlx-community/Qwen3.6-27B-4bit \
  --draft z-lab/Qwen3.6-27B-DFlash \
  --max-tokens 1024 \
  --repeat 1 \
  --cooldown 180 \
  --no-eos

# and for MoE:
dflash benchmark \
  --model mlx-community/Qwen3.6-35B-A3B-4bit \
  --draft z-lab/Qwen3.6-35B-A3B-DFlash \
  --max-tokens 1024 \
  --repeat 1 \
  --cooldown 180 \
  --no-eos

Then paste the generated results.json summary plus:

dflash doctor --json

If you intentionally want the bf16 draft comparison, please include the exact --draft-quant none / bf16 command too, but I would track that separately from the default product path. On my side, the current 4bit+w4 benchmark path is not showing the DFlash < baseline behavior for Qwen3.6 27B, and the 35B-A3B result is very sensitive to whether split-SDPA is active.