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| 1 | +//! Contains xtensa-specific types |
| 2 | +
|
| 3 | +use core::convert::{From, TryInto}; |
| 4 | +use core::{cmp, fmt, slice}; |
| 5 | + |
| 6 | +pub use capstone_sys::xtensa_insn as XtensaInsn; |
| 7 | +pub use capstone_sys::xtensa_reg as XtensaReg; |
| 8 | +use capstone_sys::{ |
| 9 | + cs_ac_type, cs_xtensa, cs_xtensa_op, cs_xtensa_op_mem, cs_xtensa_op_type, |
| 10 | + cs_xtensa_operand__bindgen_ty_1, |
| 11 | +}; |
| 12 | + |
| 13 | +pub use crate::arch::arch_builder::xtensa::*; |
| 14 | +use crate::arch::DetailsArchInsn; |
| 15 | +use crate::instruction::{RegId, RegIdInt}; |
| 16 | +use crate::RegAccessType; |
| 17 | + |
| 18 | +/// Contains xtensa-specific details for an instruction |
| 19 | +pub struct XtensaInsnDetail<'a>(pub(crate) &'a cs_xtensa); |
| 20 | + |
| 21 | +impl_PartialEq_repr_fields!(XtensaInsnDetail<'a> [ 'a ]; |
| 22 | + operands |
| 23 | +); |
| 24 | + |
| 25 | +/// xtensa operand |
| 26 | +#[derive(Clone, Debug, Eq, PartialEq, Default)] |
| 27 | +pub struct XtensaOperand { |
| 28 | + /// Operand type |
| 29 | + pub op_type: XtensaOperandType, |
| 30 | + |
| 31 | + /// How is this operand accessed? |
| 32 | + /// |
| 33 | + /// NOTE: this field is always `None` if the "full" feataure is not enabled. |
| 34 | + pub access: Option<RegAccessType>, |
| 35 | +} |
| 36 | + |
| 37 | +impl From<&cs_xtensa_op> for XtensaOperand { |
| 38 | + fn from(op: &cs_xtensa_op) -> XtensaOperand { |
| 39 | + let op_type = XtensaOperandType::new(op.type_, op.__bindgen_anon_1); |
| 40 | + XtensaOperand { |
| 41 | + op_type, |
| 42 | + access: cs_ac_type(op.access as _).try_into().ok(), |
| 43 | + } |
| 44 | + } |
| 45 | +} |
| 46 | + |
| 47 | +/// Xtensa operand |
| 48 | +#[derive(Clone, Debug, PartialEq)] |
| 49 | +pub enum XtensaOperandType { |
| 50 | + /// Register |
| 51 | + Reg(RegId), |
| 52 | + |
| 53 | + /// Immediate |
| 54 | + Imm(i32), |
| 55 | + |
| 56 | + /// Memory |
| 57 | + Mem(XtensaOpMem), |
| 58 | + |
| 59 | + /// Memory register |
| 60 | + MemReg(RegId), |
| 61 | + |
| 62 | + /// Memory immediate |
| 63 | + MemImm(i32), |
| 64 | + |
| 65 | + /// L32R target |
| 66 | + L32R(i32), |
| 67 | + |
| 68 | + /// Invalid |
| 69 | + Invalid, |
| 70 | +} |
| 71 | + |
| 72 | +impl XtensaOperandType { |
| 73 | + fn new(op_type: u8, value: cs_xtensa_operand__bindgen_ty_1) -> XtensaOperandType { |
| 74 | + match op_type as u32 { |
| 75 | + cs_xtensa_op_type::XTENSA_OP_REG => { |
| 76 | + XtensaOperandType::Reg(RegId(unsafe { value.reg } as RegIdInt)) |
| 77 | + } |
| 78 | + cs_xtensa_op_type::XTENSA_OP_IMM => XtensaOperandType::Imm(unsafe { value.imm }), |
| 79 | + cs_xtensa_op_type::XTENSA_OP_MEM => { |
| 80 | + XtensaOperandType::Mem(XtensaOpMem(unsafe { value.mem })) |
| 81 | + } |
| 82 | + cs_xtensa_op_type::XTENSA_OP_MEM_REG => { |
| 83 | + XtensaOperandType::MemReg(RegId(unsafe { value.reg } as RegIdInt)) |
| 84 | + } |
| 85 | + cs_xtensa_op_type::XTENSA_OP_MEM_IMM => XtensaOperandType::MemImm(unsafe { value.imm }), |
| 86 | + cs_xtensa_op_type::XTENSA_OP_L32R => XtensaOperandType::L32R(unsafe { value.imm }), |
| 87 | + _ => XtensaOperandType::Invalid, |
| 88 | + } |
| 89 | + } |
| 90 | +} |
| 91 | + |
| 92 | +impl cmp::Eq for XtensaOperandType {} |
| 93 | + |
| 94 | +impl Default for XtensaOperandType { |
| 95 | + fn default() -> Self { |
| 96 | + XtensaOperandType::Invalid |
| 97 | + } |
| 98 | +} |
| 99 | + |
| 100 | +/// xtensa memory operand |
| 101 | +#[derive(Debug, Copy, Clone)] |
| 102 | +pub struct XtensaOpMem(pub(crate) cs_xtensa_op_mem); |
| 103 | + |
| 104 | +impl XtensaOpMem { |
| 105 | + /// Base register |
| 106 | + pub fn base(&self) -> RegId { |
| 107 | + RegId(self.0.base as RegIdInt) |
| 108 | + } |
| 109 | + |
| 110 | + /// Displacement/offset |
| 111 | + pub fn disp(&self) -> i32 { |
| 112 | + self.0.disp |
| 113 | + } |
| 114 | +} |
| 115 | + |
| 116 | +impl_PartialEq_repr_fields!(XtensaOpMem; |
| 117 | + base, disp |
| 118 | +); |
| 119 | + |
| 120 | +impl cmp::Eq for XtensaOpMem {} |
| 121 | + |
| 122 | +def_arch_details_struct!( |
| 123 | + InsnDetail = XtensaInsnDetail; |
| 124 | + Operand = XtensaOperand; |
| 125 | + OperandIterator = XtensaOperandIterator; |
| 126 | + OperandIteratorLife = XtensaOperandIterator<'a>; |
| 127 | + [ pub struct XtensaOperandIterator<'a>(slice::Iter<'a, cs_xtensa_op>); ] |
| 128 | + cs_arch_op = cs_xtensa_op; |
| 129 | + cs_arch = cs_xtensa; |
| 130 | +); |
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