status signals completed

Author: AmirMohammadFakhimi

.vscode/configurationCache.log

@@ -1 +1 @@
-{"buildTargets":["assemble","clean","clean-mem","compile","obj_dir/Vmips_machine","sim","verify","verify-all"],"launchTargets":[],"customConfigurationProvider":{"workspaceBrowse":{"browsePath":[],"compilerArgs":[]},"fileIndex":[]}}
+{"buildTargets":["assemble","clean","clean-mem","compile","make","obj_dir/Vmips_machine","sim","verify","verify-all"],"launchTargets":[],"customConfigurationProvider":{"workspaceBrowse":{"browsePath":[],"compilerArgs":[]},"fileIndex":[]}}

.vscode/targets.log

@@ -6,11 +6,8 @@ make all --print-data-base --no-builtin-variables --no-builtin-rules --question
 # PARTICULAR PURPOSE.
 
 # This program built for i386-apple-darwin11.3.0
- 
-make: *** No rule to make target `all'.  Stop.
-
 
-# Make data base, printed on Thu Jul 21 23:21:59 2022
+# Make data base, printed on Thu Jul 21 23:44:46 2022
 
 # Variables
 
@@ -159,7 +156,7 @@ CONDA_PREFIX = /Users/AMF/opt/anaconda3
 # environment
 VSCODE_PID = 16578
 # makefile (from `Makefile', line 23)
-INPUT = test/default/addiu
+INPUT = test/default/wanted
 # environment
 _CE_CONDA = 
 # environment
@@ -174,11 +171,11 @@ LANG = C
 # Directories
 
 # . (device 16777220, inode 79971131): 16 files, no impossibilities.
-# test/default (device 16777220, inode 79971255): 30 files, no impossibilities.
+# test/default (device 16777220, inode 79971255): 33 files, no impossibilities.
 # 323src (device 16777220, inode 79971231): 7 files, no impossibilities.
-# src (device 16777220, inode 79971241): 20 files, no impossibilities.
+# src (device 16777220, inode 79971241): 14 files, no impossibilities.
 
-# 73 files, no impossibilities in 4 directories.
+# 70 files, no impossibilities in 4 directories.
 
 # Implicit Rules
 
@@ -196,7 +193,7 @@ LANG = C
 
 # Files
 
-obj_dir/Vmips_machine: src/EX.sv src/ID.sv src/IF.sv src/MEM.sv src/alu.sv src/cache.sv src/cache_control.sv src/controll.sv src/coprocessor.sv src/mips_core.sv src/pc.sv src/test_add_sub.sv src/test_cmp.sv src/test_div.sv src/test_mul.sv src/test_rev.sv src/test_rnd.sv 323src/dff.sv 323src/memory.sv 323src/mips_machine.sv 323src/regfile.sv 323src/sim_main.cpp
+obj_dir/Vmips_machine: src/EX.sv src/ID.sv src/IF.sv src/MEM.sv src/alu.sv src/cache.sv src/cache_control.sv src/controll.sv src/coprocessor.sv src/mips_core.sv src/pc.sv 323src/dff.sv 323src/memory.sv 323src/mips_machine.sv 323src/regfile.sv 323src/sim_main.cpp
 #  Implicit rule search has not been done.
 #  Modification time never checked.
 #  File has not been updated.
@@ -208,18 +205,6 @@ obj_dir/Vmips_machine: src/EX.sv src/ID.sv src/IF.sv src/MEM.sv src/alu.sv src/c
 	323src/sim_main.cpp
 
 
-# Not a target:
-src/test_add_sub.sv:
-#  Implicit rule search has not been done.
-#  Modification time never checked.
-#  File has not been updated.
-
-# Not a target:
-src/test_rnd.sv:
-#  Implicit rule search has not been done.
-#  Modification time never checked.
-#  File has not been updated.
-
 # Not a target:
 src/IF.sv:
 #  Implicit rule search has not been done.
@@ -255,7 +240,7 @@ test/default/shifttest.mem:
 #  Modification time never checked.
 #  File has not been updated.
 
-assemble: test/default/addiu.mem test/default/addtest.mem test/default/arithtest.mem test/default/brtest0.mem test/default/brtest2.mem test/default/float.mem test/default/memtest0.mem test/default/sb.mem test/default/shifttest.mem
+assemble: test/default/addiu.mem test/default/addtest.mem test/default/arithtest.mem test/default/brtest0.mem test/default/brtest2.mem test/default/float.mem test/default/memtest0.mem test/default/sb.mem test/default/shifttest.mem test/default/wanted.mem
 #  Implicit rule search has not been done.
 #  Modification time never checked.
 #  File has not been updated.
@@ -266,12 +251,6 @@ assemble: test/default/addiu.mem test/default/addtest.mem test/default/arithtest
 #  Modification time never checked.
 #  File has not been updated.
 
-# Not a target:
-src/test_rev.sv:
-#  Implicit rule search has not been done.
-#  Modification time never checked.
-#  File has not been updated.
-
 # Not a target:
 src/mips_core.sv:
 #  Implicit rule search has not been done.
@@ -305,9 +284,8 @@ test/default/addiu.mem:
 # Not a target:
 Makefile:
 #  Implicit rule search has been done.
-#  Last modified 2022-07-19 01:45:55
+#  Last modified 2022-07-21 23:25:44
 #  File has been updated.
- 
 #  Successfully updated.
 # variable set hash-table stats:
 # Load=0/32=0%, Rehash=0, Collisions=0/0=0%
@@ -318,14 +296,11 @@ src/cache.sv:
 #  Modification time never checked.
 #  File has not been updated.
 
-# Not a target:
-323src/dff.sv:
-#  Implicit rule search has not been done.
-#  Modification time never checked.
-#  File has not been updated.
+ 
+make: *** No rule to make target `all'.  Stop.
 
 # Not a target:
-src/test_mul.sv:
+323src/dff.sv:
 #  Implicit rule search has not been done.
 #  Modification time never checked.
 #  File has not been updated.
@@ -440,12 +415,6 @@ verify: sim
 	diff -u ${INPUT}.reg output/regdump.reg 1>&2
 
 
-# Not a target:
-src/test_cmp.sv:
-#  Implicit rule search has not been done.
-#  Modification time never checked.
-#  File has not been updated.
-
 # Not a target:
 test/default/brtest2.mem:
 #  Implicit rule search has not been done.
@@ -475,13 +444,13 @@ verify-all: compile assemble
 
 
 # Not a target:
-src/pc.sv:
+test/default/wanted.mem:
 #  Implicit rule search has not been done.
 #  Modification time never checked.
 #  File has not been updated.
 
 # Not a target:
-src/test_div.sv:
+src/pc.sv:
 #  Implicit rule search has not been done.
 #  Modification time never checked.
 #  File has not been updated.
@@ -493,7 +462,7 @@ src/coprocessor.sv:
 #  File has not been updated.
 
 # files hash-table stats:
-# Load=44/1024=4%, Rehash=0, Collisions=0/96=0%
+# Load=39/1024=4%, Rehash=0, Collisions=0/86=0%
 # VPATH Search Paths
 
 # No `vpath' search paths.
@@ -505,6 +474,6 @@ src/coprocessor.sv:
 # strcache size: total = 4096 / max = 4096 / min = 4096 / avg = 4096
 # strcache free: total = 4087 / max = 4087 / min = 4087 / avg = 4087
 
-# Finished Make data base on Thu Jul 21 23:21:59 2022
+# Finished Make data base on Thu Jul 21 23:44:46 2022
 
 

src/coprocessor.sv

@@ -36,7 +36,9 @@ module coprocessor(
 
      /*verilator lint_off WIDTH*/
     always @(posedge clk) begin
-        register[0] = 0;
+        if (write_data_enable == 1'b1 || opcode == 6'b001011 || opcode == 6'b110000 || opcode == 6'b110001 || opcode == 6'b110010 ||
+            opcode == 6'b110011 || opcode == 6'b110100 || opcode == 6'b110101 || opcode == 6'b110110)
+                register[0] = 0;
 
         if (!cache_done) begin
         if (write_data_enable == 1'b1) begin
@@ -49,9 +51,9 @@ module coprocessor(
 
         // add and subtract
         else if (opcode[5:1] == 5'b11000) begin
-        mantisa[0] = {1'b1, register[addr_reg_in2][22:0]}; // store the mantisa and exponent of each operand
+        mantisa[0] = {1'b1, register[addr_reg_in2][22:0]};
         mantisa[1] = {1'b1, register[addr_reg_in1][22:0]};
-        exponent[0] = register[addr_reg_in2][30:23]; // store the mantisa and exponent of each operand
+        exponent[0] = register[addr_reg_in2][30:23];
         exponent[1] = register[addr_reg_in1][30:23];
         sign[0] = register[addr_reg_in2][31];
         sign[1] = register[addr_reg_in1][31];
@@ -69,20 +71,36 @@ module coprocessor(
                 if(exponent[0] > exponent[1]) begin
                     exponent[2] = exponent[0] - exponent[1];
                     register[addr_destination][30:23] = exponent[0];
-                    mantisa[1]=(mantisa[1]) >> exponent[2];
+
+                    for (i = 0; i < exponent[2]; i = i + 1) begin
+                        if (mantisa[1][i])
+                            register[0][3] = 1;
+                    end
+
+                    mantisa[1] = (mantisa[1]) >> exponent[2];
                 end else begin
                    exponent[2] = exponent[1] - exponent[0];
                    register[addr_destination][30:23] = exponent[1];
+
+                   for (i = 0; i < exponent[2]; i = i + 1) begin
+                        if (mantisa[0][i])
+                            register[0][3] = 1;
+                    end
+                    
                    mantisa[0] = (mantisa[0]) >> exponent[2];
                 end
-                if((opcode[0] == 0 && !(sign[0] ^ sign[1])) 
+
+                if ((opcode[0] == 0 && !(sign[0] ^ sign[1])) 
                     ||(opcode[0] == 1 && (sign[0] ^ sign[1]))) begin
                         mantisa_sum = mantisa[0] + mantisa[1];
-                        if(mantisa_sum[24] == 0) begin
+                        if (mantisa_sum[24] == 0) begin
                             register[addr_destination][22:0] = mantisa_sum[22:0];
                             register[addr_destination][31] = register[addr_reg_in1][31];     
                         end
                         else begin
+                            if (mantisa_sum[0])
+                                register[0][3] = 1;
+
                             mantisa_sum = mantisa_sum >> 1;
                             register[addr_destination][30:23] = register[addr_destination][30:23] + 1;
                             register[addr_destination][22:0] = mantisa_sum[22:0];
@@ -95,10 +113,11 @@ module coprocessor(
                         d2 = mantisa[1];
                         d2 = ~d2[23:0] +1;
                         d2[24] = 0;
-                     mantisa_sum = d1 + (d2 + 1) ;
-                     if(mantisa_sum[24] == 1 && mantisa_sum[23:0] == 0)  begin
+
+                     mantisa_sum = d1 + (d2 + 1);
+                     if (mantisa_sum[24] == 1 && mantisa_sum[23:0] == 0)
                          register[addr_destination] = 0;
-                     end
+
                      else begin
                         if(mantisa_sum[24] == 0) begin
                             mantisa_sum[23:0] = ~mantisa_sum[23:0] + 1;
@@ -109,7 +128,7 @@ module coprocessor(
                             register[addr_destination][30:23] = register[addr_destination][30:23] - 1;
                         end
                         register[addr_destination][22:0] = mantisa_sum[22:0];
-                        if(mantisa[0] > mantisa[1])
+                        if (mantisa[0] > mantisa[1])
                             register[addr_destination][31] = sign[0];
                         else
                             register[addr_destination][31] = opcode[0] == 0 ? sign[1]:~sign[1];
@@ -120,15 +139,19 @@ module coprocessor(
 
         // multiply
         end else if(opcode == 6'b110010) begin
-            mantisa[0] = {1'b1, register[addr_reg_in2][22:0]}; // store the mantisa and exponent of each operand
+            mantisa[0] = {1'b1, register[addr_reg_in2][22:0]};
             mantisa[1] = {1'b1, register[addr_reg_in1][22:0]};
-            exponent[0] = register[addr_reg_in2][30:23]; // store the mantisa and exponent of each operand
+            exponent[0] = register[addr_reg_in2][30:23];
             exponent[1] = register[addr_reg_in1][30:23];
 
             if (register[addr_reg_in2] == 0 || register[addr_reg_in1] == 0)
                 register[addr_destination] = 0;
             else begin
                 mul_ans = 0;
+
+                if (exponent[0] + exponent[1] - bias + 1 > 255)
+                    register[0][5] = 1;
+
                 register[addr_destination][30:23] = exponent[0] + exponent[1] - bias + 1;
                 register[addr_destination][31] = register[addr_reg_in2][31] ^ register[addr_reg_in1][31];
                 mul_ans = mantisa[0] * mantisa[1];
@@ -139,45 +162,56 @@ module coprocessor(
             end
 
             register[addr_destination][22:0] = mul_ans[46:24];
+
+            if (mul_ans[23:0] != 0)
+                register[0][3] = 1;
         end
 
         // divide
         else if(opcode == 6'b110011) begin
 
-            mantisa[0] = {1'b1, register[addr_reg_in2][22:0]}; // store the mantisa and exponent of each operand
+            mantisa[0] = {1'b1, register[addr_reg_in2][22:0]};
             mantisa[1] = {1'b1, register[addr_reg_in1][22:0]};
-            exponent[0] = register[addr_reg_in2][30:23]; // store the mantisa and exponent of each operand
+            exponent[0] = register[addr_reg_in2][30:23];
             exponent[1] = register[addr_reg_in1][30:23];
             if (register[addr_reg_in1] == 0)
                 register[0][0] = 1;
-            else if(register[addr_reg_in2] == 0)
+            else if (register[addr_reg_in2] == 0)
                 register[addr_destination] = 0;
             else begin
                 register[addr_destination][31] = register[addr_reg_in2][31] ^ register[addr_reg_in1][31];
 
-                extra = {mantisa[0],24'b0};
-                extra = extra / mantisa[1];
+                extra = {mantisa[0], 24'b0};
+                extra = extra / mantisa[1];                
+
+                if (extra[24] == 1) begin
+                    if (extra[0])
+                        register[0][3] = 1;
 
-                if(extra[24] == 1)
                     extra = extra >> 1;
-                else
+                end else
                     exponent[0] = exponent[0] - 1;
+                
                 div_ans = extra[23:0];
+
+                if (exponent[0] < exponent[1] - bias)
+                    register[0][4] = 1;
+
                 register[addr_destination][30:23] = exponent[0] - exponent[1] + bias;
 
-                for (i = 0; i<23 && div_ans[23] != 1 ; i = i + 1 ) begin
+                for (i = 0; i<23 && div_ans[23] != 1 ; i = i + 1 )
                     div_ans = div_ans << 1;
-                end
+
                 register[addr_destination][22:0] = div_ans[22:0];
             end
 
         end
 
         //compare //cmp
         else if(opcode == 6'b110100) begin
-            mantisa[0] = {1'b1, register[addr_reg_in2][22:0]}; // store the mantisa and exponent of each operand
+            mantisa[0] = {1'b1, register[addr_reg_in2][22:0]};
             mantisa[1] = {1'b1, register[addr_reg_in1][22:0]};
-            exponent[0] = register[addr_reg_in2][30:23]; // store the mantisa and exponent of each operand
+            exponent[0] = register[addr_reg_in2][30:23];
             exponent[1] = register[addr_reg_in1][30:23];
             sign[0] = register[addr_reg_in2][31];
             sign[1] = register[addr_reg_in1][31];
@@ -242,12 +276,19 @@ module coprocessor(
                 extra = {mantisa[0], 24'b0};
                 extra = extra / mantisa[1];
 
-                if(extra[24] == 1)
+                if(extra[24] == 1) begin
+                    if (extra[0])
+                        register[0][3] = 1;
+
                     extra = extra >> 1;
-                else
+                end else
                     exponent[0] = exponent[0] - 1;
 
                 div_ans = extra[23:0];
+
+                if (exponent[0] < exponent[1] - bias)
+                    register[0][4] = 1;
+
                 register[addr_destination][30:23] = exponent[0] - exponent[1] + bias;
 
                 for (i = 0; i<23 && div_ans[23] != 1 ; i = i + 1 ) begin
@@ -284,6 +325,16 @@ module coprocessor(
             end
         end
     end
+
+    if (write_data_enable == 1'b1 || opcode == 6'b001011 || opcode == 6'b110000 || opcode == 6'b110001 || opcode == 6'b110010 ||
+            opcode == 6'b110011 || opcode == 6'b110101 || opcode == 6'b110110) begin
+        if (&register[addr_destination][30:23] == 1 && |register[addr_destination][22:0] != 0) begin
+            if (register[addr_destination][22])
+                register[0][1] = 1;
+            else
+                register[0][2] = 1;
+        end
+    end
     end
  /*verilator lint_off WIDTH*/
 endmodule