Reformat with scalafmt 3.8.6

Executed command: scalafmt --non-interactive

Author: scala-steward

firrtl/benchmark/src/main/scala/firrtl/benchmark/hot/SerializationBenchmark.scala

@@ -8,17 +8,17 @@ object SerializationBenchmark extends App {
   val inputFile = args(0)
   val warmup = args(1).toInt
   val runs = args(2).toInt
-  val select = if(args.length > 3) args(3) else "o"
+  val select = if (args.length > 3) args(3) else "o"
 
   val input = filenameToCircuit(inputFile)
 
-  if(select == "n") {
+  if (select == "n") {
     println("Benchmarking new Serializer.serialize")
     firrtl.benchmark.hot.util.benchmark(warmup, runs)(Serializer.serialize(input))
-  } else if(select == "o") {
+  } else if (select == "o") {
     println("Benchmarking legacy serialization")
     firrtl.benchmark.hot.util.benchmark(warmup, runs)(input.serialize)
-  } else if(select.startsWith("test")) {
+  } else if (select.startsWith("test")) {
     println("Testing the new serialization against the old one")
     val o = input.serialize.split('\n').filterNot(_.trim.isEmpty)
     val n = Serializer.serialize(input).split('\n').filterNot(_.trim.isEmpty)
@@ -27,11 +27,11 @@ object SerializationBenchmark extends App {
     println(s"Old lines: ${o.length}")
     println(s"New lines: ${n.length}")
     o.zip(n).zipWithIndex.foreach { case ((ol, nl), ii) =>
-      if(ol != nl) {
+      if (ol != nl) {
         println(s"❌@$ii OLD: |$ol|")
         println(s"❌@$ii NEW: |$nl|")
         throw new RuntimeException()
-      } else if(!silent) {
+      } else if (!silent) {
         println(s"✅        |$ol")
       }
     }

firrtl/benchmark/src/main/scala/firrtl/benchmark/hot/TransformBenchmark.scala

@@ -25,4 +25,4 @@ abstract class TransformBenchmark(factory: () => Transform) extends App {
 
 object LowerTypesBenchmark extends TransformBenchmark(() => LowerTypes)
 
-object DedupBenchmark extends TransformBenchmark(() => new DedupModules())
+object DedupBenchmark extends TransformBenchmark(() => new DedupModules())

firrtl/benchmark/src/main/scala/firrtl/benchmark/hot/util/package.scala

@@ -1,4 +1,3 @@
-
 package firrtl.benchmark.hot
 
 import firrtl.Utils.time

lit/tests/Converter/Circuit.sc

@@ -4,13 +4,12 @@
 import chisel3._
 import chisel3.util.circt.IsX
 
-
 // FIRRTL-LABEL: circuit FooModule :
 // FIRRTL-NEXT: extmodule FooBlackbox :
 // FIRRTL-NEXT: output o : UInt<1>
 // FIRRTL-NEXT: defname = FooBlackbox
 class FooBlackbox extends BlackBox {
-  val io = IO(new Bundle{
+  val io = IO(new Bundle {
     val o = Output(Bool())
   })
 }

lit/tests/Converter/Module.sc

@@ -2,7 +2,7 @@
 // SPDX-License-Identifier: Apache-2.0
 
 import chisel3._
-import chisel3.experimental.{Analog, attach}
+import chisel3.experimental.{attach, Analog}
 import chisel3.util.SRAM
 
 // FIRRTL-LABEL: public module Attach :
@@ -76,7 +76,7 @@ class Mem extends Module {
   // FIRRTL: invalidate r.data
   r.data := DontCare
   // FIRRTL: when r.enable :
-  when (r.enable) {
+  when(r.enable) {
     // FIRRTL-NEXT: infer mport wrPort = mem[r.address], clock
     val wrPort = mem(r.address)
     // FIRRTL-NEXT: connect r.data, wrPort
@@ -86,7 +86,7 @@ class Mem extends Module {
   }
 
   // FIRRTL: when w.enable :
-  when (w.enable) {
+  when(w.enable) {
     // FIRRTL-NEXT: infer mport wrPort_1 = mem[w.address], clock
     val wrPort = mem(w.address)
     // FIRRTL-NEXT: connect wrPort_1, w.data

lit/tests/Property/DocExample.sc

@@ -32,11 +32,7 @@ class CSRDescription extends Class {
 }
 
 // A hardware module representing a CSR and its description.
-class CSRModule(
-  csrDescDef:     Definition[CSRDescription],
-  width:          Int,
-  identifierStr:  String,
-  descriptionStr: String)
+class CSRModule(csrDescDef: Definition[CSRDescription], width: Int, identifierStr: String, descriptionStr: String)
     extends Module {
   override def desiredName = identifierStr