From 7c76585511d94761aba2880056691b0e8a038f08 Mon Sep 17 00:00:00 2001 From: Scala Steward Date: Thu, 27 Feb 2025 14:52:15 +0000 Subject: [PATCH 1/3] Update scalafmt-core to 3.8.6 --- .scalafmt.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.scalafmt.conf b/.scalafmt.conf index 75a46ff6a15..c15f653fa6c 100644 --- a/.scalafmt.conf +++ b/.scalafmt.conf @@ -1,4 +1,4 @@ -version = 3.8.5 +version = 3.8.6 runner.dialect = scala213source3 fileOverride { From f9666e70c9b55a2aad81915a46e7b63310dd88fe Mon Sep 17 00:00:00 2001 From: Scala Steward Date: Thu, 27 Feb 2025 14:52:57 +0000 Subject: [PATCH 2/3] Reformat with scalafmt 3.8.6 Executed command: scalafmt --non-interactive --- .../benchmark/hot/SerializationBenchmark.scala | 12 ++++++------ .../firrtl/benchmark/hot/TransformBenchmark.scala | 2 +- .../scala/firrtl/benchmark/hot/util/package.scala | 1 - lit/tests/Converter/Circuit.sc | 3 +-- lit/tests/Converter/Module.sc | 6 +++--- lit/tests/Property/DocExample.sc | 6 +----- 6 files changed, 12 insertions(+), 18 deletions(-) diff --git a/firrtl/benchmark/src/main/scala/firrtl/benchmark/hot/SerializationBenchmark.scala b/firrtl/benchmark/src/main/scala/firrtl/benchmark/hot/SerializationBenchmark.scala index 592b0eb84d6..8c9fe9b208a 100644 --- a/firrtl/benchmark/src/main/scala/firrtl/benchmark/hot/SerializationBenchmark.scala +++ b/firrtl/benchmark/src/main/scala/firrtl/benchmark/hot/SerializationBenchmark.scala @@ -8,17 +8,17 @@ object SerializationBenchmark extends App { val inputFile = args(0) val warmup = args(1).toInt val runs = args(2).toInt - val select = if(args.length > 3) args(3) else "o" + val select = if (args.length > 3) args(3) else "o" val input = filenameToCircuit(inputFile) - if(select == "n") { + if (select == "n") { println("Benchmarking new Serializer.serialize") firrtl.benchmark.hot.util.benchmark(warmup, runs)(Serializer.serialize(input)) - } else if(select == "o") { + } else if (select == "o") { println("Benchmarking legacy serialization") firrtl.benchmark.hot.util.benchmark(warmup, runs)(input.serialize) - } else if(select.startsWith("test")) { + } else if (select.startsWith("test")) { println("Testing the new serialization against the old one") val o = input.serialize.split('\n').filterNot(_.trim.isEmpty) val n = Serializer.serialize(input).split('\n').filterNot(_.trim.isEmpty) @@ -27,11 +27,11 @@ object SerializationBenchmark extends App { println(s"Old lines: ${o.length}") println(s"New lines: ${n.length}") o.zip(n).zipWithIndex.foreach { case ((ol, nl), ii) => - if(ol != nl) { + if (ol != nl) { println(s"❌@$ii OLD: |$ol|") println(s"❌@$ii NEW: |$nl|") throw new RuntimeException() - } else if(!silent) { + } else if (!silent) { println(s"✅ |$ol") } } diff --git a/firrtl/benchmark/src/main/scala/firrtl/benchmark/hot/TransformBenchmark.scala b/firrtl/benchmark/src/main/scala/firrtl/benchmark/hot/TransformBenchmark.scala index 4845bcff379..3aff1315c78 100644 --- a/firrtl/benchmark/src/main/scala/firrtl/benchmark/hot/TransformBenchmark.scala +++ b/firrtl/benchmark/src/main/scala/firrtl/benchmark/hot/TransformBenchmark.scala @@ -25,4 +25,4 @@ abstract class TransformBenchmark(factory: () => Transform) extends App { object LowerTypesBenchmark extends TransformBenchmark(() => LowerTypes) -object DedupBenchmark extends TransformBenchmark(() => new DedupModules()) \ No newline at end of file +object DedupBenchmark extends TransformBenchmark(() => new DedupModules()) diff --git a/firrtl/benchmark/src/main/scala/firrtl/benchmark/hot/util/package.scala b/firrtl/benchmark/src/main/scala/firrtl/benchmark/hot/util/package.scala index 911bd03ab09..3ef20e959a7 100644 --- a/firrtl/benchmark/src/main/scala/firrtl/benchmark/hot/util/package.scala +++ b/firrtl/benchmark/src/main/scala/firrtl/benchmark/hot/util/package.scala @@ -1,4 +1,3 @@ - package firrtl.benchmark.hot import firrtl.Utils.time diff --git a/lit/tests/Converter/Circuit.sc b/lit/tests/Converter/Circuit.sc index a7c7c157e08..57d5797c05f 100644 --- a/lit/tests/Converter/Circuit.sc +++ b/lit/tests/Converter/Circuit.sc @@ -4,13 +4,12 @@ import chisel3._ import chisel3.util.circt.IsX - // FIRRTL-LABEL: circuit FooModule : // FIRRTL-NEXT: extmodule FooBlackbox : // FIRRTL-NEXT: output o : UInt<1> // FIRRTL-NEXT: defname = FooBlackbox class FooBlackbox extends BlackBox { - val io = IO(new Bundle{ + val io = IO(new Bundle { val o = Output(Bool()) }) } diff --git a/lit/tests/Converter/Module.sc b/lit/tests/Converter/Module.sc index db79ad0fa00..4329e5a8185 100644 --- a/lit/tests/Converter/Module.sc +++ b/lit/tests/Converter/Module.sc @@ -2,7 +2,7 @@ // SPDX-License-Identifier: Apache-2.0 import chisel3._ -import chisel3.experimental.{Analog, attach} +import chisel3.experimental.{attach, Analog} import chisel3.util.SRAM // FIRRTL-LABEL: public module Attach : @@ -76,7 +76,7 @@ class Mem extends Module { // FIRRTL: invalidate r.data r.data := DontCare // FIRRTL: when r.enable : - when (r.enable) { + when(r.enable) { // FIRRTL-NEXT: infer mport wrPort = mem[r.address], clock val wrPort = mem(r.address) // FIRRTL-NEXT: connect r.data, wrPort @@ -86,7 +86,7 @@ class Mem extends Module { } // FIRRTL: when w.enable : - when (w.enable) { + when(w.enable) { // FIRRTL-NEXT: infer mport wrPort_1 = mem[w.address], clock val wrPort = mem(w.address) // FIRRTL-NEXT: connect wrPort_1, w.data diff --git a/lit/tests/Property/DocExample.sc b/lit/tests/Property/DocExample.sc index 6920741d56a..89c88d44951 100644 --- a/lit/tests/Property/DocExample.sc +++ b/lit/tests/Property/DocExample.sc @@ -32,11 +32,7 @@ class CSRDescription extends Class { } // A hardware module representing a CSR and its description. -class CSRModule( - csrDescDef: Definition[CSRDescription], - width: Int, - identifierStr: String, - descriptionStr: String) +class CSRModule(csrDescDef: Definition[CSRDescription], width: Int, identifierStr: String, descriptionStr: String) extends Module { override def desiredName = identifierStr From 7fe6bcf87150507a2f54009529c735728e6857ba Mon Sep 17 00:00:00 2001 From: Scala Steward Date: Thu, 27 Feb 2025 14:52:57 +0000 Subject: [PATCH 3/3] Add 'Reformat with scalafmt 3.8.6' to .git-blame-ignore-revs --- .git-blame-ignore-revs | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 .git-blame-ignore-revs diff --git a/.git-blame-ignore-revs b/.git-blame-ignore-revs new file mode 100644 index 00000000000..b3eed7da0be --- /dev/null +++ b/.git-blame-ignore-revs @@ -0,0 +1,2 @@ +# Scala Steward: Reformat with scalafmt 3.8.6 +f9666e70c9b55a2aad81915a46e7b63310dd88fe