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Platform/Intel/Vlv2TbltDevicePkg
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lines changed Original file line number Diff line number Diff line change @@ -461,7 +461,7 @@ UARTInit (
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if (SystemConfiguration -> LpssHsuart0Enabled == 1 ){
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//
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//Valleyview BIOS Specification Vol2,17.2
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- //LPSS_UART1 ¨ C set each pad PAD_CONF0.Func_Pin_Mux to function 1:
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+ //LPSS_UART1 C set each pad PAD_CONF0.Func_Pin_Mux to function 1:
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//
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MmioAnd8 (IO_BASE_ADDRESS + 0x0090 , (UINT8 )~0x07 );
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MmioOr8 (IO_BASE_ADDRESS + 0x0090 , 0x01 );
Original file line number Diff line number Diff line change @@ -205,9 +205,9 @@ GetSleepTypeAfterWakeup (
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// VLV BIOS Specification 0.6.2 - Section 18.4, "Power Failure Consideration"
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//
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// When the SUS_PWR_FLR bit is set, it indicates the SUS well power is lost.
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- // This bit is in the SUS Well and defaults to 1’ b1 based on RSMRST# assertion (not cleared by any type of reset).
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+ // This bit is in the SUS Well and defaults to 1' b1 based on RSMRST# assertion (not cleared by any type of reset).
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// System BIOS should follow cold boot path if SUS_PWR_FLR (PBASE + 0x20[14]),
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- // GEN_RST_STS (PBASE + 0x20[9]) or PWRBTNOR_STS (ABASE + 0x00[11]) is set to 1’ b1
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+ // GEN_RST_STS (PBASE + 0x20[9]) or PWRBTNOR_STS (ABASE + 0x00[11]) is set to 1' b1
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// regardless of the value in the SLP_TYP (ABASE + 0x04[12:10]) field.
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//
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GenPmCon1 = MmioRead16 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1 );
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