update changelog

jonfowler · jonfowler · commit bf3fc7f69937 · 2025-11-10T11:09:11.000Z
diff --git a/changelog/2025-11-10T09_31_42+00_00_consistent_verilog_indices b/changelog/2025-11-10T09_31_42+00_00_consistent_verilog_indices
@@ -1 +1 @@
-CHANGED: Vector functions in Verilog now have indices consistent with the Vec inputs/outputs (before they were reversed).
+CHANGED: Vector functions in Verilog now have indices consistent with the Vec inputs/outputs (before they were reversed). This is convenient when writing design constraints, which can now be referenced consistently like `imap[0],imap[1],..`.

Original file line number	Diff line number	Diff line change
`@@ -1 +1 @@`
`1`		`-CHANGED: Vector functions in Verilog now have indices consistent with the Vec inputs/outputs (before they were reversed).`
	`1`	+CHANGED: Vector functions in Verilog now have indices consistent with the Vec inputs/outputs (before they were reversed). This is convenient when writing design constraints, which can now be referenced consistently like `imap[0],imap[1],..`.