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make verilog imap index consistent
1 parent a032c85 commit fbf8e58

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+16
-11
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clash-lib/prims/verilog/Clash_Sized_Vector.primitives.yaml

Lines changed: 16 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -87,14 +87,15 @@
8787
genvar ~GENSYM[i][1];
8888
~GENERATE
8989
for (~SYM[1]=0; ~SYM[1] < ~LENGTH[~TYPO]; ~SYM[1] = ~SYM[1] + 1) begin : ~GENSYM[map][2]~IF~SIZE[~TYP[1]]~THEN
90+
localparam ~GENSYM[vec_index][5] = ~MAXINDEX[~TYPO] - ~SYM[1];
9091
wire ~TYPEL[~TYP[1]] ~GENSYM[map_in][3];
91-
assign ~SYM[3] = ~VAR[vec][1][~SYM[1]*~SIZE[~TYPEL[~TYP[1]]]+:~SIZE[~TYPEL[~TYP[1]]]];~ELSE ~FI
92+
assign ~SYM[3] = ~VAR[vec][1][~SYM[5]*~SIZE[~TYPEL[~TYP[1]]]+:~SIZE[~TYPEL[~TYP[1]]]];~ELSE ~FI
9293
~OUTPUTUSAGE[0] ~TYPEL[~TYPO] ~GENSYM[map_out][4];
9394
~INST 0
9495
~OUTPUT <= ~SYM[4]~ ~TYPEL[~TYPO]~
9596
~INPUT <= ~SYM[3]~ ~TYPEL[~TYP[1]]~
9697
~INST
97-
assign ~RESULT[~SYM[1]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]] = ~SYM[4];
98+
assign ~RESULT[~SYM[5]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]] = ~SYM[4];
9899
end
99100
~ENDGENERATE
100101
// map end
@@ -108,9 +109,10 @@
108109
genvar ~GENSYM[i][1];
109110
~GENERATE
110111
for (~SYM[1]=0; ~SYM[1] < ~LENGTH[~TYPO]; ~SYM[1] = ~SYM[1] + 1) begin : ~GENSYM[imap][2]
112+
localparam ~GENSYM[vec_index][6] = ~MAXINDEX[~TYPO] - ~SYM[1];
111113
wire [~SIZE[~INDEXTYPE[~LIT[0]]]-1:0] ~GENSYM[map_index][3];~IF~SIZE[~TYP[2]]~THEN
112114
wire ~TYPEL[~TYP[2]] ~GENSYM[map_in][4];
113-
assign ~SYM[4] = ~VAR[vec][2][~SYM[1]*~SIZE[~TYPEL[~TYP[2]]]+:~SIZE[~TYPEL[~TYP[2]]]];~ELSE ~FI
115+
assign ~SYM[4] = ~VAR[vec][2][~SYM[6]*~SIZE[~TYPEL[~TYP[2]]]+:~SIZE[~TYPEL[~TYP[2]]]];~ELSE ~FI
114116
~OUTPUTUSAGE[1] ~TYPEL[~TYPO] ~GENSYM[map_out][5];
115117
116118
assign ~SYM[3] = ~SIZE[~INDEXTYPE[~LIT[0]]]'d~MAXINDEX[~TYPO] - ~SYM[1][0+:~SIZE[~INDEXTYPE[~LIT[0]]]];
@@ -119,7 +121,7 @@
119121
~INPUT <= ~SYM[3]~ ~INDEXTYPE[~LIT[0]]~
120122
~INPUT <= ~SYM[4]~ ~TYPEL[~TYP[2]]~
121123
~INST
122-
assign ~RESULT[~SYM[1]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]] = ~SYM[5];
124+
assign ~RESULT[~SYM[6]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]] = ~SYM[5];
123125
end
124126
~ENDGENERATE
125127
// imap end
@@ -133,9 +135,10 @@
133135
genvar ~GENSYM[i][1];
134136
~GENERATE
135137
for (~SYM[1]=0; ~SYM[1] < ~LENGTH[~TYPO]; ~SYM[1] = ~SYM[1] + 1) begin : ~GENSYM[imap][2]
138+
localparam ~GENSYM[vec_index][6] = ~MAXINDEX[~TYPO] - ~SYM[1];
136139
wire ~TYP[2] ~GENSYM[map_index][3];~IF~SIZE[~TYP[1]]~THEN
137140
wire ~TYPEL[~TYP[1]] ~GENSYM[map_in][4];
138-
assign ~SYM[4] = ~VAR[vec][1][~SYM[1]*~SIZE[~TYPEL[~TYP[1]]]+:~SIZE[~TYPEL[~TYP[1]]]];~ELSE ~FI
141+
assign ~SYM[4] = ~VAR[vec][1][~SYM[6]*~SIZE[~TYPEL[~TYP[1]]]+:~SIZE[~TYPEL[~TYP[1]]]];~ELSE ~FI
139142
~OUTPUTUSAGE[0] ~TYPEL[~TYPO] ~GENSYM[map_out][5];
140143
141144
assign ~SYM[3] = ~SIZE[~TYP[2]]'d~MAXINDEX[~TYPO] - ~SYM[1][0+:~SIZE[~TYP[2]]] + ~ARG[2];
@@ -144,7 +147,7 @@
144147
~INPUT <= ~SYM[3]~ ~TYP[2]~
145148
~INPUT <= ~SYM[4]~ ~TYPEL[~TYP[1]]~
146149
~INST
147-
assign ~RESULT[~SYM[1]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]] = ~SYM[5];
150+
assign ~RESULT[~SYM[6]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]] = ~SYM[5];
148151
end
149152
~ENDGENERATE
150153
// imap end
@@ -158,17 +161,18 @@
158161
genvar ~GENSYM[i][2];
159162
~GENERATE
160163
for (~SYM[2] = 0; ~SYM[2] < ~LENGTH[~TYPO]; ~SYM[2] = ~SYM[2] + 1) begin : ~GENSYM[zipWith][6]~IF~SIZE[~TYP[1]]~THEN
164+
localparam ~GENSYM[vec_index][7] = ~MAXINDEX[~TYPO] - ~SYM[2];
161165
wire ~TYPEL[~TYP[1]] ~GENSYM[zipWith_in1][3];
162-
assign ~SYM[3] = ~VAR[vec1][1][~SYM[2]*~SIZE[~TYPEL[~TYP[1]]]+:~SIZE[~TYPEL[~TYP[1]]]];~ELSE ~FI~IF~SIZE[~TYP[2]]~THEN
166+
assign ~SYM[3] = ~VAR[vec1][1][~SYM[7]*~SIZE[~TYPEL[~TYP[1]]]+:~SIZE[~TYPEL[~TYP[1]]]];~ELSE ~FI~IF~SIZE[~TYP[2]]~THEN
163167
wire ~TYPEL[~TYP[2]] ~GENSYM[zipWith_in2][4];
164-
assign ~SYM[4] = ~VAR[vec2][2][~SYM[2]*~SIZE[~TYPEL[~TYP[2]]]+:~SIZE[~TYPEL[~TYP[2]]]];~ELSE ~FI
165-
~OUTPUTUSAGE[0] ~TYPEL[~TYPO] ~SYM[5];
168+
assign ~SYM[4] = ~VAR[vec2][2][~SYM[7]*~SIZE[~TYPEL[~TYP[2]]]+:~SIZE[~TYPEL[~TYP[2]]]];~ELSE ~FI
169+
~OUTPUTUSAGE[0] ~TYPEL[~TYPO] ~GENSYM[zip_out][5];
166170
~INST 0
167171
~OUTPUT <= ~SYM[5]~ ~TYPEL[~TYPO]~
168172
~INPUT <= ~SYM[3]~ ~TYPEL[~TYP[1]]~
169173
~INPUT <= ~SYM[4]~ ~TYPEL[~TYP[2]]~
170174
~INST
171-
assign ~RESULT[~SYM[2]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]] = ~SYM[5];
175+
assign ~RESULT[~SYM[7]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]] = ~SYM[5];
172176
end
173177
~ENDGENERATE
174178
// zipWith end
@@ -185,8 +189,9 @@
185189
genvar ~GENSYM[i][3];
186190
~GENERATE
187191
for (~SYM[3]=0; ~SYM[3] < ~LENGTH[~TYP[2]]; ~SYM[3]=~SYM[3]+1) begin : ~GENSYM[foldr][4]~IF~SIZE[~TYP[2]]~THEN
192+
localparam ~GENSYM[vec_index][8] = ~MAXINDEX[~TYPO] - ~SYM[3];
188193
wire ~TYPEL[~TYP[2]] ~GENSYM[foldr_in1][5];
189-
assign ~SYM[5] = ~VAR[xs][2][(~LENGTH[~TYP[2]]-1-~SYM[3])*~SIZE[~TYPEL[~TYP[2]]]+:~SIZE[~TYPEL[~TYP[2]]]];~ELSE ~FI
194+
assign ~SYM[5] = ~VAR[xs][2][(~SYM[8])*~SIZE[~TYPEL[~TYP[2]]]+:~SIZE[~TYPEL[~TYP[2]]]];~ELSE ~FI
190195
wire ~TYPO ~GENSYM[foldr_in2][6];
191196
~OUTPUTUSAGE[0] ~TYPO ~GENSYM[foldr_out][7];
192197

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