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This repository was archived by the owner on Jan 31, 2022. It is now read-only.
For "TDC SBit Mode" = Single VFAT2
No DC offset observed in waveforms
For "TDC SBit Mode" = iPhi sector
Large DC Offset observed on Channel 1 & 4 (J6 & J9) of R&S scope
For "TDC SBit Mode" = iEta sector
Large DC Offset observed on Channel 4 (J5) of Tektronix (TK) scope
Since thresholds of all chips in these three cases were set to 255 believe this is a problem in the output baseline voltage. Having this DC offset change depending on output SBIT mode is not desired. Can it be fixed to by 0V (as in the Single VFAT2 mode)?
Using firmware version: optohybrid_top_16-06-2016.bit
Clock source: GTX recovered clock.
Sequence: Start all VFATs -> Apply default parameters to all VFATs
Use VFAT2s I2C to set VThreshold1 = 255 for all VFATs
Using 2 oscilloscopes to monitor output copper SBIT singles from HDMI-to-LEMO card
Tektronix (TK) Scope
J3 -> CH1
J1 -> CH2
J4 -> CH3
J5 -> CH4
R&S Scope
J6 -> CH1
J7 -> CH2
J8 -> CH3
J9 -> CH4
For "TDC SBit Mode" = Single VFAT2


No DC offset observed in waveforms
For "TDC SBit Mode" = iPhi sector


Large DC Offset observed on Channel 1 & 4 (J6 & J9) of R&S scope
For "TDC SBit Mode" = iEta sector


Large DC Offset observed on Channel 4 (J5) of Tektronix (TK) scope
Since thresholds of all chips in these three cases were set to 255 believe this is a problem in the output baseline voltage. Having this DC offset change depending on output SBIT mode is not desired. Can it be fixed to by 0V (as in the Single VFAT2 mode)?