Skip to content
This repository was archived by the owner on Jan 31, 2022. It is now read-only.
This repository was archived by the owner on Jan 31, 2022. It is now read-only.

Output Coaxial SBIT Waveform DC Offset Shift Between Modes #18

@bdorney

Description

@bdorney

Using firmware version: optohybrid_top_16-06-2016.bit
Clock source: GTX recovered clock.

Sequence: Start all VFATs -> Apply default parameters to all VFATs
Use VFAT2s I2C to set VThreshold1 = 255 for all VFATs

Using 2 oscilloscopes to monitor output copper SBIT singles from HDMI-to-LEMO card

Tektronix (TK) Scope
J3 -> CH1
J1 -> CH2
J4 -> CH3
J5 -> CH4

R&S Scope
J6 -> CH1
J7 -> CH2
J8 -> CH3
J9 -> CH4

For "TDC SBit Mode" = Single VFAT2
rs_singlevfat_mode
tk_sbitmode_singlevfat
No DC offset observed in waveforms

For "TDC SBit Mode" = iPhi sector
Large DC Offset observed on Channel 1 & 4 (J6 & J9) of R&S scope
rs_iphi_mode
tk_sbitmode_iphi

For "TDC SBit Mode" = iEta sector
Large DC Offset observed on Channel 4 (J5) of Tektronix (TK) scope
rs_ieta_mode
tk_sbitmode_ieta

Since thresholds of all chips in these three cases were set to 255 believe this is a problem in the output baseline voltage. Having this DC offset change depending on output SBIT mode is not desired. Can it be fixed to by 0V (as in the Single VFAT2 mode)?

Metadata

Metadata

Assignees

No one assigned

    Labels

    No labels
    No labels

    Type

    No type

    Projects

    No projects

    Milestone

    No milestone

    Relationships

    None yet

    Development

    No branches or pull requests

    Issue actions