You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
{{ message }}
This repository was archived by the owner on Jan 31, 2022. It is now read-only.
Due to the OH we have in 904 constantly resetting, some extra debugging would be probably useful.
Having a timer that counts the number of seconds since the last time the FPGA reset would probably be the simplest, most useful thing that can be monitored intermittently.
Due to the OH we have in 904 constantly resetting, some extra debugging would be probably useful.
Having a timer that counts the number of seconds since the last time the FPGA reset would probably be the simplest, most useful thing that can be monitored intermittently.