project05 done. built CPU, RAM, and then assemble them with ROM together to build a computer

Author: codingjin

05/CPU.hdl

@@ -0,0 +1,93 @@
+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/05/CPU.hdl
+
+/**
+ * The Hack CPU (Central Processing unit), consisting of an ALU,
+ * two registers named A and D, and a program counter named PC.
+ * The CPU is designed to fetch and execute instructions written in 
+ * the Hack machine language. In particular, functions as follows:
+ * Executes the inputted instruction according to the Hack machine 
+ * language specification. The D and A in the language specification
+ * refer to CPU-resident registers, while M refers to the external
+ * memory location addressed by A, i.e. to Memory[A]. The inM input 
+ * holds the value of this location. If the current instruction needs 
+ * to write a value to M, the value is placed in outM, the address 
+ * of the target location is placed in the addressM output, and the 
+ * writeM control bit is asserted. (When writeM==0, any value may 
+ * appear in outM). The outM and writeM outputs are combinational: 
+ * they are affected instantaneously by the execution of the current 
+ * instruction. The addressM and pc outputs are clocked: although they 
+ * are affected by the execution of the current instruction, they commit 
+ * to their new values only in the next time step. If reset==1 then the 
+ * CPU jumps to address 0 (i.e. pc is set to 0 in next time step) rather 
+ * than to the address resulting from executing the current instruction. 
+ */
+
+CHIP CPU {
+
+    IN  inM[16],         // M value input  (M = contents of RAM[A])
+        instruction[16], // Instruction for execution
+        reset;           // Signals whether to re-start the current
+                         // program (reset==1) or continue executing
+                         // the current program (reset==0).
+
+    OUT outM[16],        // M value output
+        writeM,          // Write to M? 
+        addressM[15],    // Address in data memory (of M)
+        pc[15];          // address of next instruction
+
+    PARTS:
+// Put your code here:
+    And(a=instruction[15], b=instruction[15], out=isC);
+    Not(in=instruction[15], out=isA);
+
+    // For Cinstruction, if d1==1, means set Aregister as the destination of cmp which is result of ALU, then load it in ARegister
+    And(a=isC, b=instruction[5], out=aluout2A);
+    Mux16(a=instruction, b=aluout, sel=aluout2A, out=inAReg);
+
+    // if AReg needs to be load, load it
+    Or(a=isA, b=aluout2A, out=loadAReg);
+    ARegister(in=inAReg, load=loadAReg, out=ARegout, out[0..14]=addressM);
+
+    // define 1 input of ALU
+    And(a=isC, b=instruction[12], out=aset);
+    Mux16(a=ARegout, b=inM, sel=aset, out=aluin1);
+
+    // whether writeM is set
+    And(a=isC, b=instruction[3], out=writeM);
+
+    // whether write DReg
+    And(a=isC, b=instruction[4], out=writeDReg);
+    DRegister(in=aluout, load=writeDReg, out=DRegout);
+
+    And(a = isC, b = instruction[6], out = no);
+    And(a = isC, b = instruction[7], out = f);
+    And(a = isC, b = instruction[8], out = ny);
+    And(a = isC, b = instruction[9], out = zy);
+    And(a = isC, b = instruction[10], out = nx);
+    And(a = isC, b = instruction[11], out = zx);
+
+    ALU(x = DRegout, y = aluin1, zx = zx, nx = nx, zy = zy, ny = ny, f = f, no = no, out = aluout, out = outM, zr=zr, ng=ng);
+
+    And(a=isC, b=instruction[0], out=GT);
+    And(a=isC, b=instruction[1], out=EQ);
+    And(a=isC, b=instruction[2], out=LT);
+
+    And(a=ng, b=LT, out=LTJump);
+    And(a=zr, b=EQ, out=EQJump);
+
+    // output > 0
+    Not(in = ng, out = notNg);
+    Not(in = zr, out = notZr);
+    And(a = notNg, b = notZr, out = outGT);
+
+    And(a=outGT, b=GT, out=GTJump);
+
+    Or(a=LTJump, b=EQJump, out=jump0);
+    Or(a=jump0, b=GTJump, out=jump);
+
+    PC(in=ARegout, load=jump, inc=true, reset=reset, out[0..14]=pc);    
+
+}

05/Computer.hdl

@@ -0,0 +1,30 @@
+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/05/Computer.hdl
+
+/**
+ * The HACK computer, including CPU, ROM and RAM.
+ * When reset is 0, the program stored in the computer's ROM executes.
+ * When reset is 1, the execution of the program restarts. 
+ * Thus, to start a program's execution, reset must be pushed "up" (1)
+ * and "down" (0). From this point onward the user is at the mercy of 
+ * the software. In particular, depending on the program's code, the 
+ * screen may show some output and the user may be able to interact 
+ * with the computer via the keyboard.
+ */
+
+CHIP Computer {
+
+    IN reset;
+
+    PARTS:
+    // Put your code here:
+    CPU(inM=memoryout, instruction=romout, reset=reset, outM=outM, writeM=writeM, addressM=addressM, pc=pc);
+    Memory(in=outM, load=writeM, address=addressM, out=memoryout);
+    ROM32K(address=pc, out=romout);
+
+
+
+
+}

05/Memory.hdl

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+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/05/Memory.hdl
+
+/**
+ * The complete address space of the Hack computer's memory,
+ * including RAM and memory-mapped I/O. 
+ * The chip facilitates read and write operations, as follows:
+ *     Read:  out(t) = Memory[address(t)](t)
+ *     Write: if load(t-1) then Memory[address(t-1)](t) = in(t-1)
+ * In words: the chip always outputs the value stored at the memory 
+ * location specified by address. If load==1, the in value is loaded 
+ * into the memory location specified by address. This value becomes 
+ * available through the out output from the next time step onward.
+ * Address space rules:
+ * Only the upper 16K+8K+1 words of the Memory chip are used. 
+ * Access to address>0x6000 is invalid. Access to any address in 
+ * the range 0x4000-0x5FFF results in accessing the screen memory 
+ * map. Access to address 0x6000 results in accessing the keyboard 
+ * memory map. The behavior in these addresses is described in the 
+ * Screen and Keyboard chip specifications given in the book.
+ */
+
+CHIP Memory {
+    IN in[16], load, address[15];
+    OUT out[16];
+
+    PARTS:
+    // Put your code here:
+    DMux4Way(in=load, sel=address[13..14], a=a0, b=a1, c=loadscreen, d=loadkbd);
+    Or(a=a0, b=a1, out=loadram);
+
+    RAM16K(in=in, load=loadram, address=address[0..13], out=outram);
+    Screen(in=in, load=loadscreen, address=address[0..12], out=outscreen);
+    Keyboard(out=outkbd);
+
+    Mux4Way16(a=outram, b=outram, c=outscreen, d=outkbd, sel=address[13..14], out=out);
+}

README.md

@@ -22,6 +22,6 @@ Hack Machine Language programming.
 
 Project05
 
-
+Built RAM and CPU, and then assemble them wit ROM together to build a computer.