diff --git a/euvm/riscv/gen/target/rv32imcb/riscv_core_setting.d b/euvm/riscv/gen/target/rv32imcb/riscv_core_setting.d new file mode 100644 index 000000000..fe077339f --- /dev/null +++ b/euvm/riscv/gen/target/rv32imcb/riscv_core_setting.d @@ -0,0 +1,122 @@ +module riscv.gen.riscv_core_setting; + +import riscv.gen.riscv_instr_pkg: satp_mode_t, privileged_mode_t, + riscv_instr_name_t, mtvec_mode_t, interrupt_cause_t, + exception_cause_t, riscv_instr_group_t, privileged_reg_t; +import std.math: log2; +import esdl: ubvec; + +enum int XLEN = 32; + +// Parameter for SATP mode, set to BARE if address translation is not supported +enum satp_mode_t SATP_MODE = satp_mode_t.BARE; + +// Supported Privileged mode +privileged_mode_t[] supported_privileged_mode = [privileged_mode_t.MACHINE_MODE]; + +// Unsupported instructions +riscv_instr_name_t[] unsupported_instr = []; + +// ISA supported by the processor +riscv_instr_group_t[] supported_isa = [riscv_instr_group_t.RV32I, + riscv_instr_group_t.RV32M, + riscv_instr_group_t.RV32C, + riscv_instr_group_t.RV32B]; + +// Interrupt mode support +mtvec_mode_t[] supported_interrupt_mode = [mtvec_mode_t.DIRECT, + mtvec_mode_t.VECTORED]; + +// The number of interrupt vectors to be generated, only used if VECTORED interrupt mode is +// supported +enum int max_interrupt_vector_num = 16; + +// Physical memory protection support +enum bool support_pmp = false; + +// Debug mode support +enum bool support_debug_mode = false; + +// Support delegate trap to user mode +enum bool support_umode_trap = false; + +// Support sfence.vma instruction +enum bool support_sfence = false; + +// Support unaligned load/store +enum bool support_unaligned_load_store = true; + +// GPR setting +enum int NUM_FLOAT_GPR = 32; +enum int NUM_GPR = 32; +enum int NUM_VEC_GPR = 32; +// ---------------------------------------------------------------------------- +// Vector extension configuration +// ---------------------------------------------------------------------------- + +// Parameter for vector extension +enum int VECTOR_EXTENSION_ENABLE = 0; + +enum int VLEN = 512; + +// Maximum size of a single vector element +enum int ELEN = 32; + +// Minimum size of a sub-element, which must be at most 8-bits. +enum int SELEN = 8; + +// Maximum size of a single vector element (encoded in vsew format) +enum int VELEN = cast(int) log2(ELEN) - 3; + +static assert (VELEN == 2); + +// Maxium LMUL supported by the core +enum int MAX_LMUL = 8; + +// ---------------------------------------------------------------------------- +// Multi-harts configuration +// ---------------------------------------------------------------------------- + +// Number of harts +enum int NUM_HARTS = 1; + +// ---------------------------------------------------------------------------- +// Previleged CSR implementation +// ---------------------------------------------------------------------------- + +// Implemented previlieged CSR list +enum privileged_reg_t[] implemented_csr = [ + // Machine mode mode CSR + privileged_reg_t.MVENDORID, // Vendor ID + privileged_reg_t.MARCHID, // Architecture ID + privileged_reg_t.MIMPID, // Implementation ID + privileged_reg_t.MHARTID, // Hardware thread ID + privileged_reg_t.MSTATUS, // Machine status + privileged_reg_t.MISA, // ISA and extensions + privileged_reg_t.MIE, // Machine interrupt-enable register + privileged_reg_t.MTVEC, // Machine trap-handler base address + privileged_reg_t.MCOUNTEREN, // Machine counter enable + privileged_reg_t.MSCRATCH, // Scratch register for machine trap handlers + privileged_reg_t.MEPC, // Machine exception program counter + privileged_reg_t.MCAUSE, // Machine trap cause + privileged_reg_t.MTVAL, // Machine bad address or instruction + privileged_reg_t.MIP // Machine interrupt pending +]; + +// Implementation-specific custom CSRs +ubvec!12[] custom_csr = []; + +// ---------------------------------------------------------------------------- +// Supported interrupt/exception setting, used for functional coverage +// ---------------------------------------------------------------------------- + +enum interrupt_cause_t[] implemented_interrupt = [interrupt_cause_t.M_SOFTWARE_INTR, + interrupt_cause_t.M_TIMER_INTR, + interrupt_cause_t.M_EXTERNAL_INTR]; + +enum exception_cause_t[] implemented_exception = [exception_cause_t.INSTRUCTION_ACCESS_FAULT, + exception_cause_t.ILLEGAL_INSTRUCTION, + exception_cause_t.BREAKPOINT, + exception_cause_t.LOAD_ADDRESS_MISALIGNED, + exception_cause_t.LOAD_ACCESS_FAULT, + exception_cause_t.ECALL_MMODE]; \ No newline at end of file diff --git a/euvm/riscv/gen/target/rv64gc/riscv_core_setting.d b/euvm/riscv/gen/target/rv64gc/riscv_core_setting.d new file mode 100644 index 000000000..465134e50 --- /dev/null +++ b/euvm/riscv/gen/target/rv64gc/riscv_core_setting.d @@ -0,0 +1,171 @@ +module riscv.gen.riscv_core_setting; + +import riscv.gen.riscv_instr_pkg: satp_mode_t, privileged_mode_t, + riscv_instr_name_t, mtvec_mode_t, interrupt_cause_t, + exception_cause_t, riscv_instr_group_t, privileged_reg_t; +import std.math: log2; +import esdl: ubvec; + +enum int XLEN = 64; + +// Parameter for SATP mode, set to BARE if address translation is not supported +enum satp_mode_t SATP_MODE = satp_mode_t.SV39; + +// Supported Privileged mode +privileged_mode_t[] supported_privileged_mode = [privileged_mode_t.USER_MODE,privileged_mode_t.SUPERVISOR_MODE,privileged_mode_t.MACHINE_MODE]; + +// Unsupported instructions +riscv_instr_name_t[] unsupported_instr = []; + +// ISA supported by the processor +riscv_instr_group_t[] supported_isa = [riscv_instr_group_t.RV32I, + riscv_instr_group_t.RV32M, + riscv_instr_group_t.RV64I, + riscv_instr_group_t.RV64M, + riscv_instr_group_t.RV32F, + riscv_instr_group_t.RV64F, + riscv_instr_group_t.RV32D, + riscv_instr_group_t.RV64D, + riscv_instr_group_t.RV32X]; + +// Interrupt mode support +mtvec_mode_t[] supported_interrupt_mode = [mtvec_mode_t.DIRECT, + mtvec_mode_t.VECTORED]; + +// The number of interrupt vectors to be generated, only used if VECTORED interrupt mode is +// supported +enum int max_interrupt_vector_num = 16; + +// Physical memory protection support +enum bool support_pmp = false; + +// Debug mode support +enum bool support_debug_mode = false; + +// Support delegate trap to user mode +enum bool support_umode_trap = false; + +// Support sfence.vma instruction +enum bool support_sfence = true; + +// Support unaligned load/store +enum bool support_unaligned_load_store = true; + +// GPR setting +enum int NUM_FLOAT_GPR = 32; +enum int NUM_GPR = 32; +enum int NUM_VEC_GPR = 32; +// ---------------------------------------------------------------------------- +// Vector extension configuration +// ---------------------------------------------------------------------------- + +// Parameter for vector extension +enum int VECTOR_EXTENSION_ENABLE = 0; + +enum int VLEN = 512; + +// Maximum size of a single vector element +enum int ELEN = 32; + +// Minimum size of a sub-element, which must be at most 8-bits. +enum int SELEN = 8; + +// Maximum size of a single vector element (encoded in vsew format) +enum int VELEN = cast(int) log2(ELEN) - 3; + +static assert (VELEN == 2); + +// Maxium LMUL supported by the core +enum int MAX_LMUL = 8; + +// ---------------------------------------------------------------------------- +// Multi-harts configuration +// ---------------------------------------------------------------------------- + +// Number of harts +enum int NUM_HARTS = 1; + +// ---------------------------------------------------------------------------- +// Previleged CSR implementation +// ---------------------------------------------------------------------------- + +// Implemented previlieged CSR list +enum privileged_reg_t[] implemented_csr = [ + // User mode CSR + privileged_reg_t.USTATUS, // User status + privileged_reg_t.UIE, // User interrupt-enable register + privileged_reg_t.UTVEC, // User trap-handler base address + privileged_reg_t.USCRATCH, // Scratch register for user trap handlers + privileged_reg_t.UEPC, // User exception program counter + privileged_reg_t.UCAUSE, // User trap cause + privileged_reg_t.UTVAL, // User bad address or instruction + privileged_reg_t.UIP, // User interrupt pending + // Supervisor mode CSR + privileged_reg_t.SSTATUS, // Supervisor status + privileged_reg_t.SEDELEG, // Supervisor exception delegation register + privileged_reg_t.SIDELEG, // Supervisor interrupt delegation register + privileged_reg_t.SIE, // Supervisor interrupt-enable register + privileged_reg_t.STVEC, // Supervisor trap-handler base address + privileged_reg_t.SCOUNTEREN, // Supervisor counter enable + privileged_reg_t.SSCRATCH, // Scratch register for supervisor trap handlers + privileged_reg_t.SEPC, // Supervisor exception program counter + privileged_reg_t.SCAUSE, // Supervisor trap cause + privileged_reg_t.STVAL, // Supervisor bad address or instruction + privileged_reg_t.SIP, // Supervisor interrupt pending + privileged_reg_t.SATP, // Supervisor address translation and protection + // Machine mode mode CSR + privileged_reg_t.MVENDORID, // Vendor ID + privileged_reg_t.MARCHID, // Architecture ID + privileged_reg_t.MIMPID, // Implementation ID + privileged_reg_t.MHARTID, // Hardware thread ID + privileged_reg_t.MSTATUS, // Machine status + privileged_reg_t.MISA, // ISA and extensions + privileged_reg_t.MEDELEG, // Machine exception delegation register + privileged_reg_t.MIDELEG, // Machine interrupt delegation register + privileged_reg_t.MIE, // Machine interrupt-enable register + privileged_reg_t.MTVEC, // Machine trap-handler base address + privileged_reg_t.MCOUNTEREN, // Machine counter enable + privileged_reg_t.MSCRATCH, // Scratch register for machine trap handlers + privileged_reg_t.MEPC, // Machine exception program counter + privileged_reg_t.MCAUSE, // Machine trap cause + privileged_reg_t.MTVAL, // Machine bad address or instruction + privileged_reg_t.MIP, // Machine interrupt pending + // Floating point CSR + privileged_reg_t.FCSR // Floating point control and status + +]; + +// Implementation-specific custom CSRs +ubvec!12[] custom_csr = []; + +// ---------------------------------------------------------------------------- +// Supported interrupt/exception setting, used for functional coverage +// ---------------------------------------------------------------------------- + +enum interrupt_cause_t[] implemented_interrupt = [ + interrupt_cause_t.U_SOFTWARE_INTR, + interrupt_cause_t.S_SOFTWARE_INTR, + interrupt_cause_t.M_SOFTWARE_INTR, + interrupt_cause_t.U_TIMER_INTR, + interrupt_cause_t.S_TIMER_INTR, + interrupt_cause_t.M_TIMER_INTR, + interrupt_cause_t.U_EXTERNAL_INTR, + interrupt_cause_t.S_EXTERNAL_INTR, + interrupt_cause_t.M_EXTERNAL_INTR + ]; + +enum exception_cause_t[] implemented_exception = [ +INSTRUCTION_ACCESS_FAULT, + exception_cause_t.ILLEGAL_INSTRUCTION, + exception_cause_t.BREAKPOINT, + exception_cause_t.LOAD_ADDRESS_MISALIGNED, + exception_cause_t.LOAD_ACCESS_FAULT, + exception_cause_t.STORE_AMO_ADDRESS_MISALIGNED, + exception_cause_t.STORE_AMO_ACCESS_FAULT, + exception_cause_t.ECALL_UMODE, + exception_cause_t.ECALL_SMODE, + exception_cause_t.ECALL_MMODE, + exception_cause_t.INSTRUCTION_PAGE_FAULT, + exception_cause_t.LOAD_PAGE_FAULT, + exception_cause_t.STORE_AMO_PAGE_FAULT +]; \ No newline at end of file