[Intel][MTL][ARL] Improving MC Bus and DDR speed to follow OC SOC

Author: cyring

x86_64/corefreq-api.h

@@ -822,6 +822,8 @@ typedef struct
 			MTL_CAPID_B		MTL_Cap_B;
 			MTL_CAPID_C		MTL_Cap_C;
 			MTL_CAPID_E		MTL_Cap_E;
+			MTL_SA_PERF_STATUS	MTL_SA_Pll;	/* 64 bits    */
+			MTL_PWR_MGMT_BCLK	MTL_BCLK;	/* 64 bits    */
 			MTL_MEMSS_PMA_CR_MEM	MTL_CR_MEM;	/* 32 bits    */
 			MTL_MEMSS_PMA_CR_BIOS	MTL_CR_BIOS;	/* 32 bits    */
 		};

x86_64/corefreqd.c

@@ -6056,15 +6056,20 @@ void MTL_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
 	}
     }
   }
+	/* Clock Topology: BCLK drives the Memory Controller clock domain.
+	 * Qclk ratio with reference of 33.33MHz.			*/
 	RO(Shm)->Uncore.Bus.Rate = \
-		RO(Proc)->Uncore.Bus.MTL_CR_BIOS.REQ.QCLK_RATIO * PRECISION;
+		( RO(Proc)->Uncore.Bus.MTL_CR_BIOS.REQ.QCLK_RATIO
+		* RO(Proc)->Uncore.Bus.MTL_BCLK.PCIE_FREQ_KHZ ) / 3000U;
 
-	RO(Shm)->Uncore.Bus.Rate = RO(Shm)->Uncore.Bus.Rate / 3U;
-
-	RO(Shm)->Uncore.Bus.Speed = (RO(Core)->Clock.Hz
-				* RO(Shm)->Uncore.Bus.Rate)
-				/ RO(Shm)->Proc.Features.Factory.Clock.Hz;
+	/* BCLK_FREQ_0_0_0_MCHBAR is used by software to calculate
+	 * various clock frequencies that are derived from BCLK
+	 * such as Core, Ring, Memory Controller and GT.		*/
+	RO(Shm)->Uncore.Bus.Speed = \
+		( RO(Proc)->Uncore.Bus.MTL_CR_BIOS.REQ.QCLK_RATIO
+		* RO(Proc)->Uncore.Bus.MTL_BCLK.SOC_FREQ_KHZ ) / 3000LLU;
 
+	/* DDR Transfer Rate (MT/s)					*/
 	RO(Shm)->Uncore.CtrlSpeed = 2LLU * RO(Shm)->Uncore.Bus.Speed;
 
 	RO(Shm)->Uncore.Unit.Bus_Rate = MC_MHZ;

x86_64/corefreqk.c

@@ -5632,6 +5632,8 @@ static void Query_ADL_IMC(void __iomem *mchmap, unsigned short mc)
 	EMPTY_STMT();
 }
 
+#define MTL_SA ADL_SA
+
 static void Query_MTL_IMC(void __iomem *mchmap, unsigned short mc)
 {	/* Source: 13th and 14th Gen. Ultra series 1 and 2. Datasheet Vol 2 */
 	unsigned short cha, virtualCount;
@@ -5738,7 +5740,9 @@ static void Query_MTL_IMC(void __iomem *mchmap, unsigned short mc)
 static void Query_MTL_Package_IMC(void __iomem *mchmap, unsigned short mc)
 {
 	Query_Turbo_TDP_Config(mchmap);
+	MTL_SA(mchmap);
  /* Source: Intel Core Ultra 200S and 200HX Series Proc. CFG & MEM Registers */
+	PUBLIC(RO(Proc))->Uncore.Bus.MTL_BCLK.value   = readq(mchmap + 0x5f60);
 	PUBLIC(RO(Proc))->Uncore.Bus.MTL_CR_MEM.value = readl(mchmap + 0x13d00);
 	PUBLIC(RO(Proc))->Uncore.Bus.MTL_CR_BIOS.value= readl(mchmap + 0x13d08);
 }

x86_64/intel_reg.h

@@ -4158,7 +4158,7 @@ typedef union
 	struct {
 		unsigned long long
 		tFAW		:  9-0,  /* Range: 16-88		*/
-		tRRD_SG 	: 15-9,  /* Range:  4-32 | tRRD/tRRD_​L	*/
+		tRRD_SG 	: 15-9,  /* Range:  4-32 | tRRD/tRRD_L	*/
 		tRRD_DG 	: 22-15, /* Range:  4-32	tRRD	*/
 		tRCD		: 30-22,
 		ReservedBits1	: 32-30,
@@ -5323,6 +5323,18 @@ typedef union
 	};
 } MTL_CAPID_E;
 
+#define MTL_SA_PERF_STATUS ADL_SA_PERF_STATUS
+
+typedef union
+{	/* Offset 5F60h BCLK_FREQ_0_0_0_MCHBAR				*/
+	unsigned long long	value;
+	struct {
+		unsigned long long
+		SOC_FREQ_KHZ	: 32-0,
+		PCIE_FREQ_KHZ	: 64-32;
+	};
+} MTL_PWR_MGMT_BCLK;
+
 typedef union
 {	/* Offset 13D00h,  13D04h					*/
 	unsigned int		value;