C1E and HOT?

[gel-crabs]

Hey, I noticed in the Tech section at the bottom of the screen that C1E and HOT are disabled by default (AMD Ryzen)

I have two questions:

Is C1E an Intel-only C-state?

And what does HOT refer to?

[cyring]

Hey, I noticed in the Tech section at the bottom of the screen that C1E and HOT are disabled by default (AMD Ryzen)

I have two questions:

Is C1E an Intel-only C-state?

And what does HOT refer to?

C1E is better documented with Intel: specifications and registers.

With AMD, it is less clear that an enhanced halt state exists ? One EPYC PPR doc is mentioning it but I had to make some assumptions about its working state.

HOT was originally made for Intel hotproc and thermal throttling bits.
This feature has then been enhanced with other Uncore and iGPU event bits, but still of the same kinds, throttling and active limitations. For exemple, current limitation.
HOT is reflecting two event types: spontaneous and historical. That's why you have the ability to clear the event, individually or for all.

Unfortunately I have found no such MSR or CSR Registers with AMD.
The HSMP protocol is specified with a PROCHOT state but I have never been able to test it.
I believe when one is reading PROCHOT the processor is already fried !

Hope I'm providing you some answers.

[cyring]

See also discussion #333 where the HOT feature has been enhanced.