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AMD/Matisse
This is an unsolved issue about counters corruption after resuming processor from S3 (Suspend To Ram).
Looking into the UCC column, delta value of 18446744073709551615, the positive value of -1, let me think that the counter is stuck to reset.
UCC is bound to the x86 register MSR_IA32_APERF
Line 10548 in 07069d5
| MSR_CORE_PERF_UCC, Core->Counter[T].C0.UCC, \ |
The same test on a 5300U does not produce such issue!
Searching among the AMD specification updates has not revealed an errata.
Before S3
After S3
Unexpected workaround
Strangely, the effect tends to disappear over several periods and the MSR_IA32_APERF per CPU starts to count again, with occasional corruptions.
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